🔶 1.

Analog vs Digital | ADC & DAC

​

🔹 Concepts:
●​ Analog: Continuous signals (e.g., sine wave)​

●​ Digital: Discrete binary signals (0s & 1s)​

●​ ADC (Analog to Digital Converter): Converts analog input to digital (e.g.,

successive approximation, flash ADC)​

●​ DAC (Digital to Analog Converter): Converts digital to analog (e.g., weighted

resistor, R-2R ladder)​

✅ YouTube:
●​ 📺 ALL ABOUT ELECTRONICS – ADC & DAC Explained​
●​ 📺 Neso Academy – ADC & DAC numericals​

🔶 2. Number Systems & Binary Codes

🔹 Concepts:
●​ Decimal, Binary, Octal, Hexadecimal conversions​

●​ Binary Arithmetic: Addition, Subtraction (1’s, 2’s complement)​

●​ BCD, Excess-3, Gray Code​

●​ Hamming Code: Error detection & single-bit correction​

✅ YouTube:
●​ 📺 Gate Smashers – Number System Basics + Conversion​
●​ 📺 Neso Academy – Hamming Code (Best Explanation + Examples)​
🔶 3. Logic Gates & Families (RTL, DTL, TTL, ECL)
🔹 Concepts:
●​ Basic Gates: AND, OR, NOT, NAND, NOR, XOR, XNOR​

●​ RTL (Resistor-Transistor Logic)​

●​ DTL (Diode-Transistor Logic)​

●​ TTL (Transistor-Transistor Logic)​

●​ ECL (Emitter-Coupled Logic): Fastest but power hungry​

✅ YouTube:
●​ 📺 Gate Smashers – Logic Families (Detailed + Characteristics)​
●​ 📺 Neso Academy – Digital Logic Gate Operations​

🔶 4. Combinational Logic Design

🔹 Concepts:
●​ Boolean Algebra: Laws & simplification​

●​ Karnaugh Map (K-Map): 2, 3, 4 variable minimization​

●​ SOP & POS​

●​ NAND-NOR universal gates​

●​ Prime Implicants, Minimal Cover​

✅ YouTube:
●​ 📺 Neso Academy – K-Map + Minimal Covering (Top Quality)​
 ●​ 📺 Gate Smashers – Boolean Algebra Simplification + K-map​

🔶 5. MSI & PLD Components

🔹 Concepts:
●​ Half Adder, Full Adder, Subtractor​

●​ Encoder, Decoder​

●​ Multiplexer (MUX) & Demux​

●​ ROM: Fixed memory, used in PLDs​

✅ YouTube:
●​ 📺 Tech Gurukul – MUX/DEMUX/Encoders/Decoders​
●​ 📺 Neso Academy – ROM & Combinational Circuits​

🔶 6. Sequential Logic Design

🔹 Concepts:
●​ Flip-Flops: SR, JK, D, T – Truth Table & Excitation Table​

●​ Registers: Serial-in serial-out, parallel-in parallel-out​

●​ Counters: Ripple counter, synchronous counter​

✅ YouTube:
●​ 📺 Neso Academy – Flip-Flops, Registers, Counters Playlist​
●​ 📺 Gate Smashers – Flip-Flops & Counters with Numericals​
​
MCQS​
​
1. Analog vs. Digital & Number Systems

1.​ An analog signal is:​

a) Discrete in time and amplitude​
b) Continuous in time and amplitude​
c) Discrete in time but continuous in amplitude​
d) Continuous in time but discrete in amplitude​
Answer: b) Continuous in time and amplitude
2.​ The process of converting an analog signal to digital is called:​
a) Modulation​
b) Sampling​
c) Quantization​
d) Both b and c​
Answer: d) Both b and c
3.​ The binary equivalent of decimal 13 is:​
a) 1101​
b) 1011​
c) 1110​
d) 1001​
Answer: a) 1101
4.​ The 2’s complement of binary number 1010 is:​
a) 0101​
b) 0110​
c) 1010​
d) 1101​
Answer: b) 0110 (1’s complement + 1 = 0101 + 1 = 0110)
5.​ BCD code for decimal 7 is:​
a) 0111​
b) 1100​
c) 1001​
d) 1110​
Answer: a) 0111
6.​ Gray code is used for:​
a) Reducing errors in analog signals​
b) Minimizing errors in digital communication​
c) Reducing switching noise in counters​
d) Increasing arithmetic speed​
Answer: c) Reducing switching noise in counters
 7.​ Hamming code is used for:​
a) Data compression​
b) Error detection and correction​
c) Analog-to-digital conversion​
d) Frequency modulation​
Answer: b) Error detection and correction

2. Logic Gates & Logic Families

8.​ Which gate gives output 1 only when all inputs are 1?​
a) OR​
b) AND​
c) NAND​
d) NOR​
Answer: b) AND
9.​ A universal gate is:​
a) AND​
b) OR​
c) NAND​
d) XOR​
Answer: c) NAND
10.​TTL logic family operates at:​
a) Positive voltage only​
b) Negative voltage only​
c) Both positive and negative​
d) High-frequency AC​
Answer: a) Positive voltage only
11.​ECL is faster than TTL because:​
a) It uses MOSFETs​
b) It operates in saturation region​
c) It avoids saturation mode​
d) It has higher power dissipation​
Answer: c) It avoids saturation mode
12.​The fan-out of a logic gate refers to:​
a) Maximum output current​
b) Number of inputs it can drive​
c) Propagation delay​
d) Power consumption​
Answer: b) Number of inputs it can drive
3. Combinational Logic Design

13.​The Boolean expression A + A'B simplifies to:​

a) A + B​
b) A' + B​
c) AB​
d) A'B​
Answer: a) A + B
14.​A Karnaugh map is used to:​
a) Convert analog to digital​
b) Simplify Boolean expressions​
c) Perform binary addition​
d) Store data in memory​
Answer: b) Simplify Boolean expressions
15.​The minimal SOP form of F(A,B) = Σ(0,1,3) is:​
a) A' + B​
b) A + B'​
c) A'B' + AB​
d) A' + B'​
Answer: a) A' + B
16.​A prime implicant is:​
a) A minterm that cannot be combined further​
b) A group of maxterms​
c) A redundant term in K-map​
d) An essential term​
Answer: a) A minterm that cannot be combined further
17.​NAND-NAND implementation is equivalent to:​
a) AND-OR​
b) OR-AND​
c) SOP form​
d) POS form​
Answer: c) SOP form

4. MSI and PLD Components

18.​A full adder has:​

a) 2 inputs, 1 output​
 b) 3 inputs, 2 outputs​
c) 4 inputs, 2 outputs​
d) 3 inputs, 1 output​
Answer: b) 3 inputs (A, B, Cin), 2 outputs (Sum, Cout)
19.​A 4-to-1 multiplexer has:​
a) 2 select lines​
b) 4 select lines​
c) 1 select line​
d) 8 select lines​
Answer: a) 2 select lines (since 2² = 4)
20.​A decoder converts:​
a) Binary to one-hot code​
b) One-hot to binary​
c) Analog to digital​
d) Gray to binary​
Answer: a) Binary to one-hot code
21.​Which is a volatile memory?​
a) ROM​
b) PROM​
c) RAM​
d) EPROM​
Answer: c) RAM
22.​PLD stands for:​
a) Programmable Logic Device​
b) Parallel Logic Design​
c) Pulse Level Detector​
d) Programmable Load Device​
Answer: a) Programmable Logic Device

5. Sequential Logic Design

23.​A flip-flop is a:​

a) Combinational circuit​
b) 1-bit memory element​
c) Analog storage device​
d) Clock generator​
Answer: b) 1-bit memory element
24.​The output of a JK flip-flop toggles when:​
a) J=0, K=0​
b) J=1, K=1​
 c) J=1, K=0​
d) J=0, K=1​
Answer: b) J=1, K=1
25.​A shift register is used for:​
a) Storing binary data​
b) Serial-to-parallel conversion​
c) Counting pulses​
d) Both a and b​
Answer: d) Both a and b
26.​A MOD-10 counter counts up to:​
a) 2​
b) 5​
c) 10​
d) 16​
Answer: c) 10
27.​The excitation table of a D flip-flop has:​
a) D = Q(next)​
b) D = Q(current)​
c) D = Q’​
d) D = Q + Q’​
Answer: a) D = Q(next)

6. Sequential Logic Design (Continued)

28.​In a JK flip-flop, if J=1 and K=0, the output Q will:​

a) Reset to 0​
b) Set to 1​
c) Toggle​
d) Remain unchanged​
Answer: b) Set to 1
29.​A race-around condition occurs in a JK flip-flop when:​
a) J=K=1 and clock pulse is too wide​
b) J=K=0​
c) Clock frequency is very low​
d) Flip-flop is in hold state​
Answer: a) J=K=1 and clock pulse is too wide
30.​The number of flip-flops needed for a MOD-16 counter is:​
a) 2​
b) 4​
c) 8​
d) 16​
Answer: b) 4
 31.​A synchronous counter is better than an asynchronous counter because:​
a) It uses fewer flip-flops​
b) It has no propagation delay issues​
c) It operates at higher speed​
d) Both b and c​
Answer: d) Both b and c
32.​A ring counter with 4 flip-flops has how many unused states?​
a) 4​
b) 8​
c) 12​
d) 16​
Answer: c) 12 (Total states = 16, Used = 4)

7. MSI Components (Adders, Decoders, MUX)

33.​A half-adder has:​

a) 2 inputs, 2 outputs​
b) 2 inputs, 1 output​
c) 3 inputs, 2 outputs​
d) 1 input, 2 outputs​
Answer: a) 2 inputs (A, B), 2 outputs (Sum, Carry)
34.​A 3-to-8 decoder has:​
a) 3 inputs, 8 outputs​
b) 8 inputs, 3 outputs​
c) 2 inputs, 4 outputs​
d) 4 inputs, 16 outputs​
Answer: a) 3 inputs, 8 outputs
35.​A multiplexer is also called:​
a) Data selector​
b) Data distributor​
c) Priority encoder​
d) Demultiplexer​
Answer: a) Data selector
36.​To implement a 16-to-1 MUX, how many 4-to-1 MUXes are needed?​
a) 4​
b) 5​
c) 8​
d) 16​
Answer: b) 5 (Tree structure: 4 MUXes for inputs + 1 for output)
 37.​Which IC is used as a 4-bit parallel adder?​
a) 74138​
b) 74151​
c) 7483​
d) 7474​
Answer: c) 7483

8. Memory & PLDs

The capacity of a ROM with 10 address lines and 8 data lines is:​
a) 10×8 bits​
b) 1024×8 bits​
c) 256×4 bits​
d) 512×16 bits​
Answer: b)

PROM is:​
a) Programmable and erasable​
b) Programmable but not erasable​
c) Non-programmable​
d) Volatile​
Answer: b) Program

The Boolean expression (A+B)(A+C) (A+B)(A+C) simplifies to:​

a) A+BC

b) A+B+C​
c) AB+AC​
d) A⊕B⊕C​
Answer: a)

A 4-bit binary up-counter starts at 0000. After 15 clock pulses, its state will be:​
a) 0000​
b) 1111​
c) 1010​
d) Undefined​
Answer: b) 1111

Which logic family is immune to latch-up?​

a) TTL​
b) ECL​
c) CMOS​
d) DTL​
Answer: b) ECL

The Gray code for binary 1101 is:​

a) 1011​
b) 1110​
c) 1001​
d) 1100​
Answer: a) 1011

A priority encoder outputs:​

a) The binary code of the highest-priority active input​
b) The parity of input bits​
c) The sum of all inputs​
d) A one-hot code​
Answer: a) The binary code of the highest-priority active input

The hold time of a flip-flop is the time during which:​

a) Input must remain stable after the clock edge​
b) Input must remain stable before the clock edge​
c) Clock must remain high​
d) Output is invalid​
Answer: a) Input must remain stable after the clock edge

A PAL (Programmable Array Logic) has:​

a) Programmable AND + fixed OR arrays​
b) Programmable OR + fixed AND arrays​
c) Fully programmable AND/OR arrays​
d) Only NAND gates​
Answer: a) Programmable AND + fixed OR arrays

The resolution of a 12-bit DAC with a 10V reference is approximately:​

a) 2.44 mV​
b) 5 mV​
c) 10 mV​
d) 1.22 mV​
Answer: a)

A Mealy machine differs from a Moore machine in that:​

a) Mealy outputs depend only on the current state​
b) Moore outputs depend on inputs and state​
c) Mealy outputs depend on inputs and state​
d) Moore outputs are asynchronous​
Answer: c) Mealy outputs depend on inputs and state

The Excess-3 code for decimal 6 is:​

a) 1001​
b) 1100​
c) 0110​
d) 1111​
Answer: a) 1001 (Binary(6+3) = 1001)

A ripple counter’s maximum frequency is limited by:​

a) The number of flip-flops​
b) The propagation delay of each flip-flop​
c) The clock pulse width​
d) The power supply voltage​
Answer: b) The propagation delay of each flip-flop

The minimal SOP form of F(A,B,C)=Σ(0,2,4,5)is:​

a) A′C′+AB′​
b) A′B′+AC​
c) B′C′+A′B​
d) A⊕B⊕C​
Answer: a)

A 3-line to 8-line decoder can be used to implement:​

a) Any 3-input Boolean function​
b) Only SOP functions​
c) Only POS functions​
d) Sequential logic​
Answer: a) Any 3-input Boolean function

The Hamming distance between 101101 and 100001 is:​

a) 1​
b) 2​
c) 3​
d) 4​
Answer: b) 2 (XOR: 001100 → 2 bits differ)

A JK flip-flop in toggle mode (

J=K=1
 J=K=1) changes state:​
a) On the rising clock edge​
b) On the falling clock edge​
c) After a propagation delay​
d) Only if reset is high​
Answer: a) On the rising clock edge

The fan-out of a CMOS gate is typically higher than TTL because:​

a) CMOS has lower input current​
b) CMOS operates at higher voltage​
c) TTL has faster switching​
d) CMOS uses bipolar transistors​
Answer: a) CMOS has lower input current

A 4-bit ALU can perform:​

a) Only arithmetic operations​
b) Only logic operations​
c) Both arithmetic and logic operations​
d) Only shift operations​
Answer: c) Both arithmetic and logic operations

The minimal POS form of

F(A,B)=Π(1,3)

F(A,B)=Π(1,3) is:​
a) A′+B​
b) A+B′

c) (A+B)(A′+B)​
d) A⊕B​
Answer: c)

12. Number Systems & Codes (Advanced)

56.​The hexadecimal equivalent of binary 11010110 is:​

a) D6​
b) 6D​
c) 2B​
d) B2​
Answer: a) D6
 57.​The 1’s complement representation of -7 in 4 bits is:​
a) 0111​
b) 1000​
c) 1111​
d) 1010​
Answer: b) 1000
58.​Which code represents the decimal digit 5 in Excess-3 code?​
a) 1000​
b) 1010​
c) 1100​
d) 0111​
Answer: a) 1000 (Excess-3 = Binary(5+3) = 1000)
59.​The Gray code for binary 1010 is:​
a) 1010​
b) 1111​
c) 1100​
d) 1110​
Answer: b) 1111
60.​Hamming code is a:​
a) Error-detecting code​
b) Error-correcting code​
c) Data compression code​
d) Encryption code​
Answer: b) Error-correcting code

13. Combinational Circuits (Advanced)

61.​A 4-bit parallel adder uses:​

a) 4 half-adders​
b) 1 half-adder + 3 full-adders​
c) 4 full-adders​
d) 2 half-adders + 2 full-adders​
Answer: c) 4 full-adders
62.​The Boolean function F = A ⊕ B ⊕ C represents:​
a) Odd parity generator​
b) Even parity generator​
c) Multiplexer​
d) Decoder​
Answer: a) Odd parity generator
 63.​A BCD-to-7-segment decoder has:​
a) 4 inputs, 7 outputs​
b) 7 inputs, 4 outputs​
c) 3 inputs, 8 outputs​
d) 8 inputs, 3 outputs​
Answer: a) 4 inputs, 7 outputs
64.​The output of an 8:1 MUX with inputs I0=1, I1=0, I2=1, and select lines
S2S1S0=101 is:​
a) 0​
b) 1​
c) Undefined​
d) Toggles​
Answer: b) 1 (I5 is selected, which is 1 in this case)
65.​Which circuit converts binary to Gray code?​
a) Encoder​
b) Decoder​
c) XOR gates​
d) Multiplexer​
Answer: c) XOR gates

14. Sequential Circuits (Advanced)

66.​A master-slave flip-flop is used to avoid:​

a) Race condition​
b) Hold violation​
c) Setup time issues​
d) Power dissipation​
Answer: a) Race condition
67.​In a D flip-flop, if D=1 and clock rises, Q becomes:​
a) 0​
b) 1​
c) Toggles​
d) Remains unchanged​
Answer: b) 1
68.​A MOD-5 counter requires minimum:​
a) 2 flip-flops​
b) 3 flip-flops​
c) 4 flip-flops​
 d) 5 flip-flops​
Answer: b) 3 flip-flops (since
69.​A 3-bit ripple counter has a maximum delay of:​
a) 1 × propagation delay​
b) 2 × propagation delay​
c) 3 × propagation delay​
d) No delay​
Answer: c) 3 × propagation delay
70.​A Johnson counter with 5 stages has how many states?​
a) 5​
b) 10​
c) 25​
d) 32​
Answer: b) 10

15. Logic Families & Characteristics

71.​Which logic family has the highest power dissipation?​

a) TTL​
b) CMOS​
c) ECL​
d) RTL​
Answer: c) ECL
72.​Fan-out of CMOS is higher than TTL because:​
a) CMOS has lower input current​
b) CMOS has higher output voltage​
c) TTL has faster switching​
d) CMOS uses MOSFETs​
Answer: a) CMOS has lower input current
73.​Noise margin is highest in:​
a) TTL​
b) ECL​
c) CMOS​
d) DTL​
Answer: c) CMOS
74.​The typical propagation delay of TTL is:​
a) 1–10 ns​
b) 50–100 ns​
c) 1–10 µs​
 d) 100–200 ps​
Answer: a) 1–10 ns
75.​Which is not a bipolar logic family?​
a) TTL​
b) ECL​
c) CMOS​
d) DTL​
Answer: c) CMOS

16. Memory & Programmable Logic

76.​The address range of a 1K × 8 memory is:​

a) 000H–FFFH​
b) 000H–3FFH​
c) 000H–7FFH​
d) 000H–1FFFH​
Answer: b) 000H–3FFH
77.​Which memory is erasable using UV light?​
a) PROM​
b) EPROM​
c) EEPROM​
d) SRAM​
Answer: b) EPROM
78.​PLA consists of:​
a) AND + OR arrays​
b) NAND gates only​
c) Flip-flops​
d) ADC/DAC​
Answer: a) AND + OR arrays
79.​FPGA stands for:​
a) Fast Programmable Gate Array​
b) Field-Programmable Gate Array​
c) Flexible Programmable Gate Array​
d) Floating-Point Gate Array​
Answer: b) Field-Programmable Gate Array
80.​Which is volatile memory?​
a) ROM​
b) PROM​
c) SRAM​
 d) EPROM​
Answer: c) SRAM

17. ADC/DAC & Mixed Topics

81.​The resolution of a 10-bit DAC with 5V full scale is:​

a) 5 mV​
b) 10 mV​
c) 4.88 mV​
d) 2.44 mV​
Answer: c)
82.​Successive approximation ADC is slower than:​
a) Dual-slope ADC​
b) Flash ADC​
c) Sigma-delta ADC​
d) All of the above​
Answer: b) Flash ADC
83.​Which ADC is best for high-noise environments?​
a) Flash​
b) Dual-slope​
c) SAR​
d) Pipeline​
Answer: b) Dual-slope
84.​In a weighted resistor DAC, the largest resistor corresponds to:​
a) MSB​
b) LSB​
c) Mid-range bit​
d) Ground​
Answer: b) LSB
85.​A sample-and-hold circuit is used in ADC to:​
a) Reduce quantization error​
b) Stabilize input during conversion​
c) Increase resolution​
d) Decrease power consumption​
Answer: b) Stabilize input during conversion

18. Error Detection & Correction

 86.​The Hamming code for 4 data bits requires:​
a) 2 parity bits​
b) 3 parity bits​
c) 4 parity bits​
d) 5 parity bits​
Answer: b) 3 parity bits
87.​CRC is used for:​
a) Error correction​
b) Error detection​
c) Data compression​
d) Encryption​
Answer: b) Error detection
88.​The generator polynomial in CRC must have:​
a) 0 as the MSB and LSB​
b) 1 as the MSB and LSB​
c) Only even powers​
d) No restrictions​
Answer: b) 1 as the MSB and LSB
89.​The checksum method is used in:​
a) Ethernet frames​
b) IP packets​
c) UDP headers​
d) All of the above​
Answer: d) All of the above

19. Advanced Sequential Circuits

91.​A Mealy machine’s output depends on:​

a) Current state only​
 b) Input only​
c) Both input and current state​
d) Clock edge​
Answer: c) Both input and current state
92.​A synchronous reset in a flip-flop is activated:​
a) Only at clock edge​
b) Anytime reset is high​
c) Independent of clock​
d) After a delay​
Answer: a) Only at clock edge
93.​A 4-bit shift register operating in circular mode will repeat its output after:​
a) 1 clock cycle​
b) 4 clock cycles​
c) 8 clock cycles​
d) 16 clock cycles​
Answer: b) 4 clock cycles
94.​The minimum number of flip-flops for a MOD-12 counter is:​
a) 3​
b) 4​
c) 12​
d) 16​
Answer: b) 4
95.​A glitch in a counter is caused by:​
a) Incorrect clock frequency​
b) Propagation delay​
c) Power supply noise​
d) High temperature​
Answer: b) Propagation delay

20. Final Mixed Questions

96.​Which is a universal shift register IC?​

a) 74194​
b) 7486​
c) 7404​
d) 7432​
Answer: a) 74194
97.​The minimal NAND-NAND implementation of F=AB+CD is:​
a) NAND(NAND(A,B), NAND(C,D))​
b) NAND(A,B,C,D)​
c) NAND(A,B) + NAND(C,D)​
d) NAND(AB, CD)​
Answer: a) NAND(NAND(A,B), NAND(C,D))
98.​The fastest logic family among the following is:​
a) TTL​
b) CMOS​
c) ECL​
d) RTL​
Answer: c) ECL