Gujarat Technological University

C.K.Pithawala College Of Engineering & Technology, Surat

Computer Engineering Department
B.E.II (3rd Sem)
Subject Name: Digital Fundamental
Subject Code: 3130704 [3-0-2]

Question Bank

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Module1
1. Convert decimal number (43)10 to binary.

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2. Convert octal number (234)8 to hexadecimal
3. Convert decimal number (0.252)10 to binary with an error less than 1 %.

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4. find the value of x if (16)10=(100)X
5. Add (6E)16 and (C5)16
6. Find (4433)5 = ( )10 = ( )2
7. (1011011101101110)2=(___)16
8. Subtract (45)8 from (66)8
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9. Covert the Gray code 1101 to binary
10. Find the XS-3 code of 37
11. Convert (75)10 = (___________)2
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12. Convert (101011)2 = (_________)10

13. Convert (10101101)2 = (___________)16 = (__________)8
14. Convert the binary number 1001.00102 to decimal.
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15. Minimize the following Boolean expressions.

1. X = ( (A'B'C')' + (A'B)' )'
2. Y = AB + ABC' + A'BC + A'BC'
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16. If a 3-input NOR gate has eight input possibilities, how many of those possibilities
will result in a HIGH output?
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17. If a signal passing through a gate is inhibited by sending a LOW into one of the
inputs, and the output is HIGH, the gate is
18. When used with an IC, what does the term "QUAD" indicate _____ circuits
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19. Represent (472)10 in 2421 self complementing code.

20. Convert (96)10 to its equivalent gray code and EX-3 code
21. Perform addition in BCD format (79)BCD + (16)BCD
22. Minimize the following logic function using K-maps and realize using NAND and
NOR gates.
23. F(A,B,C,D) =Em(1,3,5,8,9,11,15) + d(2,13)
24. Reduce the given function using K-map and implement the same using gates
25. F(A,B,C,D)=Em (0,1,3,7,11,15) + Ed ( 2,4)
26. Minimize following Boolean function using Kmap& design the simplified
function using logic gates.
27. F(A,B,C,D) = Em(1, 2, 4, 6, 7, 11, 15) + Ed(0, 3)
28. Reduce the expression F = Em(0,2,3,4,5,6) using K-map and implement using
NAND gates only
29. Minimise the logic function F(A,B,C,D)=π (1, 2, 3, 8, 9, 10). d (7, 15)

Use Karnaugh map. Draw the logic circuit for the simplified function using NOR
gates only.

30. Draw & explain in brief pin diagram of 7485 four-bit magnitude comparator.
31. Design a full adder using 3X8 decoder followed by gates
32. Design a BCD to excess 3 code converter using minimum number of NAND gates
33. Design a circuit for 2-bit magnitude comparator

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34. Design 4 bit binary to gray code converter
35. Design 3-bit even parity generator circuit
36. Convert F (A, B, C) = BC +A into standard minterm form
37. A combinational circuit has 3 inputs A, B, C and output F. F is true for following

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input combinations
i. A is False, B is True

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ii. A is False, C is True
iii. A, B, C are False

(i)
iv. A, B, C are True S
Write the Truth table for F. Use the convention True=1 and False = 0.
(ii) Write the simplified expression for F in SOP form.
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(iii) Write the simplified expression for F in POS form.
(iv) Draw logic circuit using minimum number of 2-input NAND gates.
38. Draw the truth table of full adder and implement using minimum number of logic
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gates.
39. Perform subtraction of (78)10 - (58)10 using 2’s complement method.
40. Draw the truth table of full subtractor and implement using minimum number of
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logic gates.
41. Explain the working of multiplexer
42. Design 4 X 16 decoder using two 3 X 8 decoder.
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43. Simplify using Boolean laws and draw the logic diagram for the given expression
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44. Prove the following Boolean identities.

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45. Implement the given function using 8 X 1 Multiplexer

46. F (A,B,C,D) = Em (0,1,2,3,5,8,9,11,14)
47. Explain DeMorgan’s Theorem with necessary truth table. Prove that

48. Translate the following algebra into its logic equivalent and comment on the
necessity of simplification.
 49. Simplify the following.

50. Using K-map technique simplify the following using minimum numbers of gates.
F=m0+m1+m4+m6+m8+m9+m12+m14
51. Apply De Morgan’s theorem to solve the following.

52. What are SOP and POS forms of boolean expressions? Minimize the following
expression using K-MAP.
Y= Σm(0,1,5,9,13,14,15) + d( 3,4,7,10,11)

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Module 2
1. Design a 4 bit BCD adder using IC7483 and gates.
2. Minimize the following logic function using K-maps and realize using NAND or NOR gates.

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1. F(A,B,C,D) =Em(1,3,5,8,9,11,15) + d(2,13)
2. F(A,B,C,D)=Em (0,1,3,7,11,15) + Ed ( 2,4)

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3. F(A,B,C,D) = Em(1, 2, 4, 6, 7, 11, 15) + Ed(0, 3)
3. Design the parity generator and checker for odd parity.

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4. Draw the truth table of full subtractor and implement using minimum number of logic gates.
5. Design 4 X 16 decoder using two 3 X 8 decoder.
6. Implement the given function using 8 X 1 Multiplexer
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F (A,B,C,D) = Em (0,1,2,3,5,8,9,11,14)
7. What are SOP and POS forms of boolean expressions? Minimize the following expression
using K-MAP.
a. Y= Σm(0,1,5,9,13,14,15) + d( 3,4,7,10,11)
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8. Explain the working of decoder.

9. Implement the given function using 4 X 1 Multiplexer
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F (A,B,C,D) = Em (1,3,5,6)
10. Draw the truth table of full adder and implement using minimum number of logic gates.
11. Design the parity generator and checker for Even parity.
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12. Design a 4 bit BCD adder using IC7483 and gates.

13. Implement the given function using 4 X 1 Multiplexer
F (A,B,C,D) = Em (0,1,3,4,8,9,15)
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14. What are SOP and POS forms of boolean expressions? Minimize the following expression
using K-MAP.
a. Y= Σm(0,1,5,9,13,14,15) + d( 3,4,7,10,11)
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15. Design the parity generator and checker for odd parity.
16. Design 4 X 16 decoder using two 3 X 8 decoder.
17. Design a 4 bit BCD adder using IC7483 and gates.
18. Reduce the expression F = Em(0,2,3,4,5,6) using K-map and implement using NAND gates
only
19. Minimise the logic function F(A,B,C,D)=π (1, 2, 3, 8, 9, 10). d (7, 15).Use Karnaugh map.
Draw the logic circuit for the simplified function using NOR gates only.
Module 3
1. For the figures 1, 2, & 3, plot the output waveforms referenced to the clock signal assuming
the initial contents of all FFs is Q = 0. Assume all FFs are edge triggered.

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2. How SR flip flop’s invalid output is solved with JK flip flop?
3. Give the comparison between synchronous and asynchronous counters.
4. With neat sketch design 4-bit bidirectional shift register.
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5. Implement T flip flop using D flip flop.

6. With logic diagram explain the operation of 4 bit binary ripple counter. How up counter can
be converted into down counter?
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7. Design a mod-12 Synchronous up counter using D-flip flop.

8. In the given figure initially X=0, A=1 and B=1 is available, the input B is now replaced with a
sequence 101010…, Determine the output X and Y.
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9. Draw the graphical symbols of D latch and JK flip flop.

10. Distinguish between combinational and sequential logic circuits. Give the applications of flip-
flops.
11. Convert D flip flop into SR flip flop.
12. Design a circuit for 4-bits parallel register with load with D Flip-Flops. Load input
decides whether to load new input or to apply no change conditions.
13. Draw a frequency divider using JK FFs to divide input clock frequency by a factor of 8.
14. Design and Implement a Mod-10 synchronous counter with T FF.
15. Draw the output waveforms, if the inputs are as shown in fig. 1 for the circuit given in fig. 2
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Fig 1

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Fig 2
16. Draw the circuit of D flip flop with synchronous clear input.
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17. Explain asynchronous input in Flip flop.

18. Implement D flip flop using JK flip flop.
19. Write short note on four bit Universal Shift Register.
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20. Design and Implement a Mod-10 asynchronous counter with T FF.

21. Design a synchronous BCD counter with JK flip flops.
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Module 4
1. Explain the operation of basic sample and hold circuit.
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2. Define Resolution, Accuracy, Monotonicity, conversion time in DAC.

3. Explain flash type ADC with its advantages and disadvantages.
4. Explain counting A to D converter.
5. What do you mean by step size and full scale output in DAC.
6. Explain binary weighted resistor technique of D/A conversion with its advantages and
disadvantages.
7. Define start of conversion and end of conversion in ADC.
8. Explain Successive approximation type ADC with its advantages and disadvantages.
9. Discuss A/D converter using voltage to frequency conversion.
10. List the different D/A converter IC
11. Explain R-2R ladder DAC with advantages and disadvantages.
12. Explain Dual slop ADC with its advantages and disadvantages.
13. List specifications of ADC.
14. Explain A to D converter with voltage to time conversion.

Module 5
1. Write short note on ROM
2. List out the various types of ROMs and discuss any two of them
3. Design a 3-bit gray to binary code converter. Implement it using suitable PROM.
4. Explain PLA in details with necessary diagrams
5. Write short note on FPGA

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6. Compare RAM and ROM
7. Obtain 2048 x 8 memory using 256 x 8 memory chips.
8. Draw and explain in detail the block diagram of CPLD.

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9. Explain classification of Memories.
10. A combinational circuit is defined by the function F1 (A, B, C,) = Σ m (4, 5, 7)
F2 (A, B, C,) = Σ m (3, 5, 7) Implement the circuit with a PLA having 3 inputs, 3

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product term & 2 outputs.
11. Compare SRAM with DRAM
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12. Draw and explain in brief block diagram of CPLD. Also compare CPLD with FPGA.
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