PART A - Short Answers (1 Mark Each)

Q.1: Differentiate between BCD and binary system.

• BCD (Binary-Coded Decimal): Represents each decimal digit (0-9) as a 4-bit binary.
• Binary System: Represents numbers using base-2 (0 and 1) in a continuous binary format.

Q.2: What is DeMorgan’s Theorem?

• DeMorgan’s Theorem states:
1. (A.B)’ = A’ + B’ (AND to OR with complement).
2. (A + B)’ = A’.B’ (OR to AND with complement).

Q.3: What is K-map?

• K-map (Karnaugh Map) is a graphical method to simplify Boolean expressions and minimize
logic circuits.

Q.4: Give few examples of sequential circuits.

• Flip-Flops, Counters, Shift Registers, Latches.

Q.5: What is an excitation table?

• An excitation table shows the inputs required to transition from the current state to the
next state in sequential circuits.

Q.6: Define 1’s and 2’s complements in digital electronics.

• 1’s complement: Invert all bits (0→1, 1→0).
• 2’s complement: Add 1 to the 1’s complement result.

Q.7: What do you mean by RAM?

• RAM (Random Access Memory) is a volatile memory used to store data temporarily while
the computer is operating.

Q.8: What are the universal gates?

• NAND and NOR gates are universal gates because they can implement any Boolean function.
Q.9: Define Flip Flop.
• A Flip-Flop is a bistable device that stores one bit of data and has two states: SET (1) and
RESET (0).

Q.10: What is half subtractor circuit?

• A Half Subtractor performs subtraction of two binary digits and provides Difference and
Borrow outputs.

PART B - Answers (3 Marks Each)

Q.11: Convert (10010)₂ into decimal equivalent number.

To convert binary to decimal:
(10010)2 = 1 x 24 +0 x 23+ 0 x 22+1 x 21+0 x 20
=16+0+0+2+0=18
Q.12: Differentiate between synchronous and asynchronous counter.
1. Synchronous Counter: All flip-flops are triggered by the same clock signal simultaneously.
• Faster and avoids timing delays.
2. Asynchronous Counter: Flip-flops are triggered by different clock signals (output of one FF
drives the next).
• Slower and prone to propagation delays.

Q.13: Define SOP and POS.

• SOP (Sum of Products): Logical expression is the sum of ANDed terms (e.g., ABC + A’B’C).
• POS (Product of Sums): Logical expression is the product of ORed terms (e.g.,
(A+B+C)(A’+B’+C’)).

Q.14: Draw the excitation table for T-flip flop.

Current State (Qn) Input T Next State (Qn+1)

0 0 0
0 1 1
1 0 1
1 1 0
Explanation:
• When T = 0, state remains the same.
• When T = 1, the state toggles.

Q.15: Explain race-around condition in J-K Flip Flop.

• Race-around condition occurs when the input J=K=1 and the clock pulse remains HIGH for a
long time.
• The output toggles continuously, leading to instability.
• Solution: Use Master-Slave Flip-Flop or Edge-triggered Flip-Flop to avoid this issue.

Q.16: What are the advantages of EEPROM?

1. Non-volatile memory (retains data after power-off).
2. Can be erased and reprogrammed electrically.
3. Supports byte-wise erasing and writing.

Q.17: Explain clearly the differences between RAM and ROM.

RAM ROM
Volatile memory. Non-volatile memory.
Data can be read and written. Data can only be read (programmed).
Used for temporary storage. Used for permanent storage.

Q.18: Explain the advantages and disadvantages of dynamic RAM.

• Advantages:
1. High storage density.
2. Cost-effective and simple structure.
• Disadvantages:
1. Requires refreshing to retain data.
2. Slower compared to SRAM.
Q.19: Write the truth table of JK Flip Flop.

J K Qn (Current State) Qn+1 (Next State)

0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0

Explanation:
• J = 1, K = 1 → Toggle state.

Q.20: What do you mean by a Demultiplexer?

• A Demultiplexer (DEMUX) takes a single input and channels it to one of the multiple outputs
based on control (select) signals.
• Example: 1-to-4 Demux distributes input data to 4 outputs.
PART C - Detailed Answers (5 Marks Each)

Q.21: Explain the concept of virtual memory in detail.

• Virtual Memory is a memory management technique where a part of the secondary storage
(e.g., hard disk) is used as extended RAM.
• It allows programs larger than the available physical memory to run efficiently by creating
an illusion of a large, contiguous memory space.
• Working:
1. The operating system divides memory into pages (fixed-size blocks).
2. Pages that are currently not in use are stored on the hard disk.
3. When needed, these pages are loaded back into RAM.
• Advantages:
1. Allows multitasking by sharing memory between processes.
2. Enables large programs to run even with limited RAM.
 • Disadvantages:
1. Slower due to disk access.
2. Excessive swapping can cause thrashing (system slowdown).

Q.22: Design a 3-bit asynchronous up counter and explain its working.

• A 3-bit asynchronous counter uses 3 Flip-Flops connected in series.
• Each Flip-Flop toggles on the negative edge of the previous Flip-Flop’s output.

Diagram: 3-Bit Asynchronous Counter

1. Connect JK Flip-Flops with J=1 and K=1.
2. Clock signal is applied to the first Flip-Flop only.

Truth Table:

Clock Pulse Q2 Q1 Q0
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1

Working:
• Q0 toggles with every clock pulse.
• Q1 toggles on Q0’s falling edge, and Q2 toggles on Q1’s falling edge.
• The counter counts from 0 to 7 (3-bit binary count).

Q.23: Design 8:1 multiplexer using 2:1 multiplexer and explain its working.
• 8:1 MUX selects one out of 8 inputs based on 3 select lines (S2, S1, S0).
• To implement it, use 7 units of 2:1 MUX.
Diagram:
1. Combine four 2:1 MUXes in the first stage to reduce 8 inputs to 4.
2. Use two 2:1 MUXes in the second stage to reduce 4 inputs to 2.
3. Use the final 2:1 MUX to produce a single output.

Working:
• Inputs: D0-D7, Select Lines: S2, S1, S0.
• S2 determines the MUX at the final stage, while S1 and S0 control the intermediate stages.
• Based on select lines, the corresponding input is passed to the output.

Q.24: Design BCD to 7-segment decoder circuit.

• A BCD to 7-segment decoder converts Binary-Coded Decimal (BCD) input to drive a 7-
segment display.

Segments: The display has 7 LEDs labeled a, b, c, d, e, f, g.

Truth Table:

BCD (Input) a b c d e f g
0000 (0) 1 1 1 1 1 1 0
0001 (1) 0 1 1 0 0 0 0
… … … … … … … …

Working:
• Logic gates are designed to activate specific segments based on the input BCD code.
• For example, when BCD = 0000, segments a, b, c, d, e, f are turned ON.

Q.25: What is a multiplexer? Draw the logic diagram of 8-to-1 line multiplexer.
• A Multiplexer (MUX) selects one input from multiple inputs based on the control (select)
signals.
• 8:1 MUX has 8 inputs (D0-D7), 3 select lines (S2, S1, S0), and 1 output (Y).
Logic Diagram:
1. Use 3 control lines S2,S1,S0 to select the active input.
2. Outputs are connected through AND gates and combined using an OR gate.

Equation:
Y= S2’S1’S01D0+S2’S1’S0D1+S2S1S0D7

Working:
• Depending on the combination of S2,S1,S0, the corresponding input is routed to the
output.

Q.26: What is D Flip Flop? Draw the logic diagram for it using NAND gates only. Also, write the truth table
for it.
• D Flip-Flop: Transfers the input D to the output Q on a clock edge.

NAND Gate Design:

1. Use 4 NAND gates to form the latch.
2. Add clock-controlled gates to enable input D.

Truth Table:

D Clock Q (Next State)

0 ↑ 0
1 ↑ 1

Working:
• When the clock pulse is HIGH, the value of D is transferred to Q.

Q.27: Briefly explain JK Flip Flop. What are the advantages of JK Flip Flop over SR Flip Flop?
• JK Flip-Flop:
It is a modified version of the SR Flip-Flop where the undefined state (S = 1, R = 1) is eliminated.
• Inputs: J (Set), K (Reset), and a Clock.
• Behavior:
 1. J = 0, K = 0 → No change (hold state).
2. J = 0, K = 1 → Reset (Q = 0).
3. J = 1, K = 0 → Set (Q = 1).
4. J = 1, K = 1 → Toggle (Q flips state).

Advantages of JK Flip-Flop over SR Flip-Flop:

1. The undefined condition (S = R = 1) of SR Flip-Flop is resolved in JK Flip-Flop by toggling the
output.
2. It is more versatile because it can perform Set, Reset, Hold, and Toggle operations.
3. Widely used in counters and control circuits.

Q.28: Differentiate synchronous and asynchronous sequential logic circuit.

Synchronous Sequential Logic Asynchronous Sequential Logic

Uses a clock signal to synchronize state changes. State changes occur based on input changes
without a clock.
Easier to design and implement. More complex due to timing issues.
Less prone to hazards and glitches. Prone to races, hazards, and glitches.
Examples: Counters, Shift Registers. Examples: Handshaking circuits, event
detectors.

Explanation:
• Synchronous circuits are reliable as they operate with a common clock, while asynchronous
circuits depend on input changes and delays.

Q.29: What do you mean by a half adder? Design a half adder using NAND gates only.
• Half Adder: A combinational circuit that performs the addition of two binary inputs A and B,
producing Sum and Carry outputs.

Truth Table:

A B Sum (S) Carry (C)

0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Logic Equations:
• S= A (XOR SIGN) B (XOR operation).
• C= A . B(AND operation).

Half Adder Using NAND Gates:

1. XOR operation (Sum) can be implemented using 4 NAND gates.
2. AND operation (Carry) can be implemented using 2 NAND gates.

Diagram: Use six NAND gates to implement Sum and Carry.

Q.30: Draw the basic circuit of ROM cell and explain its working.
• ROM (Read-Only Memory): A non-volatile memory that stores data permanently during
manufacturing or programming.

Basic Circuit of ROM Cell:

1. ROM is built using an array of diodes or transistors arranged in rows and columns.
2. Each intersection (cell) can either store a 1 or a 0 based on its connectivity.

Working:
• A decoder activates one row (word line) based on the address input.
• The corresponding column (bit line) reads the stored value (0 or 1).

Advantages of ROM:
1. Non-volatile (retains data without power).
2. Fast read access.
3. Used for firmware and permanent data storage.