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Assignment 3

The document outlines the course details for VLSI Design, including modules focused on synchronous and asynchronous resets, flip-flops, dynamic shift registers, CMOS logic, RAM cells, and design for testability. Each module contains specific topics that require explanations, diagrams, and circuit designs. The course aims to provide a comprehensive understanding of VLSI design principles and testing methodologies.

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Shweta Kulkarni
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6 views2 pages

Assignment 3

The document outlines the course details for VLSI Design, including modules focused on synchronous and asynchronous resets, flip-flops, dynamic shift registers, CMOS logic, RAM cells, and design for testability. Each module contains specific topics that require explanations, diagrams, and circuit designs. The course aims to provide a comprehensive understanding of VLSI design principles and testing methodologies.

Uploaded by

Shweta Kulkarni
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Department of Electronics & Communication Engineering

Name of the Course :VLSI Design Course Code: 18EC72

Sem/Sec: VII Astrosat Faculty Name: Swetha Kulkarni

MODULE-4
1. With necessary circuit diagrams explain the resettable i) synchronous reset ii)
asynchronous reset. [K2]
2. With necessary diagrams explain a D-flipflop with two phases non overlapping clocks .
[K2]
3. With necessary circuit diagram explain 3-bit dynamic shift register with enhancement
load [K2]
4. Realize A1A2A3+B1B2 using dynamic CMOS logic. [K4]
5. Explain the general structure of ratioless synchronous dynamic logic with relevant
diagram. [K2]
6. Discuss on Domino CMOS logic. [K3]
7. Using CMOS transmission gate Explain resettable latches and flip-flops. [K4]
8. Using equations explain charge storage and charge leakage in dynamic logic. [K4]
9. Discuss about cascading problem in dynamic circuits. [K3]
10. Draw and explain the functioning of pulse generators. [K4]
11. Explain dynamic synchronous CMOS transmission gate with necessary diagrams. [K2]
12. Explain conventional CMOS flip flops with neat diagrams. [K2]
13. With neat circuit diagram explain 4 transparent latches. [K3]

MODULE-5
1. With necessary diagrams explain the operation of three transistor dynamic RAM cell .
[K3]
2. Explain full CMOS static RAM with schematic diagram. [K2]
3. Draw the diagram of 4bit x 4bit NOR based ROM array, explain the functioning. [K4]
4. With a neat logic diagram explain delay in multistage logic networks. [K2]
5. With neat diagram explain any 3 static RAM circuits. [K3]
6. Mention the approaches used in design for testability. Explain scan based testing
using necessary diagrams. [K3]
7. Sketch the circuit of 3-bit BIST register and explain. [K4]
8. State the terms i) Observability ii) Controllability iii) Fault coverage. [K4]
9. What is fault model. Explain stuck at model with examples. [K3]
10. Using block diagram Discuss briefly on logic verification principle. [K4]
11. Explain manufacturing test principle in detail. [K2]
12. Illustrate briefly on design for testability. [K3]
13. Explain CMOS bridging fault with necessary example. [K2]
14. Write short notes on Scan design technology. [K4]

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