Sure!
Let's walk through a **practical example** of the **PCI Express (PCIe) link
training process** described in your detailed explanation, from the point of view
of a **downstream-facing port (host/root complex)** trying to link up with an
**upstream-facing port (device/endpoint)**, such as a graphics card or NVMe SSD.
---
## 🧩 Scenario
* **Host (root complex)** supports: **x4 lanes**, PCIe Gen 3 (8 GT/s)
* **Device (endpoint)** supports: **x4 lanes**, PCIe Gen 2 (5 GT/s)
* Initial speed: **2.5 GT/s (Gen 1)** — the default safe speed
* Goal: Establish a **x4 link**, then possibly upgrade the speed to the **highest
common rate** (Gen 2 = 5 GT/s)
---
## Step-by-Step Walkthrough
### 🔍 1. **Detect State**
* Both host and device detect electrical presence on their lanes.
* LTSSM (Link Training and Status State Machine) transitions to **Polling**.
---
### 🔄 2. **Polling and Configuration.Linkwidth.Start**
* Host begins sending **TS1 (Training Set 1)** ordered sets:
* **Link Number:** 10 (arbitrary number from 0–31)
* **Lane Number (PAD):** not yet assigned
* It transmits these on all 4 lanes.
* Device receives TS1s, checks the Link Number, and if it matches, **echoes them
back** with the same Link Number and PAD.
✅ **Condition met:** Two consecutive TS1s received with matching Link Number on any
lane.
---
### 🔧 3. **Configuration.Linkwidth.Accept**
* Host observes that TS1s with the matching Link Number are coming back on **lanes
0–3**.
* So it decides: "Great! I can form a full x4 link."
* It **assigns Lane Numbers 0–3** to lanes 0–3 respectively.
---
### 📦 4. **Configuration.Lanenum.Wait**
* Host now sends TS1s with:
* **Link Number = 10**
* **Lane Numbers = 0, 1, 2, 3** for respective lanes
* Device now **echoes back** TS1s with the same Link and Lane Numbers — but **may
take up to 1ms** due to skew or internal delays.
✅ **Condition met:** Two TS1s received with the updated Lane Numbers on any lane.
---
### 🔁 5. **Configuration.Lanenum.Accept**
* Host checks if the echoed Lane Numbers match what it sent.
* If they match → Proceed
* If the device sent reversed lanes (e.g., 3, 2, 1, 0) and host supports reversal
→ Adjust accordingly
* If not matching or incomplete → Retry or fallback
✅ In our case, all match → Host proceeds to next state.
---
### ✅ 6. **Configuration.Complete**
* Host sends **TS2 (Training Set 2)** packets with finalized Link and Lane Numbers.
* Device echoes TS2s back.
✅ Host confirms:
* At least **16 TS2s transmitted** after receiving one on all lanes
* At least **8 consecutive matching TS2s received** on all lanes
---
### ⚙️ 7. **Configuration.Idle**
* Host and device send **IDL (Idle symbols)** to verify proper symbol alignment and
that **scrambling is working**.
✅ Host confirms:
* 16 IDLs transmitted after receiving one
* 8 consecutive IDLs received
---
### 🚀 8. **L0 – Link Up!**
* The **Link is considered "up"**, and real data can now be exchanged.
* This is still at **2.5 GT/s (Gen 1)**, the safe default.
---
## ⚡ BONUS: Speed Upgrade to Gen 2 (5 GT/s)
Both devices support **at least Gen 2**. So now the LTSSM can attempt to
**negotiate a speed increase**:
### 🛠 9. **Recovery State**
* Host initiates a **transition to Recovery** to change speed.
* Both sides go through substates:
* **Recovery.RcvrLock**
* **Recovery.RcvrCfg**
* **Recovery.Speed**
They both agree to move to **5 GT/s (Gen 2)**, which is the highest speed supported
by both.
---
### ✅ 10. **Back to L0**
* Once Recovery is successful, they re-enter **L0**, now at the **new speed**.
* Real data transfer now happens at **5 GT/s per lane**, totaling **20 GT/s**
across 4 lanes.
---
## 🔚 Summary (Human Terms)
Think of it like a negotiation between a laptop (host) and a high-performance SSD
(device). They start talking at the slowest speed, confirm they understand each
other, agree on how many lanes they want to use (e.g., a 4-lane highway), make sure
all lanes are aligned and working, then finally go full throttle at the fastest
speed they both support.
---
Would you like a diagram or table to visualize the lane assignments and transitions
as well?
Absolutely bro — let's break this down **practically**, so you can understand how
the **PCIe LTSSM (Link Training and Status State Machine)** behaves during a speed
change to **8GT/s**, focusing on what’s really going on at a **low-level signal and
logic level**.
---
## 🎯 First, What's Going On?
You're changing PCIe link speed from a base rate like **2.5GT/s** up to **8GT/s**
(Gen3). This is a **non-trivial** operation because the electrical behavior changes
a lot — you now need **equalization** to deal with signal distortion over the
physical traces (the PCB).
So the LTSSM goes through a bunch of **Recovery substates** to:
* Coordinate both sides of the link
* Adjust signal shapes (preshoot, de-emphasis)
* Confirm that the new speed is stable
---
## Let’s Walk the Normal Path Step-by-Step (Simplified)
### 1. 🔁 From L0 to Recovery.RcvrLock (First Time, 2.5GT/s)
* The device says: "Yo, I want to go faster!"
* It sends **TS1s** (Training Sequences) with `Speed Change = 1`.
* It can **suggest presets** for equalization (like: "Hey, when you switch, use
this preset for your transmitter").
**Goal here:** Get 8 TS1/TS2s back with Speed Change also = 1 ➡️ shows that the
other end agrees.
---
### 2. 🔁 Recovery.RcvrCfg (First Time, Still 2.5GT/s)
* Now you both agree to change speeds.
* You send **TS2s with Speed Change = 1** to confirm config.
**Exit:** When you receive 8 matching TS2s back ➡️ move to Recovery.Speed.
---
### 3. ⚡ Recovery.Speed
* Transmitter: **go into electrical idle** (stop transmitting real data).
* Then it switches to **8GT/s** speed and applies the equalization presets.
* Wait 800ns to 1ms.
**Exit:** Go back to Recovery.RcvrLock — now you're talking at 8GT/s.
---
### 4. 🔁 Recovery.RcvrLock (Second Time, Now at 8GT/s)
* You’re now at the faster speed — need to re-establish the link.
* Send TS1s at 8GT/s with `Speed Change = 0` (we're done switching speeds).
* The receiver checks if it can lock onto the new data stream.
**Exit:** Once 8 TS1/TS2s with `Speed Change = 0` are received ➡️ move to
Recovery.Equalization.
---
### 5. ⚙️ Recovery.Equalization
This is where the magic happens. You:
* Send TS1s with `EC = 01` (equalization phase 1).
* Tell the other side: "Here’s my voltage swing capability and my current preset."
* If the other side agrees with the settings → you’re done.
**Normal exit:** After receiving **2 TS1s with EC = 01** ➡️ back to
Recovery.RcvrLock.
**Else:** Timeout? Drop back to Recovery.Speed and try again, maybe with different
EQ settings.
---
### 6. 🔁 Recovery.RcvrLock (Third Time, Still 8GT/s)
* This time it's to **finalize** the link at 8GT/s.
* Send TS1s with `Speed Change = 0`, EC = 00, and your actual EQ settings.
**Exit:** 8 good TS1s/TS2s received? ➡️ Move to Recovery.RcvrCfg.
---
### 7. 🔁 Recovery.RcvrCfg (Second Time, Still 8GT/s)
* Final confirmation: Send TS2s with `Speed Change = 0`.
**Exit:** 8 good TS2s received ➡️ move to Recovery.Idle.
---
### 8. 🛑 Recovery.Idle
* Send **Idle symbols** (`IDL = 0x00`) at 8GT/s.
* Receiver looks for 8 in a row.
* You need to **see** at least one Idle, then send 16.
**Success = Link is Up!** ➡️ You’re back in L0 at 8GT/s!
---
## 🎉 Now You’re in L0 Again at 8GT/s
This means:
* **Physical Layer is done.**
* **Data Link Layer (DLL)** now kicks in (starts credit-based flow control).
* Only after DLL init can the **Transaction Layer** send memory reads/writes.
---
## 🔧 Real-World Troubleshooting Tips
If something fails:
* **Use a protocol analyzer** like your U4301B.
* Look at the Training Sequences — are the `Speed Change` bits mismatched?
* Are TS1/TS2s missing or malformed?
* Are EC bits stuck in the wrong phase?
* Did it timeout in Equalization (24ms limit)?
Each of these tells you **where** and **why** the link training failed.
---
## 🧠 TL;DR (The Bro Summary)
* You switch from 2.5GT/s → 8GT/s.
* It’s like a handshake with retries: “I wanna go faster.” “Cool. You good with
this EQ?” “Yeah, looks good.” “Alright, I’m going fast now.” “Confirmed.” “Okay,
I’m idle at full speed now.” “Cool, let’s go!”
* Takes about 8–12ms normally.
* Requires good signal integrity, tuned equalization, and matching TS1/TS2
sequences.
---
If you want a **flowchart diagram** or a visual timeline of this process, I can
make one for you — just let me know!
Want me to explain the **equalization presets** and how preshoot/de-emphasis
actually work at the analog level next?
L0 @ Gen1
↓
Recovery.RcvrLock (2.5GT/s) → TS1s, Speed Change = 1
↓
Recovery.RcvrCfg (2.5GT/s) → TS2s, confirm target Gen5
↓
Recovery.Speed → Switch PHY to 32GT/s
↓
Recovery.RcvrLock @ Gen5 → TS1s, Speed Change = 0
↓
Recovery.Equalization (entered, EC = 00)
↓
Recovery.RcvrLock @ Gen5 → TS1s EC = 00, 8 TS1s rule
↓
Recovery.RcvrCfg @ Gen5 → TS2s EC = 00
↓
Recovery.Idle
↓
✅ L0 @ Gen5 🎉
