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Verilogcode of 24 Hour Clock

This document describes a Verilog module that implements a 24-hour clock. It contains registers to store the seconds, minutes, hours, and day of week. It increments the time each clock cycle and rolls over the seconds to minutes and hours as needed. It also changes the day of week when hours rolls over from 23 to 0. A test bench is provided to simulate setting the time and monitor the output for 100 time units.

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suresh
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91 views3 pages

Verilogcode of 24 Hour Clock

This document describes a Verilog module that implements a 24-hour clock. It contains registers to store the seconds, minutes, hours, and day of week. It increments the time each clock cycle and rolls over the seconds to minutes and hours as needed. It also changes the day of week when hours rolls over from 23 to 0. A test bench is provided to simulate setting the time and monitor the output for 100 time units.

Uploaded by

suresh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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***********************************************************************************

*******************************************************
24 hour clock
***********************************************************************************
*******************************************************
module
clock_generator(set_rt,seconds,minutes,hours,daystring,s_rt,m_rt,h_rt,ds_rt,clock,r
eset);
input clock, reset,s_rt,m_rt,h_rt,ds_rt,set_rt;
output seconds,minutes,hours,daystring;
reg[5:0] seconds;
reg[5:0] minutes;
reg[4:0] hours;
reg[3*8:1]daystring;

wire[5:0] s_rt;
wire[5:0] m_rt;
wire[4:0] h_rt;
wire[3*8:1] ds_rt;
wire set_rt;

initial
begin
seconds=6'b0;
minutes=6'b0;
hours=5'b0;
daystring="SUN";
end

always@(posedge clock or posedge reset)


begin
if(reset==1'b1)
begin
seconds=0;
minutes=0;
hours=0;
daystring="SUN";
end
else
if(set_rt==0)
begin
seconds=6'b0;
minutes=6'b0;
hours=5'b0;
daystring="SUN";
end
if(set_rt==1)
begin
seconds=s_rt;
minutes=m_rt;
hours=h_rt;
daystring=ds_rt;
assign seconds=seconds+1;
if(seconds==60)
begin
assign seconds=0;
assign minutes=minutes+1;
if(minutes==60)
begin
assign minutes=0;
assign hours=hours+1;
if(hours==24)
begin
assign hours=0;
if(daystring=="SUN")
assign daystring="MON";
else if(daystring=="MON")
assign daystring="TUE";
else if(daystring=="TUE")
assign daystring="WED";
else if(daystring=="WED")
assign daystring="THU";
else if(daystring=="THU")
assign daystring="FRI";
else if(daystring=="FRI")
assign daystring="SAT";
else if(daystring=="SAT")
assign daystring="SUN";
end
end
end
end
end
endmodule
***********************************************************************************
*******************************************************
Test Bench
***********************************************************************************
*******************************************************
module clock_gen_tb;
wire[5:0] seconds_tb;
wire[5:0] minutes_tb;
wire[4:0] hours_tb;
wire[3*8:1] daystring_tb;

reg clock_tb, reset_tb;

reg[5:0] s_tb;
reg[5:0] m_tb;
reg[4:0] h_tb;
reg[3*8:1]ds_tb;
reg set_tb;

clock_generator dut
(.set_rt(set_tb),.seconds(seconds_tb),.minutes(minutes_tb),.hours(hours_tb),.daystr
ing(daystring_tb),.s_rt(s_tb),.m_rt(m_tb),.h_rt(h_tb),.ds_rt(ds_tb),.clock(clock_tb
),.reset(reset_tb));
initial clock_tb=0;
always #2 clock_tb=~clock_tb;
initial
begin
$monitor("%0t;Day=%s:hour=%0d:minute=%0d:second=%0d",
$time,daystring_tb,hours_tb,minutes_tb,seconds_tb);
end
initial
begin
reset_tb=1;
#50
reset_tb=0;
set_tb=1;
s_tb=59;
m_tb=23;
h_tb=13;
ds_tb="SUN";

#100
$finish;
end
endmodule

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