Chapter one

Basic semiconductor theory

1.1 Semiconductor Materials

The label semiconductor itself provides a hint as to its characteristics. The prefix semis normally
applied to a range of levels midway between two limits.
Conductor: is applied to any material that will support a generous flow of charge when a
voltage source of limited magnitude is applied across its terminals.
Insulator: is a material that offers a very low level of conductivity under pressure from an applied
voltage source.
Semiconductor: therefore, is a material that has conductivity level somewhere between
the extremes of an insulator and conductor.
Resistivity
Inversely related to the conductivity of a material is its resistance to the flow of charge, or current.
That is, the higher the conductivity level, the lower the resistance level. In tables, the term
resistivity (ρ, Greek letter rho) is often used when comparing the resistance levels of materials.

Figure 1.1 defining the metric units of resistivity

Note in Table 1.1 the extreme range between the conductor and insulating materials for the 1-cm
length (1-cm2 area) of the material. Ge and Si have received the attention they have for a number of
reasons.
One very important consideration is the fact that they can be manufactured to a very high purity
level. In fact, recent advances have reduced impurity levels in the pure material to 1 part in 10
billion (1:10,000,000,000).
The ability to change the characteristics of the material significantly through this process, known as
“doping,‖ is yet another reason why Ge and Si have received such wide attention. Further reasons
include the fact that their characteristics can be altered significantly through the application of heat
or light—an important consideration in the development of heat- and light-sensitive devices.
1.2 Atomic theory

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Some of the unique qualities of Ge and Si noted above are due to their atomic structure. The atoms
of both materials form a very definite pattern that is periodic in nature (i.e., continually repeats
itself). One complete pattern is called a crystal and the periodic arrangement of the atoms a lattice.
For Ge and Si the crystal has the three-dimensional diamond structure of Fig. 1.2

Figure 1.2 Ge and Si (Single-crystal structure Silicon Lattice)

Any material composed solely of repeating crystal structures of the same kind is called a single-
crystal structure. For semiconductor materials of practical application in the electronics field, this
single-crystal feature exists, and, in addition, the periodicity of the structure does not change
significantly with the addition of impurities in the doping process.

How the structure of the atom might affect the electrical characteristics of the material?

As you are aware, the atom is composed of three basic particles: the electron, the proton, and the
neutron. In the atomic lattice, the neutrons and protons form the nucleus, while the electrons
revolve around the nucleus in a fixed orbit. The Bohr models of the two most commonly used
semiconductors; Germanium and silicon are shown in Fig. 1.3

Figure 1.3 Atomic structures: (a) germanium; Figure 1.4 Covalent bonding of the
(b) Silicon silicon atom

As indicated by Fig. 1.3a, the germanium atom has 32 orbiting electrons, while silicon has 14
orbiting electrons. In each case, there are 4 electrons in the outermost (valence) shell. The potential
(ionization potential) required to remove any one of these 4 valence electrons is lower than that
required for any other electron in the structure. In a pure germanium or silicon crystal these 4

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valence electrons are bonded to 4 adjoining atoms, as shown in Fig. 1.4 for silicon. Both Ge and Si
are referred to as tetravalent atoms because they each have four valence electrons.

A bonding of atoms, strengthened by the sharing of electrons, is called covalent bonding.

ENERGY LEVELS

In the isolated atomic structure there are discrete (individual) energy levels associated with each
orbiting electron, as shown in Fig. 1.5. Each material will, in fact, have its own set of permissible
energy levels for the electrons in its atomic structure.
The more distant the electron from the nucleus, the higher the energy state, and any electron that has left its
parent atom has a higher energy state than any electron in the atomic structure.

Figure 1.5 Energy levels: discrete levels in isolated atomic structures;

The energy associated with each electron is measured in electron volts (eV). The unit of measure is
appropriate, since

As derived from the defining equation for voltage V = W/Q. The charge Q is the charge associated
with a single electron. Substituting the charge of an electron and a potential difference of 1 volt into
Eq. (1.2) will result in an energy level referred to as one electron volt. Since energy is also
measured in joules and the charge of one electron =1.6 × 10-19 coulomb,

Energy Band Model

One method of characterizing an electrical material is based up on a diagram that represents

electron energy in that material. In the general case, electronic energy is divided among three bands
that are designated as the valence band (bonding electrons with lowest energy), forbidden gap or
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band (electrons do not occupy energy states), and conduction band (conduction electrons with
highest energy). In metallic conductors the forbidden gap is absent. In insulators, the forbidden gap
is very large, and in semiconductors it is relatively small. Energy band diagrams for these three
classes of materials are illustrated in figure 1.6.

Figure 1.6 Conduction and valence bands of an insulator, semiconductor, and conductor.

Electrons occupy specific energy states, or levels, in the conduction and valence bands, but they
may not occupy energy states located in the band gap, which is why it is frequently called the
forbidden gap. Relative to figure 1.6, to achieve electrical conduction, electrons must transfer from
energy states in the valence band to energy states in the conduction band. The valence band
represents low energy states of the electrons, in which the electrons are tightly bound to the atoms
of the material. The forbidden band is not a physical void, but rather an energy gap. To cross the
band gap, an electron must attain energy equal to or greater than the lowest allowed energy state in
the conduction band; otherwise it cannot cross the gap.
In metals once temperature rises above absolute zero (0K), electrons acquire sufficient thermal
energy to transfer from the valence band to the conduction band, thus making electrical conduction
possible in the form of that described by Ohm‘s law. In semiconductors, the term ohmic condition
is applied to this phenomenon. Atoms are ionized (electrons are torn loose), and free (conduction)
electrons are released to establish an electric current.
The forbidden gap regions associated with insulators and semiconductors represent energy levels
that electrons may not assume. The only way that an electron can move from the valence band to
the conduction band in these materials is by acquiring sufficient energy to cross the gap. Because of
the large forbidden band in insulators, the material is usually damaged or destroyed.
In the pure (intrinsic) state, semiconducting materials manifest a forbidden gap that is less than that
found in insulators. These materials are basically insulators, but not particularly good ones. When
intrinsic semiconductors are modified by the addition of certain impurities, new (allowed) valence
electrons states are created high in the forbidden gap, so that electrons can jump relatively easily
into the conduction band

Example
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 1. How much energy in joules is required to move a charge of 6 C through a difference in
potential of 3 V?

Solution

2. If 48 eV of energy is required to move a charge through a potential difference of 12V,

determine the charge involved.

Intrinsic semiconductor
An intrinsic semiconductor is one, which is pure enough that impurities do not appreciably affect
its electrical behaviour. In this case, all carriers are created due to thermally or optically excited
electrons from the full valence band into the empty conduction band. Thus equal numbers of
electrons and holes are present in an intrinsic semiconductor. Electrons and holes flow in opposite
directions in an electric field, though they contribute to current in the same direction since they are
oppositely charged. Hole current and electron current are not necessarily equal in an intrinsic
semiconductor, however, because electrons and holes have different effective masses (crystalline
analogues to free inertial masses).
The concentration of carriers is strongly dependent on the temperature. At low temperatures, the
valence band is completely full making the material an insulator. Increasing the temperature leads
to an increase in the number of carriers and a corresponding increase in conductivity. This
characteristic shown by intrinsic semiconductor is different from the behaviour of most metals,
which tend to become less conductive at higher temperatures due to increased phonon scattering.
Negative temperature coefficient:
Semiconductor materials such as Ge and Si that show a reduction in resistance with increase in
temperature are said to have a negative temperature coefficient.

Extrinsic semiconductor
The characteristics of semiconductor materials can be altered significantly by the addition of
certain impurity atoms into the relatively pure semiconductor material. These impurities, although
only added to perhaps 1 part in 10 million, can alter the band structure sufficiently to totally change
the electrical properties of the material.
A semiconductor material that has been subjected to the doping process is called an extrinsic material.
There are two extrinsic materials of immeasurable importance to semiconductor device fabrication:
n-type and p-type. Each will be described in some detail in the following paragraphs.
n-Type Material
Both the n- and p-type materials are formed by adding a predetermined number of impurity atoms
into a germanium or silicon base. The n-type is created by introducing those impurity elements that
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have five valence electrons (pentavalent), such as antimony, arsenic, and phosphorus. The effect of
such impurity elements is indicated in Fig. 1.7 (using antimony as the impurity in a silicon base).

Figure 1.7 Antimony impurity in n-type material.

Note that the four covalent bonds are still present. There is, however, an additional fifth electron
due to the impurity atom, which is not associated with any particular covalent bond. This
remaining electron, loosely bound to its parent (antimony) atom, is relatively free to move within
the newly formed n-type material. Since the inserted impurity atom has donated a relatively ―free‖
electron to the structure:
Diffused impurities with five valence electrons are called donor atoms.
It is important to realize that even though a large number of ―free‖ carriers have been established in
the n-type material, it is still electrically neutral since ideally the number of positively charged
protons in the nuclei is still equal to the number of ―free‖ and orbiting negatively charged electrons
in the structure.
The effect of this doping process on the relative conductivity can best be described through the use
of the energy-band diagram of Fig. 1.8. Note that a discrete energy level (called the donor level)
appears in the forbidden band with an Eg significantly less than that of the intrinsic material. Those
―free‖ electrons due to the added impurity sit at this energy level and have less difficulty absorbing
a sufficient measure of thermal energy to move into the conduction band at room temperature. The
result is that at room temperature, there are a large number of carriers (electrons) in the conduction
level and the conductivity of the material increases significantly. At room temperature in an
intrinsic Si material there is about one free electron for every 1012 atom (1 to 109 for Ge). If our
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dosage level were 1 in 10 million ( 107 ), the ratio ( 10 7  10 ) would indicate that the carrier
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concentration has increased by a ratio of 100,000: 1.

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Figure 1.8 Effect of donor impurities on the energy band structure.

p-Type Material
The p-type material is formed by doping a pure germanium or silicon crystal with impurity atoms
having three valence electrons. The elements most frequently used for this purpose are boron,
gallium, and indium. The effect of one of these elements, boron, on a base of silicon is indicated in
Fig. 1.9.

Figure 1.9 Boron impurity in p-type material.

Note that there is now an insufficient number of electrons to complete the covalent bonds of the
newly formed lattice. The resulting vacancy is called a hole and is represented by a small circle or
positive sign due to the absence of a negative charge. Since the resulting vacancy will readily
accept a ―free‖ electron:
The diffused impurities with three valence electrons are called acceptor atoms.
The resulting p-type material is electrically neutral, for the same reasons described for the n-type
material.

Electron versus Hole Flow

The effect of the hole on conduction is shown in Fig. 1.10. If a valence electron acquires sufficient
kinetic energy to break its covalent bond and fills the void created by a hole, then a vacancy, or
hole, will be created in the covalent bond that released the electron. There is, therefore, a transfer of
holes to the left and electrons to the right, as shown in Fig. 1.10. The direction to be used in this
text is that of conventional flow, which is indicated by the direction of hole flow.

Figure 1.10 Electron versus Hole flow.

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Diffusion and drift current
The diffusion is a flow of charge carriers from a region of high density to a region of low density
due to non uniform distribution of it. Diffusion current is the transport of charge carriers in a
semiconductor.
Drift is charged particle motion in response to an applied electric field. When an electric field is
applied across a semiconductor, the carriers start moving, producing a current. The positively
charged holes move with the electric field, whereas the negatively charged electrons move against
the electric field.

Majority and Minority Carriers

In the intrinsic state, the number of free electrons in Ge or Si is due only to those few electrons in
the valence band that has acquired sufficient energy from thermal or light sources to break the
covalent bond or to the few impurities that could not be removed. The vacancies left behind in the
covalent bonding structure represent our very limited supply of holes. In an n-type material, the
number of holes has not changed significantly from this intrinsic level. The net result, therefore, is
that the number of electrons far outweighs the number of holes. For this reason:

In an n-type material (Fig. 1.11a) the electron is called the majority carrier and the hole is the minority
carrier.

For the p-type material the number of holes far outweighs the number of electrons, as shown in Fig.
1.11b. Therefore:
In a p-type material the hole is the majority carrier and the electron is the minority carrier.

When the fifth electron of a donor atom leaves the parent atom, the atom remaining acquires a net
positive charge: hence the positive sign in the donor-ion representation. For similar reasons, the
negative sign appears in the acceptor ion. The n- and p-type materials represent the basic building
blocks of semiconductor devices. We will find in the next section that the ―joining‖ of a single n-
type material with a p-type material will result in a semiconductor element of considerable
importance in electronic systems.

Figure 1.11 (a) n-type material; (b) p-type material.

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Chapter 2: Semiconductor diodes and their applications
Introduction

The construction, characteristics, and models of semiconductor diodes were introduced in Chapter 1. The primary
goal of this chapter is to develop a working knowledge of the diode in a variety of configurations using models
appropriate for the area of application. By chapter‘s end, the fundamental behavior pattern of diodes in dc and ac
networks should be clearly understood. The concepts learned in this chapter will have significant carryover in the
chapters to follow. For instance, diodes are frequently employed in the description of the basic construction of
transistors and in the analysis of transistor networks in the dc and ac domains.
The content of this chapter will reveal an interesting and very positive side of the study of a field such as
electronic devices and systems once the basic behavior of a device is understood, its function and response in an
infinite variety of configurations can be determined. The range of applications is endless, yet the characteristics
and models remain the same. The analysis will proceed from one that employs the actual diode characteristic to
one that utilizes the approximate models almost exclusively.
It is important that the role and response of various elements of an electronic system be understood without
continually having to resort to lengthy mathematical procedures. This is usually accomplished through the
approximation process, which can develop into an art itself. Although the results obtained using the actual
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characteristics may be slightly different from those obtained using a series of approximations, keep in mind that
the characteristics obtained from a specification sheet may in themselves be slightly different from the device in
actual use.

LOAD-LINE ANALYSIS
The applied load will normally have an important impact on the point or region of operation of a device. If the
analysis is performed in a graphical manner, a line can be drawn on the characteristics of the device that
represents the applied load. The intersection of the load line with the characteristics will determine the point of
operation of the system. Such an analysis is, for obvious reasons, called load-line analysis.
Although the majority of the diode networks analyzed in this chapter do not employ the load-line approach, the
technique is one used quite frequently in subsequent chapters, and this introduction offers the simplest application
of the method. It also permits a validation of the approximate technique described throughout the remainder of
this chapter.
Consider the network of Fig. 2.1a employing a diode having the characteristics of Fig. 2.1b. Note in Fig. 2.1a that
the ―pressure‖ established by the battery is to establish a current through the series circuit in the clockwise
direction. The fact that this current and the defined direction of conduction of the diode are a ―match‖ reveals that
the diode is in the ―on‖ state and conduction has been established. The resulting polarity across the diode will be
as shown and the first quadrant (VD and ID positive) of Fig. 2.1b will be the region of interest the forward-bias
region. Applying Kirchhoff‘s voltage law to the series circuit of Fig. 2.1a will result in

Figure2.1: Series diode configuration: (a) circuit; (b) characteristics

The two variables of Eq. (2.1) (VD and ID) are the same as the diode axis variables of Fig. 2.1b. This
similarity permits a plotting of Eq. (2.1) on the same characteristics of Fig. 2.1b.

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The intersections of the load line on the characteristics can easily be determined if one simply
employs the fact that anywhere on the horizontal axis ID = 0 A and anywhere on the vertical axis VD
=0 V.
If we set VD =0 V in Eq. (2.1) and solve for ID, we have the magnitude of ID on the vertical axis.
Therefore, with VD =0 V, Eq. (2.1) becomes

as shown in Fig. 2.2. If we set ID = 0 A in Eq. (2.1) and solve for VD, we have the magnitude of VD
on the horizontal axis. Therefore, with ID =0 A, Eq. (2.1) becomes

as shown in Fig. 2.2. A straight line drawn between the two points will define the load line as
depicted in Fig. 2.2. Change the level of R (the load) and the intersection on the vertical axis will
change. The result will be a change in the slope of the load line and a different point of intersection
between the load line and the device characteristics.
We now have a load line defined by the network and a characteristic curve defined by the device.
The point of intersection between the two is the point of operation for this circuit. By simply
drawing a line down to the horizontal axis the diode voltage VDQ can be determined, whereas a
horizontal line from the point of intersection to the vertical axis will provide the level of IDQ. The
current ID is actually the current through the entire series configuration of Fig. 2.1a. The point of
operation is usually called the quiescent point (abbreviated ―Q-pt.‖) to reflect its ―still, unmoving‖
qualities as defined by a dc network.

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 Figure2.2: Drawing the load line and finding the point of operation
Example 1: For the series diode configuration of Fig. 2.3a employing the diode characteristics of
Fig. 2.3b determine:
(a) VDQ and IDQ.
(b) VR.

Figure2.3: (a) Circuit; (b) characteristics

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Example 2: Repeat the analysis of Example 1 with R =2 kΩ.

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SERIES DIODE CONFIGURATIONS WITH DC INPUTS
In this section the approximate model is utilized to investigate a number of series diode
configurations with dc inputs. The content will establish a foundation in diode analysis that will
carry over into the sections and chapters to follow. The procedure described can, in fact, be applied
to networks with any number of diodes in a variety of configurations. For each configuration the
state of each diode must first be determined. Which diodes are ―on‖ and which are ―off‖? Once
determined, the appropriate equivalent as defined in Section 2.3 can be substituted and the
remaining parameters of the network determined.
In general, a diode is in the “on” state if the current established by the applied sources is such
that its direction matches that of the arrow in the diode symbol, and VD =0.7 V for silicon and
VD=0.3 V for germanium.

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For each configuration, mentally replace the diodes with resistive elements and note the resulting
current direction as established by the applied voltages (―pressure‖). If the resulting direction is a
―match‖ with the arrow in the diode symbol, conduction through the diode will occur and the
device is in the ―on‖ state. The description above is, of course, contingent on the supply having a
voltage greater than the ―turn on‖ voltage (VT) of each diode.
If a diode is in the ―on‖ state, one can either place a 0.7-V drop across the element, or the network
can be redrawn with the VT equivalent circuit. In time the preference will probably simply be to
include the 0.7-V drop across each ―on‖ diode and draw a line through each diode in the ―off‖ or
open state. Initially, however, the substitution method will be utilized to ensure that the proper
voltage and current levels are determined.
The series circuit of Fig. 2.10 described in some detail in Section 2.2 will be used to demonstrate
the approach described in the paragraphs above. The state of the diode is first determined by
mentally replacing the diode with a resistive element as shown in Fig. 2.11. The resulting direction
of I is a match with the arrow in the diode symbol, and since E >VT the diode is in the ―on‖ state.
The network is then redrawn as shown in Fig. 2.12 with the appropriate equivalent model for the
forward-biased silicon diode. Note for future reference that the polarity of VD is the same as would
result if in fact the diode were a resistive element. The resulting voltage and current levels are the
following:

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 (a) (b)

(c)
Figure2.4: (a) Series diode configuration (b) Determining the state of the diode (c) Substituting the
equivalent model for the ―on‖ diode

Figure2.5: Reversing the diode; determining the state of the diode and Substituting the equivalent
model for the ―off‖ diode

The resulting current direction does not match the arrow in the diode symbol. The diode is in the
―off‖ state, resulting in the equivalent circuit of the above figure. Due to the open circuit, the diode
current is 0 A and the voltage across the resistor R is the following:

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Example 3: For the series diode configuration of Fig. 2.16, determine VD, VR, and ID.

Example 4: Determine Vo and ID for the series circuit given below.

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PARALLEL DIODE CONFIGURATION
The methods applied in series diode configuration can be extended to the analysis of parallel
configuration. For each area of application, simply match the sequential series of steps applied to
series diode configurations.
Example 5: Determine Vo, I1, ID1, and ID2 for the parallel diode configuration given below.

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Example 6: Determine the current I for the network shown below.

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SINUSOIDAL INPUTS; HALF-WAVE RECTIFICATION
The diode analysis will now be expanded to include time-varying functions such as the sinusoidal
waveform and the square wave. There is no question that the degree of difficulty will increase, but
once a few fundamental maneuvers are understood, the analysis will be fairly direct and follow a
common thread.
The simplest of networks to examine with a time-varying signal appears in Fig. 2.6. For the
moment we will use the ideal model (note the absence of the Si or Ge label to denote ideal diode) to
ensure that the approach is not clouded by additional mathematical complexity.

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 Figure2.6: Half-wave rectifier
Over one full cycle, defined by the period T of Fig. 2.43, the average value (the algebraic sum of
the areas above and below the axis) is zero. The circuit of Fig. 2.6, called a half-wave rectifier, will
generate a waveform vo that will have an average value of particular, use in the ac-to-dc conversion
process. When employed in the rectification process, a diode is typically referred to as a rectifier.
Its power and current ratings are typically much higher than those of diodes employed in other
applications, such as computers and communication systems. During the interval t=0→T/2 in Fig.
2.6 the polarity of the applied voltage vi is such as to establish ―pressure‖ in the direction indicated
and turn on the diode with the polarity appearing above the diode. Substituting the short-circuit
equivalence for the ideal diode will result in the equivalent circuit of Fig. 2.7, where it is fairly
obvious that the output signal is an exact replica of the applied signal. The two terminals defining
the output voltage are connected directly to the applied signal via the short-circuit equivalence of
the diode.

Figure2.7: Conduction region (0→T/2)

For the period T/2 →T, the polarity of the input vi is as shown in Fig. 2.8 and the resulting polarity
across the ideal diode produces an ―off‖ state with an open-circuit equivalent. The result is the
absence of a path for charge to flow and vo= iR =(0)R= 0 V for the period T/2→T. The input vi and

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the output vo were sketched together in Fig. 2.9 for comparison purposes. The output signal vo now
has a net positive area above the axis over a full period and an average value determined by

Figure2.8: Nonconduction region (T/2→T)

Figure2.9: Half-wave rectified signal

The process of removing one-half the input signal to establish a dc level is called half-wave
rectification. The effect of using a silicon diode with VT = 0.7 V is demonstrated in Fig. 2.10 for the
forward-bias region. The applied signal must now be at least 0.7 V before the diode can turn ―on.‖
For levels of vi less than 0.7 V, the diode is still in an open circuit state and vo = 0 V as shown in the
same figure. When conducting, the difference between vo and vi is a fixed level of VT =0.7 V and vo
= vi - VT, as shown in the figure. The net effect is a reduction in area above the axis, which naturally

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reduces the resulting dc voltage level. For situations where Vm >>VT, the following equation can be
applied to determine the average value with a relatively high level of accuracy.

Figure2.10: Effect of VT on half-wave rectified signal

Example 7:
(a) Sketch the output vo and determine the dc level of the output for the network of figure shown
below.
(b) Repeat part (a) if the ideal diode is replaced by a silicon diode.
(c) Repeat parts (a) and (b) if Vm is increased to 200 V and compare solutions using the above two
equations.

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FULL-WAVE RECTIFICATION

Bridge Network

The dc level obtained from a sinusoidal input can be improved 100% using a process called full-
wave rectification. The most familiar network for performing such a function appears in Fig. 2.11
with its four diodes in a bridge configuration. During the period t = 0 to T/2 the polarity of the input
is as shown in Fig. 2.12. The resulting polarities across the ideal diodes are also shown in Fig. 2.12
to reveal that D2 and D3 are conducting while D1 and D4 are in the ―off‖ state. The net result is the
configuration of Fig. 2.13, with its indicated current and polarity across R. Since the diodes are
ideal the load voltage is vo = vi, as shown in the same figure.

Figure2.11: Full-wave bridge rectifier

Figure2.12: Network for the period 0 T/2 of the input voltage vi

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 Figure2.13: Conduction path for the positive region of vi
For the negative region of the input the conducting diodes are D1 and D4, resulting in the
configuration of Fig. 2.14. The important result is that the polarity across the load resistor R is the
same as in Fig. 2.12, establishing a second positive pulse, as shown in Fig. 2.14. Over one full
cycle the input and output voltages will appear as shown in Fig. 2.15.

Figure2.14: Conduction path for the negative region of vi

Figure2.15: Input and output waveforms for a full-wave rectifier

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Since the area above the axis for one full cycle is now twice that obtained for a half-wave system,
the dc level has also been doubled and

If silicon rather than ideal diodes are employed as shown in Fig. 2.16, an application of Kirchhoff‘s
voltage law around the conduction path would result in

The peak value of the output voltage vo is therefore

For situations where Vm>>2VT, Eq. (2.11) can be applied for the average value with a relatively
high level of accuracy.

Figure2.16: Determining Vomax for silicon diodes in the bridge configuration

Then again, if Vm is sufficiently greater than 2VT, then Eq. (2.10) is often applied as a first
approximation for Vdc.

Center-Tapped Transformer
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A second popular full-wave rectifier appears in Fig. 2.17 with only two diodes but requiring a
center-tapped (CT) transformer to establish the input signal across each of the secondary of the
transformer. During the positive portion of vi applied to the primary of the transformer, the network
will appear as shown in Fig. 2.18. D1 the short-circuit equivalent and D2 the open-circuit
equivalent, as the secondary voltages and the resulting current directions. The output voltage
appears as shown in Fig. 2.18.

Figure2.17: Center-tapped transformer full-wave rectifier

Figure2.18: Network conditions for the positive region of vi

During the negative portion of the input the network appears as shown in Fig.2.19, reversing the
roles of the diodes but maintaining the same polarity for the voltage across the load resistor R. The
net effect is the same output as that appearing in Fig. 2.15 with the same dc levels.

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 Figure2.19: Network conditions for the negative region of vi
Example 8: Determine the output waveform for the network of Figure shown below and calculate
the output dc level and the required PIV of each diode.

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Types of diode
Zener diode
A Zener diode is a type of diode that permits current to flow in the forward direction like a normal
diode, but also in the reverse direction if the voltage is larger than the rated breakdown voltage or
"Zener voltage".

Figure2.20: Symbolic Representation of Zener Diode

A Zener diode exhibits almost the same properties, except the device is especially designed so as
to have a greatly reduced breakdown voltage, the so-called Zener voltage. A Zener diode contains
a heavily doped p-n junction allowing electrons to tunnel from the valence band of the p-type
material to the conduction band of the n-type material. A reverse biased Zener diode will exhibit a
controlled breakdown and let the current flow to keep the voltage across the Zener diode at the
Zener voltage. For example, a 3.2-volt Zener diode will exhibit a voltage drop of 3.2 volts if
reverse biased. The breakdown voltage can be controlled quite accurately in the doping process.
Another mechanism that produces a similar effect is the avalanche effect as in the avalanche diode.
The two types of diode are in fact constructed the same way and both effects are present in diodes
of this type. In silicon diodes up to about 5.6 volts, the Zener effect is the predominant effect and
shows a marked negative temperature coefficient. Above 5.6 volts, the avalanche effect becomes
predominant and exhibits a positive temperature coefficient.

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The VI characteristic of a Zener diode is shown in figure 2.21. With the application of sufficient
reverse voltage, a p-n junction will experience a rapid avalanche breakdown and conduct current in
the reverse direction. Valence electrons, which break free under the influence of the applied electric
field, can be accelerated enough that they can knock loose other electrons and the subsequent
collisions quickly become an avalanche. When this process is taking place, very small changes in
voltage can cause very large changes in current. The breakdown process depends upon the applied
electric field, so by changing the thickness of the layer to which the voltage is applied, Zener
diodes can be formed which break down at voltages from about 4 volts to several hundred volts.

Schottky diodes
These are diodes consisting of a junction called metal semiconductor (ms) junction and formed by
bringing metal (Al) in to moderately doped n-type semiconductor. Al acts as a p-type material
(anode), the n-type material is the cathode.
Unlike a normal semiconductor diode it can be turned off very quickly.

Light Emitting Diode (LED)

When pn-junction is forward biased, free electrons cross the junction and recombines with holes at
p-side. These electrons have been in the conduction band and drop to the valence band by
recombination. Because they are falling to a lower energy level they emit energy. This released
energy may be in the form of heat or light depending on the material used.
For example, silicon and germanium diodes release energy in the form of heat, whereas gallium
arsenide (GaAs) and gallium phosphate (GaP) release light energy. The color of emitted light is
controlled by the doping level.

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Application of diode circuits
Semiconductor diodes find many applications in electronics circuit designing. A major use is as a
rectifier in power supplies, to convert ac to dc in radio frequency receivers; in some instrumentation
systems they are used in a similar manner to recover (detect) amplitude modulation super imposed
upon a carrier signal. They may be used as polarity sensitive dc conductive devices (often called
steering diodes) as such they pass dc of one polarity while blocking dc of the opposite polarity. In
clipping, limiting and clamping circuits they are used to shape and alter signal profiles. Zener diodes
are used as voltage regulating devices. Varactor diodes serve as voltage tuned capacitors and find
many applications in radio frequency design. Light emitting diodes (LEDs) are used as indicator
lights and in displays, while light sensitive photodiodes are used as optical detectors.
Power supply
Most electronic equipment requires DC voltages for its operation. These can be provided by
batteries or by internal power supplies that convert alternating current as available at the home
electric outlet, into regulated DC voltages. The first element in an internal DC power supply is a
transformer, which steps up or steps down the input voltage to a level suitable for the operation of
the equipment. The transformer is then followed by a rectifier. Fluctuations and ripples
superimposed on the rectified DC voltage can be filtered out by a filter. Finally to get more precise
control over voltage levels and ripples can be achieved by a voltage regulator. This whole process
can be shown by the following block diagram.

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Transformer

This block (the transformer) levels the amplitude to the desired amount and it isolates the whole
electronic elements from the line voltage.

We know that the line voltage from the outlet is given by

2
Vrms  Vdc2  Vac2

Rectifier

The second block is the rectifier which changes AC into pulsating DC. Here the rectification result
is not pure DC. It has got some AC component and some DC components, as it is shown in the
following figure and equation for full wave rectifier:
2
Vrms  Vdc2  Vac2
Vac  Vrms
2
 Vdc2

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Filter

The third block reduces the ripple component of the rectified output.

Regulator

The last block, the regulator, reduces the ripple component of the output of the filter and stabilizes
the output voltage against the variation of source and load.

Clipper circuits
clippers that have the ability to ―clip‖ off a portion of the input signal without distorting the
remaining part of the alternating waveform. Depending on the orientation of the diode, the positive
or negative region of the input signal is ―clipped‖ off.
There are two general categories of clippers: series and parallel. The series configuration is defined
as one where the diode is in series with the load, while the parallel variety has the diode in a branch
parallel to the load.
Series
The response of the series configuration of Fig. 2.22a to a variety of alternating waveforms is
provided in Fig. 2.22b. Although first introduced as a half-wave rectifier (for sinusoidal

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waveforms), there are no boundaries on the type of signals that can be applied to a clipper. The
addition of a dc supply such as shown in Fig. 2.23 can have a pronounced effect on the output of a
clipper. Our initial discussion will be limited to ideal diodes, with the effect of VT reserved for a
concluding example.

Figure 2.22: Series clipper circuits and the output waveform

Figure 2.23: Series Clipper with a DC supply

There is no general procedure for analyzing networks such as the type in Fig. 2.23, but there are a
few thoughts to keep in mind as you work toward a solution.

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1. Make a mental sketch of the response of the network based on the direction of the diode and
the applied voltage levels.
For the network of Fig. 2.23, the direction of the diode suggests that the signal vi must be positive to
turn it on. The dc supply further requires that the voltage vi be greater than V volts to turn the diode
on. The negative region of the input signal is ―pressuring‖ the diode into the ―off‖ state, supported
further by the dc supply. In general, therefore, we can be quite sure that the diode is an open circuit
(―off‖ state) for the negative region of the input signal.
2. Determine the applied voltage (transition voltage) that will cause a change in state for the
diode.
For the ideal diode the transition between states will occur at the point on the characteristics where
vd =0 V and id =0 A. Applying the condition id =0 at vd =0 to the network of Fig. 2.22 will result in
the configuration of Fig. 2.24, where it is recognized that the level of vi that will cause a transition
in state is

Figure 2.24: Determining the transition level for the circuit

For an input voltage greater than V volts the diode is in the short-circuit state, while for input
voltages less than V volts it is in the open-circuit or ―off‖ state.
3. Be continually aware of the defined terminals and polarity of vo.

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When the diode is in the short-circuit state, such as shown in Fig. 2.25, the output voltage vo can be
determined by applying Kirchhoff‘s voltage law in the clockwise direction:

Figure2.25: Determining vo

4. It can be helpful to sketch the input signal above the output and determine the output at
instantaneous values of the input.
It is then possible that the output voltage can be sketched from the resulting data points of vo as
demonstrated in Fig. 2.26. Keep in mind that at an instantaneous value of vi the input can be treated
as a dc supply of that value and the corresponding dc value (the instantaneous value) of the output
determined. For instance, at vi =Vm for the network of Fig. 2.22, the network to be analyzed appears
in Fig. 2.27. For Vm > V the diode is in the short-circuit state and vo = Vm-V, as shown in Fig. 2.26.
At vi =V the diodes change state; at vi=-Vm, vo =0 V; and the complete curve for vo can be sketched
as shown in Fig. 2.27.

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 Figure2.26: Determining levels of vo

Figure2.27: Determining vo when vi =Vm and Sketching vo

Example 9: Determine the output waveform for the network given below.

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Parallel
The network of Fig. 2.28 is the simplest of parallel diode configurations with the output for the
same inputs of Fig. 2.22. The analysis of parallel configurations is very similar to that applied to
series configurations, as demonstrated in the next example.

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 Figure2.28: Response to a parallel clipper
Example 10: Determine vo for the network given below.

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Clamper Circuits

The clamping network is one that will ―clamp‖ a signal to a different dc level. The network must
have a capacitor, a diode, and a resistive element, but it can also employ an independent dc supply
to introduce an additional shift. The magnitude of R and C must be chosen such that the time
constant RC is large enough to ensure that the voltage across the capacitor does not discharge
significantly during the interval the diode is non-conducting. Throughout the analysis we will
assume that for all practical purposes the capacitor will fully charge or discharge in five time
constants.
The network of Fig. 2.29 will clamp the input signal to the zero level (for ideal diodes). The resistor
R can be the load resistor or a parallel combination of the load resistor and a resistor designed to
provide the desired level of R.

Figure 2.29: Clamper Circuit

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During the interval 0 → T/2 the network will appear as shown in Fig. 2.30, with the diode in the
―on‖ state effectively ―shorting out‖ the effect of the resistor R. The resulting RC time constant is
so small (R determined by the inherent resistance of the network) that the capacitor will charge to V
volts very quickly. During this interval the output voltage is directly across the short circuit and vo
=0 V.
When the input switches to the -V state, the network will appear as shown in Fig. 2.30, with the
open-circuit equivalent for the diode determined by the applied signal and stored voltage across the
capacitor—both ―pressuring‖ current through the diode from cathode to anode. Now that R is back
in the network the time constant determined by the RC product is sufficiently large to establish a
discharge period 5 much greater than the period T/2 → T, and it can be assumed on an approximate
basis that the capacitor holds onto all its charge and, therefore, voltage (since V = Q/C) during this
period.
Since vo is in parallel with the diode and resistor, it can also be drawn in the alternative position
shown in Fig. 2.30. Applying Kirchhoff‘s voltage law around the input loop will result in

Figure2.30: Diode ―on‖ and the capacitor charging to V volts and determining vo with the diode
―off.‖
The negative sign resulting from the fact that the polarity of 2V is opposite to the polarity defined
for vo. The resulting output waveform appears in Fig. 2.31 with the input signal. The output signal
is clamped to 0 V for the interval 0 to T/2 but maintains the same total swing (2V) as the input.

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 Figure2.31: Sketching vo for the network of figure 2.29
For a clamping network:
The total swing of the output is equal to the total swing of the input signal.

In general, the following steps may be helpful when analyzing clamping networks:
1. Start the analysis of clamping networks by considering that part of the input signal that will
forward bias the diode.
2. During the period that the diode is in the “on” state, assume that the capacitor will charge
up instantaneously to a voltage level determined by the network.
3. Assume that during the period when the diode is in the “off” state the capacitor will hold on to
its established voltage level.
4. Throughout the analysis maintain a continual awareness of the location and reference
polarity for vo to ensure that the proper levels for vo are obtained.
5. Keep in mind the general rule that the total swing of the total output must match the swing of
the input signal.
Example 11: Determine vo for the network shown below for the input indicated.

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4
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CHAPTER THREE
BIPOLAR JUNCTION TRANSISTORS
3.1 INTRODUCTION
Transistors are three terminal, three-layered, two-junction electronic devices whose voltage-current
relationship is controlled by a third voltage or current. We may regard a transistor as a controlled
voltage or current source.
They were demonstrated by a team of scientists at Bell laboratories in 1947 and their introduction
brought an end to the era of vacuum tube devices.
Advantages of transistors over vacuum tubes:
• Smaller size, light weight
• No heating elements required
• Low power consumption

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• Low operating voltages
Areas of application:
Used in applications such as signal amplifiers, electronic switches, oscillators, design of digital
logics, memory circuits etc.
Physical structure of transistors:
According to the physics of the device, we can classify transistors into two main classes:
1. Bipolar junction transistors (BJT)
2. Field effect transistors (FET) (to be discussed in the next chapter).

BJT: definition, construction, normal operating condition & symbolic representation

BJT is a diode-based transistor which is usually blocked unless the control terminals are forward
biased. So, the controlling agent is a current and BJT is a current amplifier by nature. Two types of
construction exist namely:
• Thin layer of n-type material sandwiched between two p-type materials (called a PNP transistor).
• Thin layer of p-type material sandwiched between two n-type materials (called NPN transistor)

Fig 3.1 physical structure and the terminals of BJT

Emitter (E) is heavily doped – supplies charge carriers.
Base (B) is lightly doped – allows most of the charge carriers to pass through it.
Collector is moderately doped(C) – collects the charge carriers.
We can also see that there are two junctions shared between the three terminals, the Emitter-base
junction and Collector-base junction.
The normal operating condition prevails if E-B junction is forward biased and C-B junction is reverse
biased.
The following figure shows the symbolic representation of the PNP and NPN transistors. In each case
arrow head represents the direction of current through emitter.

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Fig. 3.2: Transistor symbolic representation

3.2 PRINCIPLE OF OPERATION AND CHARACTERISTICS

The working principle of NPN transistor is discussed here and that of PNP transistor is similar
except the fact that roles of free electrons and holes are interchanged and current directions are
reversed.
Principle of operation of an NPN BJT transistor
• EB diode is forward biased. So, depletion region at EB junction is narrow.
• CB diode is reverse biased. So, depletion region at CB junction is wide.
• Free electrons from emitter region cross the junction and reach base region repelled by the
negative potential at the emitter terminal.
• Some of these free electrons combine with the holes in the base region. So, they move towards
the base terminal and form the base current.
• There are very less number of holes available in base. Therefore, most electrons (say, about
99%) coming from emitter do not combine with holes. They fall down the potential gradient and
enter collector region attracted by the positive potential at the collector terminal. This is how the
number of holes at base determines the flow from emitter to collector.
• So, emitter emits electrons acting as source of electrons. The collector collects these electrons
acting as absorbent and the naming resulted from this fact.
Directions of three currents are shown in figure 3.3.

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Fig. 3.3: Transistor operation & direction of currents

Characteristics of BJT
We are still considering an NPN transistor and by virtual agreement, current directions are opposite
to electron-flow directions. Because of the collective statements we made above we can say that,
we use a small base current to induce a large collector current. This large collector current is
proportional to the base current because of the role of the small number of holes there in base. So,

IC = IB………………………………………………………………………………………………..3.1
Where, IE is emitter current, IB is base current, IC is collector current.
Current relationship simply obtained from the current directions stated in fig 3.3:

IE = I C + I B …………………………………………………………………………………………….3.2
When emitter circuit is opened, there is no supply of free electrons from emitter to collector. Even then,
there will be small collector current called reverse saturation collector current

ICBO. This is due to thermally generated electron-hole pairs. Even during normal operation, ICBO is

present. We define another equation adding the effect of ICBO.

I C = αdc IE + ICBO ………………………………………………………………………………………3.3

αdc is fraction of emitter current which flows to collector. Since ICBO is very small,
αdc = I C / IE…………………………………………………………………………………………………3.4
we have also another parameter from eq. 3.1

βdc = I C / IB………………………………………………………………………………………………….3.5

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Dividing eqn 3.2 by I C we have

1/ αdc =1 + 1/ βdc and αdc = βdc /1+ βdc………………………………………………….3.6

Because of our knowledge on how a PN junction operates we would expect the base voltage to be about
0.65 to 0.7 volt positive (forward biased) with respect to the emitter, and to have electrons move from
emitter to base and leave the device at that point. With the collector junction reverse biased, we would
expect no current to flow through that junction too. But something happens inside the base region. The
forward bias on this junction does indeed attract electrons from the emitter into the base, but then the
forward momentum of the electrons carries them across most of the base region and into the depletion
region around the collector junction. From there, the higher positive collector voltage attracts these
electrons across the collector junction and into the collector region. A small amount of current does still
leave the device through the base contact, but most of the current is diverted through the collector

instead. In this way, the small base current IB controls the much larger collector current IC. I C is

proportional to IB. This is generally known as the transistor effect.

In the case of a PNP transistor, holes will be drawn from the emitter into the base region by the forward
bias, and will then be pulled into the collector region by the higher negative bias.
Example 1: If the emitter current of a transistor is 8 mA and IB is 1/100 of IC, determine the levels
of IC and IB.
Example 2: (a) Given that αdc = 0.987, determine the corresponding value of βdc.
(b) Given βdc = 120, determine the corresponding value of α.
(c) Given that βdc =180 and IC =2.0 mA, find IE and IB.
3.3 BJT CONFIGURATIONS
Transistor is 3-terminal device. For applications such as amplifier circuit, four terminals are required –
two for input and two for output. So, one of the three terminals of transistor should be made common
for both input and output in such cases. Accordingly, we will end up with three types of configurations:
• Common base (CB) configuration
• Common emitter (CE) configuration
• Common collector (CC) configuration
3.5.1 Common base configuration

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 Fig. 3.4: Common Base configuration
Base is common, emitter is input terminal, and collector is output terminal. We will consider two
characteristics: input characteristics and output characteristics

Input characteristics:

Plot of input current IE versus input voltage VEB for various values of output voltage VCB is shown in fig
3.5.

As VEB is increased, IE increases similar to diode characteristics

If VCB is increased, then IE increases slightly. This is due to the increase in electric field aiding the flow
of electrons from emitter.

Fig 3.5: CB Input and Output characteristics

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Output characteristics

Plot of output current IC versus output voltage VCB for various values of input current IE also shown in
fig 3.5 above.
Three regions can be identified: namely active, cutoff and saturation

Active region: Region to the right of y-axis, above IE =0 curve, where the curves are linear.

IE is positive nonzero (i.e., E-B diode is forward biased) and VCB is positive (i.e., C-B diode is reverse
biased).

When VCB is increased, IC increases slightly. This is because, when VCB is increased, depletion region
width at C-B junction increases, so effective base width decreases and IB decreases. Hence IC increases.
This effect is known as early effect (also called base width modulation).

If IE is increased, IC also increases when IE =0, IC = ICBO (reverse saturation Collector current in

common Base with emitter Open). ICBO doubles for every 10 degree centigrade rise in temperature.

Cutoff region: Region below IE =0 curve.

Here IE is less than zero (E-B diode is reverse biased) and VCB is positive (C-B diode is

reverse biased) .Transistor is said to be in OFF state since IC is zero.

Saturation region: Region to the left of y-axis, above IE =0 curve.

Here IE is positive nonzero (E-B diode forward biased) and VCB is negative (C-B diode is

forward biased) IC decreases exponentially in this region.

Input resistance: Ratio of change in VEB to corresponding change in IE, with VCB held constant.

Ri=∆VEB / ∆IE with VCB constant……………………………….3.7

Output resistance: Ratio of change in VCB to corresponding change in IC, with IE held constant.

Ro=∆VCB /∆IC with IE constant

Current gain: Ratio of change in collector current to change in emitter current, with VCB held constant

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αac= ∆ IC /∆ IE with VCB constant

Voltage gain: Ratio of change in output voltage to change in input voltage with IE held constant.
Av=∆VCB /∆VEB with IE constant.

Note that αac and αdc are approximately equal. Their value lies between 0.9 and 0.998.
Example 3: (a) Using the characteristics of the following figure, determine IC if VCB = 10 V and
VBE =800 mV.
(b) Determine VBE if IC =5 mA and VCB =10 V.

3.5.2 Common emitter configuration

Emitter is common or reference to base terminal and collector terminal, base is input terminal and
collector is output terminal.
Again we get two characteristics: input characteristics and output characteristics.

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 Fig. 3.6: Common-Emitter configuration
Input characteristics

Plot of input current IB versus input voltage VBE for various values of output voltage VCE shown in fig
3.7.

As VBE is increased, IB increases similar to diode characteristics.

If VCE is increased, then IB decreases slightly. This is due to early effect.

Fig. 3.7: CE Input and Output configurations

Output characteristics

Plot of output current IC versus output voltage VCE for various values of input current IB. shown in fig
3.7 above. Three regions can be identified again: Active, cutoff and saturation.

Active region: Region to the right of VCE Sat, above IB =0 curve, where the curves are linear Note that
VCE = VCB + VBE
If VCE > VCE Sat, then VCB becomes positive (i.e., C-B diode is reverse biased) VCE Sat is around 0.3V for
silicon transistor. If IB > 0, then it means E-B diode is forward biased.

When VCE is increased, IC increases slightly due to early effect. Note that slope of curve is more than

that of CB o/p characteristics. If IB is increased, IC also increases.

When IB =0, IC= ICEO (Collector current in common Emitter with base Open). ICEO is much more than
ICBO of CB configuration.
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Cutoff region: Region below IB =0 curve

Here E-B diode and C-B diode are both reverse biased. Transistor is said to be in OFF state since IC is
almost zero.

Saturation region: Region to the left of VCE Sat and right of y-axis.
Here E-B diode and C-B diode are both forward biased.
Input resistance

Ratio of change in VBE to corresponding change in IB, with VCE held constant.

Ri = ΔVBE / ΔIB with VCE constant

Output resistance
Ratio of change in VCE to corresponding change in IC, with IB held constant.

Ro= ΔVCE / IC with IB constant

Current gain
Ratio of change in collector current to change in base current, with VCE held constant

βac = ΔIC/ ΔIB with VCE constant

Voltage gain
Ratio of change in output voltage to change in input voltage with IB held constant.

AV= ΔVCE / ΔVBE with IB constant

Note again that βac = βdc = β

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Example 4: (a) Using the characteristics of the above figure, determine IC at IB =30 µA and VCE =
10 V.
(b) Using the characteristics of the above figure, determine IC at VBE =0.7 V and VCE = 15 V.

3.5.3 Common collector characteristics

Common collector characteristic is similar to that of common emitter, hence not discussed here.
3.4 BIASING METHODS
Introduction
One of the most common applications of transistors that should be stated repeatedly is its role in
amplifier circuits. For a faithful amplification we require that transistor be operated in active region
throughout the duration of input signal. To ensure this, proper dc voltages should be applied which
result to a situation called biasing. But first of all, how can we sense and measure the effect of biasing?
Operating point

When no input signal is applied to transistor circuit, and only dc voltages are supplied, currents IC, IB
and voltage VCE will have certain values. If these values are plotted over the transistor output
characteristics, the point we get is called ‗Operating point‘. It is also called ‗Quiescent point‘ or just Q-
point.

Fig. 3.8: Quiescent point

In above figure, currents IBQ (the value of IB at Q), ICQ and voltage VCEQ are plotted at point Q. In
practice, we have to choose Q-point according to our requirement. If we want to operate in the middle
of active region, we may choose Q as Q-point. For instance in the case of the so called Class A
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amplifiers (to be discussed later) we want Q-point to be in the middle of active region. If we want to
operate near saturation, we may choose Q‘ (Q prime) as Q-point. If we want to operate near cutoff, we
may choose Q‘‘ as Q-point too. Note that if no biasing is used, Q-point will be in the origin of the
graph. So, biasing is used to fix the Q-point according to our need.
Types of bias
• Fixed bias Circuit
• Voltage divider bias (Self bias)
Fixed Bias Circuit
Base resistor RB is connected to Vcc (Instead of VBB) negative terminal of Vcc is not shown. It is
assumed to be at ground.

Fig. 3.9: Fixed bias circuit

Applying KVL to the input side, we get

VCC- IB RB - VBE=0
Rearranging, we get

IB = VCC - VBE / RB …………………………………………………….3.8

VCC is constant, VBE is almost constant (0.7V for silicon). So by selecting proper RB, we can fix IB as
required.
Applying KVL to output side we get:

VCC - IC RC- VCE =0

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VCC - IC RC = VCE……………………………………………………….3.9
IC is related to IB by β.
So, VCE can be fixed by selecting proper RC. Eq (3.9) is an equation of straight line with VCE and IC as
two variables. This straight line is called load line. Again, output characteristic is also a function of

same two variables. Intersection of load line and output characteristic for particular IB gives the
common solution. This is nothing but Q-point.
Figure 3.10 shows load line superimposed on output characteristics, with Q-point marked. Now if we
vary RB, Q-point moves along the load line. If RB is held constant, and RC is varied, then slope of load
line varies. If RB and RC are held constant and VCC is varied, then load line shifts, maintaining same
slope.
From these graphs we infer that, with everything else held constant, if R B is increased, transistor goes
towards cutoff, if RB is decreased, transistor goes towards saturation. Again with everything else held
constant, if RC is increased, transistor goes towards saturation, if RC is decreased, transistor goes
towards active region. Still With everything else held constant, if V CC is increased, transistor goes
towards active region, if VCC is decreased, transistor goes towards saturation.
Advantages of fixed bias
• Simple to analyze and design
• Uses very few circuit components
Disadvantages of fixed bias
• Q-point is not stable. i.e., if temperature varies, β will vary, hence IC will vary.
• If transistor is replaced by another transistor having different β then Q-point will
Shift.

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Fig. 3.10: Load line variations

Example 5: Determine the following for the fixed-bias configuration of figure shown below.
(a) IBQ and ICQ.
(b) VCEQ.
(c) VB and VC.
(d) VBC.

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Example 6: Given the load line of Figure below and the defined Q-point, determine the required
values of VCC, RC, and RB for a fixed-bias configuration.

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Fixed base biasing with emitter resistor
In the fixed biasing we have seen that Ic varies with β this implies that a replacement of a defective
transistor will result in different β and Qpoint fluctuates. One way of improving this is to connect a
resistor to the emitter terminal. It is just to connect a resistor Re to emitter terminal of the figure below.

Taking KVL from ground to ground, we have

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VCC – IB Rb- IERe- VBE=0
But, IE= (β +1) IB
VCC = IB (Rb + (β +1)Re) + VBE
IB= VCC – VBE/[Rb+(1+ β)Re] = VCC - VBE/[Rb + β Re]
IC = β IB = VCC - VBE /(Rb/ β) + Re = VCC - VBE/Re with the condition Re>> Rb/ β

IC is independent of β but in order to fulfill the above condition Re must be very large. We have to

maintain very large VCC to maintain the current in the desired value. The other possibility is to keep Rb
small but this will decrease the voltage drop across Rb to the extent that it becomes less than the voltage
drop across Rc i.e CB junction becomes forward biased.
Example 7: For the emitter bias network of Figure below, determine:
(a) IB.
(b) IC.
(c) VCE.
(d) VC.
(e) VE.
(f) VB.
(g) VBC.

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Voltage divider bias or Self bias

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Uses two resistors R1 and R2 instead of RB and RE is connected between emitter and ground here too.

Fig. 3.11: Self bias circuit

There are two methods of analysis:

• Exact method
• Approximate method
Exact method
Input side of the above circuit is redrawn for a dc analysis below in fig 3.13(a)

Fig 3.12: in put side redrawn circuit and Thevenin‘s network

Fig (a) should be replaced by Thevenin‘s equivalent circuit shown in fig (b).VTH is the open circuit
voltage between points A & B in fig (a) given by:
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VTH= VCC R2 / [R1+R2 ]…………………………………………………..3.10

Fig. 3.13: Equivalent circuit

RTH is the resistance seen between A & B with VCC replaced by short circuit. See fig 3.12.
RTH = R1//R2 = R1R2/[R1+R2]……………………………………….3.11
Self bias circuit with its input loop replaced by Thevenin‘s equivalent circuit is shown in fig
3.13. Applying KVL to the input loop we get:

VTH – IB Rth- VBE- IE R e=0……………………………………………3.12 a

Substituting IE =(β+1) IB
IB= VTH – VBE / [Rth + (β+1) Re]………………………………………3.12 b
Applying KVL to the output loop, we get

VCC – IC RC- VCE- IE RE =0……………………………………………3.13

Note that, VC= VCC - IC RC where, VC is voltage from collector to ground and,
VE= IE RE where, VE is voltage from emitter to ground.
Since β >> 1, we have (β+1) ≈ β. If βRE >> RTH, then equation (3.12 b) reduces to:

IB = VTH - VBE / β Re……………………………………………………3.14

And IC= βIB = [VTH - VBE ]/ Re………………………………………..3.15
Since equation for IC does not contain β, we say that IC is independent of temperature variation and
transistor replacement.
Example 8: Determine the dc bias voltage VCE and the current IC for the voltage-divider
configuration of Figure shown below.

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Approximate method

Self bias circuit is redrawn below. From the figure we can see that compared to currents I1 and I2 (in
mA), IB (in μA) is very small.

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Fig. 3.15. Self bias circuit
So, voltage from base to ground is given by voltage divider rule:

VB= VCC R2/R1+R2

VB = VBE+ VE
IE = VE/Re
IC can be calculated if β is given, or else if β is very high then IC ≈IE.

VCE is given by equation (3.13).Here again, IC is independent of β, and hence it is immune to

temperature changes and replacement of transistor.
Approximate method is fairly accurate only if the following condition is satisfied:
βRe>=10R2
Advantages of voltage divider bias
• Collector current, and hence Q-point is independent of β. Hence Q-point is stable against variation
in temperature and replacement of transistor.
Disadvantages of voltage divider bias
• Analysis and design is complex
• More circuit components required

Example 9: Determine the dc bias voltage VCEQ and the current ICQ using approximate for the
Figure shown below.

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3.5 SMALL SIGNAL BJT AMPLIFIERS AND PARAMETRIC
REPRESENTATIONS
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As far as we are concerned with transistors application as small signal amplifiers the most common
transistor parameters involved are defined below.
β is the common emitter current gain as obtained from the common emitter configuration.
α is the common base current gain as obtained from common base configuration.

ICBO are leakage (of small amplitude) currents that run from collector to base.
ICEO are still leakage currents flowing from collector to emitter.

The governing relations are

β= α/ 1-α and ICEO = ICBO /1- α………………………..3.16

Under any kind of configuration the following relationship holds true.

IC= α IE
β= IC / IB= I input/ I output
Ai= IC / IB = β…………………………. Current gain in common emitter configuration
Ai= IC / IE= α………………………….. Current gain in common emitter configuration
Transistor parameterization: two port network, the hybrid model and linear analysis of
transistors.
Two port networks are widely used to model transistors, transformers, transmission lines and other
circuit blocks.

Ii Io
+ +
Vi
NETWORK Vo
- -

Fig 3.16 A typical two port network

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This two port network can be mathematically modeled in to six set of matrix representations taking two
of the four variables as independent. Four of these six models differ on the nature of input output
impedances and further explanation is beyond the scope of this material.
The hybrid model is taken as the most suitable for modeling transistors. This model could be stated by
using two linear equations.
Vi = h11Ii + h12 Vo…………………………………i

Io = h21Ii + h22 Vo…..............................................ii

Here we see that Ii and Vo are independent and Vi and Io are dependent variables.
Now, h11 = Vi/Ii | Vo=0 (input impedance when output is short)
h12= Vi/Vo| Ii=0 (inverse transfer voltage gain when input is open)
h21 = Io/Ii |Vo=0 (current gain when output is short)
h22= Io/Vo |Ii=0 (output admittance when input is open)
Common names given to these new parameters when we apply this model to transistors are given
below.
h11 = hi h12= hr h21= hf and h22= ho = 1/ro
Finally we can model our transistor as indicated in the following figure. This model is common to any
types of configurations discussed earlier.

hi
+ +

Vi hrVo ho
AC hf Ii AC Vo

- -

Fig 3.17 Hybrid Transistor model

The analysis that results from this model is concerned with four quantities namely
Current gain AI= Io/Ii
Voltage gain AV=Vo/Vi
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Input impedance Ri=Vi/Ii
Output impedance Ro=Vo/Io.
Additionally we have power gain (Pgain).
But keep in mind that the analysis is made based on the following figure. The block transistor in the
figure is simply the model we have sketched above.

+ +

Vi
TRANSISTOR Vo
- -

Fig 3.18 typical small signal BJT amplifier

The above figure is redrawn below with the block transistor replaced by the detailed model discussed
above. We use the exact method if ho or Ro is mentioned otherwise we use the approximate method.
So, the analysis generally depends on the following general model.

hi
+ +
Rs
-
Vi ho RL
hrVo AC hf Ii AC Vo
AC
+
- -

Fig 3.19. The hybrid model as small signal amplifier.

Current gain:
AI = Io/Ii
Io = hf Ii + Voho…………………i
Io= -Vo/RL => Vo= -IoRL …….ii
Now, Io= hf Ii + (-IoRL)ho
Finally we see that Io/Ii = AI= hf/ 1+RLho…… exact value………………….3.17a
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If RLho is very small this reduces to
AI=hf……………………………………………………………………………3.17b
Voltage gain:
Two types of voltage are available. The overall voltage gain(Vo/Vs) and normal voltage gain(Vo/Vi).
Vo/Vi= -IoRL/Vi = -(AI*Ii) RL/Vi
= -AI RL *(Ii/Vi)
= AI RL/Ri………………………………………………..3.18
The negative sign is removed here since we are concerned with magnitude only.
The overall voltage gain is obtained by setting
Vi =(Rs/Rs+Ri)Vs
Hence AVs = Vo/Vs = Vo/[V1(Rs+Ri)/Rs] = [Rs/Rs+Ri]*[AV]…………..3.19
But we should first find Ri.
Input impedance:
Ri=Vi/Ii
But Ri Ii=hi Ii + hrVo KVL around the first loop.
Ri = [hi Ii + hr(IoRL) ]/Ii
= [hi Ii + hr(AI Ii RL) ]/Ii
= hi –AI RL hr……….exact value…………………………….2.20a
Ri=hi…….approximately…………………………………………3.20b
Output impedance:
Ro = Vo/Io = -Io RL/Io
Ro=RL…………………………………………………………………….3.21
Power gain:
This is simply the product of voltage and current gains
Pgain = AV*AI……………………………………………………………3.22

4.1. Introduction
Field Effect Transistors (FETs) are three terminal electronic devices used for variety of
applications, mostly similar to BJTs, such as amplifiers, electronic switches and impedance

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matching circuits. However, the field effect transistor differs from bipolar junction transistor in the
following important characteristics.
 In FETs an Electric Field is established to control the conduction path of output
devices without the need for direct contact between the controlling and controlled
quantities.
 Its operation depends upon the flow of majority carriers (one-polarity), hence, uni-
polar device.
 It exhibits high input impedance, typically, in many mega ohms.
 FET‘s are less sensitive to temperature variations and because of their construction
they are more easily integrated on IC‘s.
 FET‘s are also generally more static sensitive than BJT‘s.

4.2. Types of FET

There are two types of field effect transistors. These are Junction Field Effect Transistor (JFET)
and Metal-Oxide Field Effect Transistor (MOSFET).
4.2.1. Junction Field Effect Transistors (JFET)
The basic Structure of junction field effect transistor is formed from a bar of n/p semiconductor
material called channel with a region of p/n material embedded in each side. The n-channel JFET is
constructed by the n-type material that forms the channel between the embedded layers of p-type
material. The top of the n-type channel is connected through an ohmic contact to a terminal referred
to as the drain (D), while the lower end of the same material is connected through an ohmic contact
to a terminal referred to as the source (S). The two p-type materials are connected together and to
the gate (G) terminal as shown in figure 4.1(a). In the same way, the p-channel JFET is constructed
by the p-type material that forms the channel between the embedded layers of n-type material as
shown in figure 4.1(b). In practice, the channel is always lightly doped than the gate. In the absence
of any applied potentials the JFET has two p-n junctions under no-bias conditions. The result is a
depletion region at each junction that resembles the same region of a diode under no-bias
conditions.

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 Figure 4.1: Junction Field Effect Transistors basic construction and their symbol
Operating characteristics of JFET

To demonstrate the i-v characteristics of JFET lets use the following n-channel JFET circuit layout
shown in figure 4.2. For normal operation of JFET the two junctions made between the channel and
the two gates should be reverse biased. As can be seen from the circuit diagram there are two
possible conditions to control the variation of channel current, either changing the voltage level of
VGG or VDD. Depending on this there are two operating conditions.
The p-channel FET is similar to the n-channel except that the voltage polarities and current
directions are reversed. And regarding response time, as electrons are more mobile than holes, there
will be considerable delay of current in p-channels compared to n-channel FETs.

Figure 4.2: n-channel JFET circuit connection

Case1: VGS = 0, VDS increasing to some positive value

A positive voltage VDS has been applied across the channel and the gate has been connected directly
to the source to establish the condition VGS = 0 V. The instant the voltage VDS is applied, the
electrons will be drawn to the drain terminal, establishing the conventional current ID with the
defined direction. The path of charge flow clearly reveals that the drain and source currents are
equivalent (ID = IS). For a few volts increase in VDS, the current will increase as determined by
Ohm‘s Law (See fig. 4.3a). But further increase in VDS begins to make the depletion region near the

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drain to be wider and wider than the source ends because the relative voltage level near the drain is
greater than the source. This causes the channel resistance to change See fig. 4.3(b). As VDS
increases and when it gets large enough to cause the two depletion regions touch near the drain,
pinch-off occurs and no further increase in ID. At this point, ID maintains the saturation level
defined as IDSS and the voltage is called pinch-off voltage Vp. In this region JFETs can act as
constant current source, See fig. 4.3(c).

Case 2: VGS < 0 (VGS varying)

As VGS becomes more negative, the width of the depletion region increases uniformly across the
channel causing an increase in channel resistance. See fig. 4.4 (b). At this condition, the effect of
varying VDS is to establish depletion regions similar to those obtained with VGS=0V but a lower
level of VDS is required to reach the saturation level. If VGS is taken up to a position where the two
depletion regions are pinched, then the device will be turned off and any change in VDS will
produce no current. See fig. 4.4 (c).

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Therefore, the result of applying a negative bias to the gate is to reach the saturation level at a lower
level of VDS. The resulting saturation level for ID has been reduced and in fact will continue to
decrease as VGS is made more and more negative. The region to the right of the pinch-off locus on
the fig. 4.5 is the region typically employed in linear amplifiers (amplifiers with min distortion of
the applied signal) and is commonly referred to as the constant-current, saturation, or linear
amplification region. The region to the left of the pinch-off locus of the figure is referred to as the
ohmic or voltage-controlled resistance region. In this region the JFET can actually be employed as
a variable resistor (possibly for an automatic gain control system) whose resistance is controlled by
the applied gate-to-source voltage. In the ohmic region JFET can be used as variable resistors of
value given as

ro
rd 
(1  VGS )2
VP

Where ro is the resistance of the channel before applying VGS (VGS=0) and Vp is the pinch-off
voltage.

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 Figure 4.5: current voltage relationships curve

Transfer Characteristics
In a JFET the relationship of VGS (input) and ID (output) is a little more complicated, and is given
by Shockley‘s equation:
2
  V 
I D  I DSS 1   GS 
  V p ( pinchoff ) 

The transfer characteristics defined by Shockley‘s equation are unaffected by the network in which
the device is employed. The transfer curve can be obtained using Shockley‘s equation as shown in
Fig. 4.6.

Figure 4.6: transfer charactersitcs curve

4.2.2. Metal Oxide Field Effect Transistors (MOSFETs)
MOSFETs have characteristics similar to JFETs and additional characteristics, but they have added
features of characteristics extended to the region of opposite polarities of VGS that make them very
useful. There are two types of MOSFET; Depletion-Type and Enhancement-Type MOSFET.
[Link]. Depletion-Type MOSFET
The basic construction of the n-channel depletion-type MOSFET is provided in Fig.4.7. The Drain
(D) and Source (S) are connected to the n-doped regions. These n-doped regions are connected via

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an n-channel. This n-channel is connected to the Gate (G) via a thin insulating layer of SiO2. The n-
doped material lies on a p-doped substrate that may have an additional terminal connection called
SS.

Figure 4.7: Construction of n channel Depletion type MOSFET and symbol

Operational Characteristics of Depletion-type MOSFET
If the VGS is set to zero and VDS is made to increase, the effect will be to establish a current similar
to that established through the channel of the JFET. But if V GS is increase negatively, it will tend to
pressure electrons toward the p-type substrate and attract holes from the p-type substrate as shown
in Fig. 4.8. Depending on the magnitude of the negative bias established by V GS, a level of
recombination between electrons and holes will occur that will reduce the number of free electrons
in the n-channel available for conduction. The more negative the bias, the higher the rate of
recombination. The resulting level of drain current is therefore reduced with increasing negative
bias for VGS as shown. This is called depletion mode operation.
For positive values of VGS, the positive gate will draw additional electrons (free carriers) from the
p-type substrate due to the reverse leakage current and establish new carriers through the collisions
resulting between accelerating particles. As the gate-to-source voltage continues to increase in the
positive direction. This is called enhancement mode operation.

Figure 4.8:Operation of depletion type MOSFETs Figure 4.9: operation characteristics of n-

channel Depletion type MOSFETs

[Link]. Enhancement-Type MOSFET

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Although there are some similarities in construction and mode of operation between depletion-type
and enhancement-type MOSFETs, the characteristics of the enhancement-type MOSFET are quite
different from anything obtained thus far.
The Drain (D) and Source (S) connect to the n-doped regions. The Gate (G) connects to the p-
doped substrate via a thin insulating layer of SiO2. There is no channel. The n-doped material lies
on a p-doped substrate that may have an additional terminal connection called SS.

Figure 4.10: n-Channel enhancement-type MOSFET and symbol

Basic Operation
If VGS is set at 0 V and a voltage applied between the drain and source of the device, the absence of
an n-channel (with its generous number of free carriers) will result in a current of effectively zero
amperes—quite different from the depletion-type MOSFET and JFET where ID=IDSS.
The Enhancement-type MOSFET only operates in the enhancement mode. Hence, V GS is always
positive and as VGS increases, ID increases. But if VGS is kept constant and VDS is increased, then ID
saturates (IDSS) after the saturation level, VDSst is reached.

Figure 4.11: Drain characteristics of an n-channel enhancement-type MOSFET

To determine ID given VGS:
( )
Where, VT is threshold voltage or voltage at which the MOSFET turns on.
k is a constant that can be determined by using the formula:

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 ( )

( ( ) )
VDSsat can also be calculated as

Example1: Given IDSS = 9 mA and VP=3.5 V, determine ID when:

(a) VGS = 0 V.
(b) VGS=-2 V.
(c) VGS=-3.5 V.
(d) VGS=-5 V.
4.3. Biasing techniques
There are different biasing techniques for FET circuits: some of commonly used are fixed bias, self-bias and voltage
divider bias.
4.3.1. Fixed-bias configuration
Consider the following simplest biasing configuration circuit for the n-channel JFET,

Figure 4.12: Fixed-bias configuration. Figure 4.13: Network for dc analysis.

The coupling capacitors (C1 and C2) are open circuits for the dc analysis as is shown in figure
4.13; it would be short circuit for the ac analysis. Attempting the circuit for dc analysis:

This is shown in the above figure replacing RG with short circuit.

Applying Kirchhoff‘s voltage law in the clockwise direction of the indicated loop of Fig. 4.13 will
result in

Since VGG is a fixed dc supply, the voltage VGS is fixed in magnitude, resulting in the notation
―fixed-bias configuration.‖ And the drain current ID is controlled by:

( )
The level of ID is simply determined from a vertical line drawn
by taking the fixed level of VGS which is superimposed as a
vertical line at VGS= - VGG, which is shown in figure 4.14 below.

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 Figure 4.14: Finding the solution for the fixed-bias configuration
Hence, the solution for a fixed bias configuration is the intersection of the two curves in the above
figure, and this is commonly referred to as quiescent point or simply Q-point. Note in the figure
that the q-point of ID is determined by drawing a horizontal line across the intersection point of the
two curves and crossing the ID axis.
The drain-to-source voltage of the output section can be determined by applying Kirchhoff‘s
voltage law as follows:

Note from figure 4.13 that, the values of the source, drain, and gate voltages with respect to ground,
in relation to VDS and VGS are given by:

But VDS is given by:

So

In addition, VGS is given by:

Example 2: Determine the following for the network of Figure shown below.
(a) VGSQ.
(b) IDQ.
(c) VDS.
(d) VD.
(e) VG.
(f) VS.

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4.3.2. Self-bias configuration

Here a resistor RS is introduced in the source leg of the configuration, which is used to determine
the controlling gate-to-source voltage (VGS). This is shown in the following figure.

Figure 4.15: JFET self-bias

configuration. Figure 4.16:
DC analysis of the self-bias
configuration.

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Replacing the capacitors (C1 and C2) with open circuit and RG with short circuit (since IG=0A),
will result in the network of dc analysis shown in figure 4.16 above.
The current through RS is the source current IS, but IS= ID and

For the indicated loop of figure 4.16,

 VGS  VRS  0
VGS  
Note in this case that VGS is a function ofVRthe
S
 output
 I D RS current ID and not fixed in magnitude as
occurred for the fixed-bias configuration.
The solution of a self-bias configuration is obtained by substituting VGS into the drain current
equation as follows:

( ) ( ) ( )
Solving this quadratic equation will result in appropriate solution of ID.
The graphical analysis can also be used to determine the operating point, which is the intersection
point of the device characteristic curve and a straight line curve drawn using the equation
VGS   I D RS , as shown in the following figure.

Figure 4.17: Finding the solution for the self-bias

configuration

Applying Kirchhoff‘s voltage law to the output circuit, the level

of VDS can also be determined:

( )
In addition,

Example 3: Determine the following for the network of Figure shown below.
(a) VGSQ.
(b) IDQ.
(c) VDS.
(d) VS.
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(e) VG.
(f) VD.

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4.3.3. Voltage divider bias configuration

Figure 4.18 Voltage-divider bias arrangements. Figure 4.19: Redrawn network of Fig. 4.18 for dc analysis.

As shown in the figure 4.19 above, all the capacitors are replaced with open circuit and the voltage
VDD is separated in to two equivalent sources, which split the input and output regions of the
network. And since IG = 0A, R1 and R2 are in series and this will result in VG to be equal with VR2.
Now the voltage VG is given by using voltage divider rule:

Applying Kirchhoff‘s voltage law in the clockwise direction for the indicated loop of figure 4.19:

Substituting , we get:

This is an equation of a straight line, and the intersection point of this curve with the device transfer
curve will result in the operating point and the corresponding levels of ID and VGS. It looks like
figure 4.20 shown below.

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Figure 4.20: Finding the solution for the
Voltage divider bias configuration

Once the quiescent values of IDQ and VGSQ

are determined, the remaining network analysis (for the output circuit) can be performed in the
usual manner. That is,

( )

The similarities in appearance between the transfer curves of JFETs and depletion type MOSFETs
permit a similar analysis of each in the dc domain. The primary difference between the two is the
fact that depletion-type MOSFETs permit operating points with positive values of VGS and levels of
ID that exceeds IDSS. In fact, for all the configurations discussed thus far, the analysis is the same if
the JFET is replaced by a depletion-type MOSFET.

The transfer characteristics of the enhancement-type MOSFET are quite different from those
encountered for the JFET and depletion-type MOSFETs, resulting in a graphical solution quite
different from the preceding sections. First and foremost, recall that for the n-channel
enhancement-type MOSFET, the drain current is zero for levels of gate-to-source voltage less than
the threshold level VGS(Th), as shown in Fig. 4.21. For levels of VGS greater than VGS(Th), the
drain current is defined by
ID =k(VGS - VGS(Th))2

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 Figure 4.21: Transfer characteristics of an n-channel enhancement type MOSFET
To complete the curve, the constant k of the above equation must be determined from the
specification sheet data by substituting and solving for k as follows:

Example 4: Determine the following for the network of Figure shown below.
(a) IDQ and VGSQ.
(b) VD.
(c) VS.
(d) VDS.
(e) VDG.

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Important relationships
A number of important equations and operating characteristics have been introduced in the sections
above that are of particular importance for the analysis to follow for the dc and ac configurations.
Here the relation between JFET and BJT is given below.

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Feedback Biasing Arrangement
A popular biasing arrangement for enhancement-type MOSFETs is provided in Fig.4.22. The
resistor RG brings a suitably large voltage to the gate to drive the MOSFET ―on.‖ Since IG=0 mA
and VRG= 0 V, the dc equivalent network appears as shown in Fig. 4.23.

Figure 4.22: Feedback biasing arrangement figure 4.23: DC equivalent of the network of Fig.
4.22.

A direct connection now exists between drain and gate, resulting in

For the output circuit,

VDS = VDD - IDRD
Hence,
VGS = VDD - IDRD
The result is an equation that relates the same two variables and enables to plot on the
characteristics graph with the resulting operating point as shown in Fig. 4.24.

Figure 4.24: Determining the Qpoint

Voltage-Divider Biasing Arrangement

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A second popular biasing arrangement for the enhancement-type MOSFET appears in Fig. 4.25.
The fact that IG = 0 mA results in the following equation for VGG as derived from an application of
the voltage-divider rule:

Figure 4.25: Voltage-divider biasing arrangement for an n-channel enhancement MOSFET

Applying Kirchhoff‘s voltage law around the indicated loop will result in:

Since the characteristics are a plot of ID versus VGS on the characteristics curve, a solution
determined at their intersection. Once IDQ and VGSQ are known, all the remaining quantities of the
network such as VDS, VD, and VS can be determined.

Important relationships

A number of important equations and operating characteristics have been introduced in the sections
above that are of particular importance for the analysis to follow for the dc and ac configurations.
Here the relation between JFET and BJT is given below.

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Example 4.2: Determine the following
parameters for the network shown below: IDQ
and VGSQ, VD, VS, VDS, and VDG

Solution:
To determine the operating point, first find
the intercepts on the ID and VGS axes on
which the straight line passes.

( )

( )

The intersection point of this line and the transfer curve gives us the Q-point as shown below:
IDQ=2.4mA and VGSQ=-1.8V. This can also be determined using the quadratic equation obtained by
substituting the value of VGS into the i-v characteristics equation.

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 = 16V- 2.4mA (2.4KΩ) =10.24V
= (2.4mA)(1.5KΩ)
= 3.6V
( ) or
( )
The voltage VDG is easily determined by:

4.4. Small-Signal FET model and parametric representation

The small-signal h-parametric model of FET is represented as in the figure 4.26.
D
G D
+
G FET vgs gmvgs rd
-
S S
S
Figure 4.26: FET small signal model
Input impedance ( ri)
As the gate current (IG) is nearly zero, we can assume the input impedance of FET to be very large.

Trans-admittance (gm)

For JFET’s, * ( ⁄ )+ * ⁄ +, let

* ⁄ +
And for MOSFET’s,
[ ( )] [ ]
Output impedance (rd )
, where yos is defined as the output-admittance of the transistor
Example 4. 2: For the self-bias n-channel JFET shown in the figure below, calculate
a) the input and the output impedance ,and
b) The voltage gain. assume yos=20μS

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 VDD =20V

RD 3.3KΩ
C2
v0
C1
IDSS=8mA Z0
vi VP= -6V

Zi

RG 1MΩ RS 1KΩ C3

Solution:
DC Analysis;

( ) , but from loop 1

( )
( ) ( ) ,
( )

0 ,
Since ,
From loop 2, ( ) ( )
And
AC Analysis:

* ⁄ + = * + = 1.51mS

Ac equivalent circuit: Short all DC sources and capacitors

vi v0
+

RG vgs gmvgs rd RD

a) Input impedance,
,
b) Output impedance,
( )
c) Voltage gain,
=

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 Chapter Five
Frequency Response of BJT and FET
Introduction
The analysis thus far has been limited to a particular frequency. For the amplifier, it was a
frequency that normally permitted ignoring the effects of the capacitive elements, reducing the
analysis to one that included only resistive elements and sources of the independent and controlled
variety. We will now investigate the frequency effects introduced by the larger capacitive elements
of the network at low frequencies and the smaller capacitive elements of the active device at the
high frequencies. Since the analysis will extend through a wide frequency range, the logarithmic
scale will be defined and used throughout the analysis and concept of the decibel is introduced in
some detail.

Logarithms
Relationship between the variables of a logarithmic function

Common logarithm : x  log10a

Natural logarithm : y  log e a
The two are related by: log e a  2.3log10 a
log101  0

a
log10  log10 a  log10 b
b

1
log10  log10 b
b

log10 ab  log10 a  log10 b

Semi log
Most graph paper available is of the semi log or double-log (log-log) variety. The term semi
(meaning one-half) indicates that only one of the two scales is a log scale, whereas double-log
indicates that both scales are log scales. A semi log scale appears in Fig. below.
Vertical scale is linear scale with equal divisions. The distance from log10 1=0 to log10 2 is 30% of
the span. Plotting a function on a log scale can change the general appearance of the waveform as
compared to a plot on a linear scale. Straight line plot on a linear scale can develop a curve on a log
scale and nonlinear plot on a linear scale can take on the appearance of a straight line on a log plot.

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 Fig.1 Semi log graph paper

Fig.2 identifying the numerical values of the tic marks on a log scale

DECIBELS
Decibel is a measure of the difference in magnitude between two power levels, P1 and P2. The
term decibel is from the fact that power and audio levels are related on a logarithmic basis. The
terminal rating of electronic communication equipment is commonly in decibels.

Bel-is too large unit of measurement for practical purposes, so decibel (dB) was defined such that
10 decibels = 1 bel.

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The reference power (P1) is generally accepted to be 1mW. The resistance to be associated with the
1-mW power level is 600 Ω, chosen because it is the characteristic impedance of audio
transmission lines. When the 1-mW level is employed as the reference level, the decibel symbol
frequently appears as dBm.

There exists a second equation for decibels that is applied frequently. It can be best described
through the system of [Link]. For Vi equal to some value V1, P1=V21/Ri, where Ri, is the input
resistance of the system. If Vi should be increased (or decreased) to some other level, V2, then P2 =
V22/Ri. If we substitute into the decibel equation to determine the resulting difference in decibels
between the power levels,

Fig.3

Advantages of the logarithmic relationship, it can be applied to cascade stages.

Gain versus Frequency

Fig.4 normalized gain versus frequency plot

In this figure, the gain at each frequency is divided by the mid-band value.
Obviously, the mid-band value is then 1 as indicated. At the half-power frequencies, the resulting
level is . A decibel plot can now be obtained by applying decibel equation in the
following manner:
( )

1
0
0
At mid-band frequencies, 20 log10 1 = 0, and at the cutoff frequencies, 20 log10 1/√ = -3 dB. Both
values are clearly indicated in the resulting decibel plot below. The smaller the fraction ratio, the
more negative the decibel level.

Fig.5. decibel plot of the normalized gain versus frequency plot

It should be understood that most amplifiers introduce a 180° phase shift between input and output
signals. This fact must now be expanded to indicate that this is the case only in the mid-band
region. At low frequencies, there is a phase shift such that Vo lags Vi by an increased angle. At
high frequencies, the phase shift will drop below 180°. Figure 6 is a standard phase plot for an RC-
coupled amplifier.

Fig.6. phase plot of RC- coupled amplifier system

Example1: Find the magnitude gain corresponding to a decibel gain of 100.

Example 2: The input power to a device is 10,000 W at a voltage of 1000 V. The output power is
500 W, while the output impedance is 20Ω.
(a) Find the power gain in decibels.
(b) Find the voltage gain in decibels.
(c) Explain why parts (a) and (b) agree or disagree.
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LOW-FREQUENCY ANALYSIS—BODE PLOT

In the low-frequency region of the single-stage BJT or FET amplifier, it is the R-C combinations
formed by the network capacitors CC, CE, and Cs and the network resistive parameters that
determine the cutoff frequencies. In fact, an R-C network similar to Fig. 7 can be established for
each capacitive element and the frequency at which the output voltage drops to 0.707 of its
maximum value determined. Once the cutoff frequencies due to each capacitor are determined, they
can be compared to establish which will determine the low-cutoff frequency for the system.

Fig.7. R-C combination that will define a low cutoff frequency

1
RC circuit at very high frequencies: X C   0Ω
2 πfC
The result is that Vo = Vi at high frequencies.

Fig.8. R-C circuit at very high frequencies

RC circuit at f = 0 Hz.X C  1  1
 Ω
2 πfC 2 π(0) C
Vo = 0 V.

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Fig.9. R-C circuit at f = 0Hz

At low frequency, the reactance of the capacitive becomes very large, so a significant portion of a
signal dropped across them. Then as the frequency approaches zero or at dc, the capacitive
reactance approach infinity or become an open circuit. As the frequency increases, the capacitive
reactance decreases and more of the input voltage appears across the output terminals. Between the
two extremes, the ratio Av = Vo/Vi will vary as shown in Fig.

Fig.10. Low-frequency response for the RC circuit

The output and input voltages are related by the voltage-divider rule in the following manner:

With the magnitude of Vo determined by

For the special case where XC = R,

At the frequency of which XC = R, the output will be 70.7% of the input. The frequency at which
this occurs is determined from:

In terms of logs,

While at Av = Vo/Vi = 1 or Vo = Vi (the maximum value),

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3
Gv = 20 log10 1 = 20(0) = 0 dB
If the gain equation is written as:

And using the frequency defined above,

In the magnitude and phase form,

Fig.11. Bode plot for the low-frequency region

The phase angle of Ѳ is determined from

Fig.12. phase response for the R-C circuit

Example 3: For the network given below:

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4
(a) Determine the break frequency.
(b) The magnitude of output voltage when Vi=10V.
(c) Sketch the frequency response curve.

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5
1
0
6
1
0
7
LOW-FREQUENCY RESPONSE —BJT AMPLIFIER
At low frequencies Coupling capacitors (Cs, CC) and Bypass capacitors (CE) will have capacitive
reactance (XC) that affect the circuit impedances.

Fig.13. loaded BJT amplifier with capacitors that affect the low frequency response

Coupling Capacitor - CS

Fig.14. determining the effect of CS on the low frequency response

1
f Ls 
2 (R s  R i )Cs 1
0
8
Cutoff frequency: (also known as corner frequency, or break frequency) is defined as a boundary in
a system‘s frequency response at which energy flowing through the system begins to be attenuated
(reflected or reduced) rather than passing through.

R i Vs
Voltage Vi: Vi 
Ri  Rs

Fig.14. localized ac equivalent for C

R i  R1 || R 2 || βre

Coupling Capacitor - CC

Fig.15. determining the effect of CC on the low-frequency response

1
Cutoff frequency: f LC 
2π (R o  R L )CC

Fig.16. localized ac equivalent for CC with Vi = 0V

R o  R C || ro

Bypass Capacitor - CE

Fig.17. determining the effect of CE on the low-frequency response

Cutoff frequency: f  1
LE
2πReC E
1
0
9
Fig.18. localized ac equivalent for CE
R
Re  RE || ( s  re)
β
R s  R s || R 1 || R 2
Example 4:
a. Determine the lower cutoff freq. for the network of Fig. 13 using the following parameters:
Cs = 10μF, CE = 20μF, Cc = 1μF
Rs = 1KΩ, R1= 40KΩ, R2 = 10KΩ,
RE = 2kΩ, Rc = 4kΩ, RL = 2.2KΩ,
β = 100, r0 = ∞Ω, Vcc = 20V
b. Sketch the frequency response using a Bode plot

Solution
(a) Determining re for dc conditions:

The result is:

Cs

Cc

1
1
0
CE

Bode plot of low frequency response

The Bode plot indicates that each capacitor may have a different cutoff frequency. It is the device
that has the highest of the low cutoff frequency (fL) that dominates the overall frequency response
of the amplifier (fLE). For the above case the lower cutoff frequency of the network is equal to f LE
=327Hz.

LOW-FREQUENCY RESPONSE — FET AMPLIFIER

Fig.19. capacitive elements that affect the low-frequency response of a JFET amplifier

CG

Fig.20. determining the effect of CG on the low frequency response

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1
1
CC

Fig.21. determining the effect of CC on the low frequency response

CS

Fig.22. determining the effect CS on the low frequency response

Example 5:

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HIGH-FREQUENCY RESPONSE — BJT AMPLIFIER

At the high-frequency end, there are two factors that will define the cut off frequencies: the
network capacitance (parasitic and introduced) and the frequency dependence of hfe.

At increasing frequencies, the reactance XC will decrease in magnitude, resulting in a shorting

effect across the output and a decrease in gain. The derivation leading to the corner frequency for

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this RC configuration follows along similar lines to that encountered for the low-frequency region.
The most significant difference is in the general form of Av appearing below:

Fig.23. an RC circuit similar to low frequency ckt

( ⁄ )
The various parasitic capacitances (Cbe, Cbc, Cce) of the transistor have been included with the
wiring capacitances (CWi, CWo) introduced during construction. The high-frequency equivalent
model for the network of Fig. 11.44 appears in Fig. 11.45.

Fig 24(a)upper- amplifier ckt with capacitance values in high frequency analysis
(b)lower-small signal model

Determining the Thévenin equivalent circuit for the input and output networks of Fig. 28(a) will
result in the configurations of Fig. 24(b) For the input network, the -3-dB frequency is defined by

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 Fig. 25 simplified input circuit

At very high frequencies, the effect of Ci is to reduce the total impedance of the parallel
combination of R1, R2, Ri, and Ci in Fig. 24(b). The result is a reduced level of voltage across Ci, a
reduction in Ib, and a gain for the system.

( )

For the output network

Fig. 26 simplified output circuit

At very high frequencies, the capacitive reactance of Co will decrease and consequently reduce the
total impedance of the output parallel branches of Fig. 11.45. If the parasitic capacitors were the
only elements to determine the high cutoff frequency, the lowest frequency would be the
determining factor. However, the decrease in hfe with frequency must also be considered as to
whether its break frequency is lower than fHi or fHo.

Example 6

Solution

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hfe also has frequency dependence, with fB as the cutoff frequency. fB is determined by a set of
parameters employed in a modified hybrid model frequently applied to best represent the transistor
in the high-frequency region.

HIGH-FREQUENCY RESPONSE — FET AMPLIFIER

There are interelectrode and wiring capacitances that will determine the high-frequency
characteristics of the amplifier.

Fig. 27(a)upper- FET amplifier ckt with high frequency capacitance (b)lower- small
signal model
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6
The cutoff frequencies defined by the input and output circuits can be obtained by first finding the
Thévenin equivalent circuits for each section as shown in Fig. 28 and [Link] actual high frequency
cutoff value is approximately the lowest of the two values.
For the input circuit

( )
Fig. 28 input ckt
For the output circuit,

( )

Fig. 29 output ckt

Example 7

Solution

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1
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 Chapter Six
Multistage Amplifiers

Two or more amplifiers can be connected in a cascaded arrangement with the output of one
amplifier driving the input of the next. Each amplifier in a cascaded arrangement is known as a
stage. The basic purpose of a multistage arrangement is to increase the overall voltage gain.

Multistage voltage gain

The overall voltage gain, Av of cascaded amplifiers as shown below, is the product of the
individual voltage gains.

′𝑣 = 𝑣1 𝑣2 𝑣3 … 𝑣 𝑠 𝑠 𝑠.

Input 𝐴𝑣𝑛 1 Output

Fig.1 cascaded amplifiers where each triangular symbol represents a separate amplifier

Voltage gain expressed in Decibels

Amplifier voltage gain is often expressed in decibels (dB) as follows:

𝑣( ) = 20 𝑣

This is particularly useful in multistage systems because the overall voltage gain in dB is the sum
of the individual voltage gains in dB.

′𝑣( )= 𝑣1 ( ) + 𝑣2 ( ) + ⋯+ 𝑣 ( )

Multistage Amplifier Analysis

For the purpose of illustration, we will use the two stage capacitive coupled amplifiers in fig 2. Notice
both stages are identical common emitter amplifier with the output of the first stage capacitive coupled to
the input of the second stage.

Capacitive coupling prevents the DC bias of one stage from affecting that of the other but allows the AC-
signal to pass without attenuation because XC =0Ω at the frequency of operation.

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9
 VCC
+10V
First stage Second stage

47kΩ R3 4.7kΩ R7 4.7kΩ

47kΩ R5 C5
Vout
C3 1µF

Vin 1µF
1µF

10kΩ 10kΩ R6 C4 100µF

R4 C2 100µF R8 1kΩ
1kΩ

βDC=βAC=150 for Q1 and Q2

Figure 2 A two stage Common emitter amplifier

DC voltages in the capacitive coupled multi stage amplifier

Since both stages in fig 2 are identical, the voltages for Q1 and Q2 are the same.

+VCC

VC R3
47kΩ Ω

1
VCC

VTh
10kΩ

Thevenin

RTh = R1//R2 = 8.245kΩ

VTh = [R2 /(R 1 + R2)] VCC

KVL (BE loop)

𝑇 + 𝑇 + 𝐸 + (1 + 𝛽) 4 =0

1.754 + 8.245 + 0.7 + 151 =0

= 6.62𝜇

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The base voltage is calculated as

= 𝑇 𝑇 = 1.7

The emitter voltage is:

𝐸 = 𝐸 𝐸 =1

The emitter current is

𝐸 1
= = =1
𝐸
4 1
The collector current is

𝐸 ≅ =1

The collector voltage is

= 3 = 5.3

Loading effect

In determining the voltage gain of the first stage, you must consider the loading effect of the
second stage. Because the coupling capacitor C3 effectively appears as a short at the signal
frequency, the total input resistance of the second stage presents an ac-load to the first stage.

Using the model for the transistor, assuming ≅ ∞,

Voltage gain of the second stage

Ib
VC > V

26 26
= = = 26Ω
𝐸 1

= (𝛽 )( 7) 7 4.7
2
= = = Ω = 180.77
1
(𝛽 ) 26

1
2
1
Voltage gain of the first stage

Input resistance from the second stage

= 5// 6//𝛽

Thus, the total ac-collector resistance of the first stage is:

1
= 3// = 3// 5// 6//𝛽 = 1.52 Ω

Ib b C
Vi V C1

βIb

1
( 𝛽 )� 1 � 1 1.52 Ω
𝑣 = = = = = 58.57
(𝛽 )( ) 26Ω
Overall voltage gain
′
= = (58.57)(180.77) = 10,588
𝑣 𝑣1 𝑣2

The overall voltage gain can be expressed in dB.

′
𝑣( ) = 20 log 10,588 = 4.025

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Direct coupled Multistage Amplifiers:

A basic two-stage, direct coupled amplifier is shown in fig.3. Notice that there are no coupling or bypass
capacitors in this circuit.

The dc collector voltage of the first stage provides the base bias voltage for the second stage. Because of
direct coupling, this type of amplifier has a better low frequency response than the capacitive coupled
type in which the reactance of coupling and bypass capacitors at very low frequency may become
excessive.

The increased reactance of capacitors at lower frequencies produces gain reduction in capacitive coupled
amplifiers.

VCC

Vo

V1n

Fig.3.A basic two-stage direct coupled amplifier.

The advantage of direct coupled amplifiers is that small changes in the dc bias voltages from temperature
effects or power supply variation are amplified by the succeeding stages, which can result in a significant
drift in the dc levels throughout the circuit.

Example: - for the direct coupled amplifier shown, determine all dc voltages for both stages and over all
ac voltage gain.

VCC =12V ac   D C  125

V1n

C2
10µf

1
2
3
DC analysis

VCC =12V

VCC =12V

RTH
1

VTH

2
=� �(12) = 2.164 = | = 18.032
𝑇𝐻 𝑇𝐻 1 2
1 + 2

KVL around BE loop of Q1,

𝑇𝐻+ 1 𝑇𝐻 + 𝐸 + 𝐸1 4 =0

𝑇𝐻 𝐸 12 0.7 = 2.465𝜇
1 = =
𝑇𝐻 + (1 + 𝛽) 4 18.032 + ∗ 4.7

𝐸1 = (1 + 𝛽) 1 = 0.31 1 = (𝛽) 1 = 0.308

𝐸1 = 4 𝐸1 = 1.46

1 = 𝐸1 + 𝐸 = 2.16

KVL around CE loop of Q1,

1 = 3 1 = 5.224

KVL around BE loop of Q2,

𝐸2 = 2 𝐸 = 4.46 But 2 = 1 = 5.224

𝐸1
1 = = 3.54𝜇
(1 + 𝛽)

2 = (𝛽) 2 = 0.442

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4
KVL around CE loop of Q2,

2 = 5 2 = 7.57

Voltage gain of the 2nd stage.

Vc1
Ib2
Vo

Ri re2

VC1 0.026V
R   re 2 , re2   0.056K
Ib 2 IE 2
Ri  125  0.056K  7K
V
A  o (  I b 2 )(RS )  RS  179
 
b 2 )(re 2 )
V2
C1 re2

Voltage gain of the 1nd stage

Vi Ib1 Vc1

R1 // R2 re1

0.026V
re1   0.08K
I E1

AV 1 
VC1 (  I b1 )(R3 // Ri )   (R3 // Ri )
  

Vi (I b1 )(re1 ) re1
AV 1  66

Overall voltage gain

A'V  AV 1 AV 2  66 179
A'V  11,814

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MULTISTAGE FREQUENCY EFFECTS

For a second transistor stage connected directly to the output of a first stage, there will be a significant
change in the overall frequency response. For each additional stage the upper cutoff frequency will be
determined primarily by that stage having the lowest- cutoff frequency. The low-frequency cutoff is
primarily determined by that stag having the highest low-frequency cutoff frequency. Obviously,
therefore, one poorly designed stage can offset an otherwise well-designed cascaded system.

The effect of increasing the number of stages can be clearly demonstrated by considering the situations
indicated in Figure below. In each case, the upper and lower cutoff frequencies of each of the cascaded
stages are identical. For a single stage, the cutoff frequencies are f1 and f2 as indicated. For two identical
stages in cascade, the drop-off rate in the high- and low-frequency regions has increased to 40dB/decade,
60dB/decade for three stages and so forth.

For the low-frequency region,

𝑣( 𝑣 )= 1( ) 2( ) … ( )

But, for identical stages, 1( ) = 2( ) =⋯= ( )

Hence, [ 𝑣( 𝑣 ) [ 1( )] 1
𝑣( 𝑣 )= 1( )
] or = =
𝑣( ) 𝑣( ) ( / 1)

�
𝑣( 𝑣 )
At the cut-off frequency, �= 1 = 1/√2
𝑣( ) ��1+[( ′/ 12 )]

′ 1
= =
( 𝑣 ) 1
√ 1/ 1
Similarly, the higher cut-off frequency
is calculated as ( 𝑣 ) =�21/
1 2

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 Chapter Seven
Power Amplifiers
Introduction
So far, we have been discussion on small signal voltage amplifiers where the output power and
input power are very small so that special emphasise was given to the voltage and current gain,
and the efficiency of the amplifier and the power handling capacity of the amplifying device
(transistor) were not of much concern. However, the situation will be very different at the last
stage of multi-stage amplifiers for which the signal will be very strong in the range of few tens of
watts there by insisting such amplifiers that are capable of handling larger power called power
amplifiers. Thus the main factors that has got special place in power amplifiers are efficiency,
linearity and amplification.
Classes of Power Amplifies
Depending on the biasing condition and the shape of the output signal for a sinusoidal input,
power amplifiers are classified as class-A, class-B, class-AB, and class-C amplifiers.
Class-A
In class-A amplifiers the output device conducts for the full cycle of 360o, and it is biased in the
active region.
Class-B
However, such types of power amplifiers are biased at the cut-off region so that they could
conduct only for half cycle (180o).
Class-AB
In these types of power amplifiers conduction is possible for greater than half cycle, or for
0o<θ<360o.
Class-C
These are design to conduct for less than half cycle or θ<180o.
Class-A Power Amplifies
Series fed class A amplifiers
The output is taken directly as shown in the figure 7.1.
ng
wi
ts

VCC
pu

IC
In

VCC /RC
RB RC

V0 ICQ Q-point ( VCC/ 2RC , VCC/ 2 )

C1
Output current swing
Vi
VCE
Output voltage swing

VCQ VCC

1
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 Figure 7.1
The DC load line is expressed as: 𝐸 , and
The ac current and voltage relationship can be determine from the small signal model, and is
given by:
𝑣
Efficiency:
The efficiency of power amplifier is defined as the ratio of the output ac power to input dc
power. Mathematically,
( )

( )
The DC input power is,
( )
The AC output power is defined as,
( )
As it was true that the Q-point is chosen at the center of the load line, the maximum possible
efficiency of class-A amplifier will be obtained when and .
Hence,
( )

Transformer coupled Class-A amplifier

Obviously, 25 percent efficiency does mean about three-fourth of the input dc power is
dissipated inside the transistor which indicates inefficiency as well as requirement of greater
power handling capacity by the device. Such type of inefficiency can be partially solved by using
a transformer as depicted by figure 7.2.
VCC

N1 / N2

RL V0
RB

IC
DC load line
Vi 2ICQ

Q-point
ICQ AC load line

VCE
VCQ=VCC 2VCC

Figure 7.2
The AC small signal model,

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 ic
Vo(ac)

1
+
Vi R’L
Vce
-
RB

Figure 7.3
After taking KVL around loop 1, the ac current and voltage are related by

Substituting and 𝐸 𝐸 into the above equation, the AC load line is

given by
( 𝐸 𝑣 𝐸 )
From the DC analysis we know that 𝐸
Therefore, the AC load line equation is expressed as
( 𝐸 𝑣 )

Using impedance reflection rule, the effective resistance value of R2 as seen from the primary
side of the transformer is given as,

[ ]

For class-A operation the Q-point is selected so that

Comparing this with equation (1), we have ′
Thus,

( )

At the maximum voltage swing, the output ac power is given by

( )
( )

Therefore, the maximum possible efficiency is,

( )
( )
Class-B Power Amplifiers
The principle of operation of class B power amplifiers can be easy demonstrated using the circuit
of figure 7.4a.

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 N1 / N2

RL Vo
Vi
VCC

Figure 7.4a
If the BE diode is considered as an ideal rectifier, the power transistor will conduct for the
positive cycle of the input producing an output of the form similar to half-wave rectified signal.
A more explicit understanding could be developed using the load line in figure7.4b.
IC
DC load line
ICmax
Io

AC load line

VCC VCE
π 2π
Q-point

Vm
π 2π

Vo

Figure 7.4b
Efficiency
In class-B operation the input DC power is the product of the DC value of the output current to
that of the DC supply voltage. That is,
( ) ( )
And the AC output power is determined as
( ) ( 𝑠) ( 𝑠) ( )( )
For maximum output swing
Hence, the maximum theoretical efficiency of class-B power amplifier is determined as

Transistor coupled Push-Pull Power Amplifier

This type of amplifier employs two Class B amplifiers that are made to operate in the positive
and negative half cycles of the input signal so that continues current is deliver to the load. An
example of this arrangement is shown in the figure 7.5.

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 Figure 7.5
During the first half-cycle of operation, transistor Q1 is driven into conduction whereas transistor
Q2 is driven off. The current I1 through the transformer results in the first half-cycle of signal to
the load. During the second half-cycle of the input signal, Q2 conducts whereas Q1 stays off, the
current I2 through the transformer resulting in the second half-cycle to the load. The overall
signal developed across the load then varies over the full cycle of signal operation.
The efficiency of push-pull amplifier is the same as that of normal class B amplifier. i.e.,
η=78.5%.
Complimentary push-pull Class-B Amplifier
This is constructed from npn and pnp complimentary transistors.
VCC

Q1

RL
Q2

-VCC

Figure 7.6
Compared to class A, class B amplifier is far more efficient. However, the great problem of
push-pull amplifier is that, in practical situation, each transistor conduct only for just less than
180o, which leaves a small interval of signal discontinuity in between the takeover operation as
shown in figure 7.7. This type of distortion is called cross-over distortion.

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 Cross-over distortion

Figure 7.7
To prevent such type of distortion the B-E junction diodes of each transistor are forward biased
so that they will operate for above 180o.
Class C Amplifier
A class C amplifier, as shown in Fig. 7.8, is biased to operate for less than 180° of the input
signal cycle. The tuned circuit (will be discussed later) in the output, however, will provide a full
cycle of output signal for the fundamental or resonant frequency of the tuned circuit (L and C
tank circuit) of the output. This type of operation is therefore limited to use at one fixed
frequency, as occurs in a communications circuit.
VCC

L2 C1

π 2π
Vo
Vm

Vi Q1 Input Output of LC Tune

Output of the
Signal circuit
L1 Amplifier

-VBE

Figure 7.8

Distortion and Thermal Effects

For small signal variation, the response of the amplifier can be approximated as linear. But for
large signal distortion can occur because the device characteristic is not linear, in which case
nonlinear or amplitude distortion occurs. This can occur with all classes of amplifier operation.
Distortion can also occur because the circuit elements and devices respond to the input signal

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2
differently at various frequencies, this being frequency distortion. Distortion is mainly due to
induced harmonic components other than the fundamental frequency signal in the output.
When the amplifier is operated for long time its temperature increases causing the variation of
the transistor current gain. Thus a small change in the value of α will bring a large change in the
vaue of β called α-crowding.

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