Verilog: Hardware Description Language

Arijit Mondal
Dept. of CSE

IIT Patna 1
Digital CAD flow
Application/
B1 B2 System Level
Hardware−Software
B3 B4 codesign
Architecture Physical
level Level
High level synthesis
R1 R2 R3
Controller

RTL Fabrication
Compute unit Level
Logic synthesis

Logic level Packaging

Q D

Q’

Circuit level

IIT Patna 2
Introduction

• Verilog was designed primarily for digital hardware designers developing FPGAs and
ASICs.
• It is different from C/C++/Java.
• Uses discrete event simulation techniques
• This is one of the most commonly used languages for describing hardware. Other
popular language is VHDL
• Supports both structural as well as behavioral description

IIT Patna 3
Structural vs Behavioral
• Structural • Behavioral
∗ Connectivities of gates ∗ Behavior of module
∗ out = SA + S̄B
A G1
I2
S

G2 out
G4

I1

I3
B G3

IIT Patna 4
Concept of module

• Basic unit is module that describes a hardware component

∗ Modules cannot contain definitions of other modules.
∗ A module can, however, be instantiated within another module.
∗ Allows the creation of a hierarchy in a Verilog description.

IIT Patna 5
Syntax of module definition

module module name(list of ports);

input /output declaration;
local net declaration;
statements;
endmodule

IIT Patna 6
MUX : Structural form

module MUX(out, A, B, S);

output out;
input A, B, S; A G1
wire I1, I2, I3; S
I2

G2 out
and G1(I2, A, S); G4
and G3(I3, I1, B); I1
not G2(I1, S); I3
or G4(out, I2, I3); B G3

endmodule

IIT Patna 7
Primitive gates

• and, or, nand, not, nor, xor, xnor, buf

• Syntax: <gate name> <inst name> (<out>,<in1>,<in2>);
• Syntax: <gate name> <inst name> (<out>,<in1>);

IIT Patna 8
Hierarchical design

module mux4x1(y,i1,i2,i3,i4,s0,s1);
input i1,i2,i3,i4,s0,s1; s0
s1
output y; i1
M01
i2 y1
MUX MUX 01(y01,i1,i2,s0); M03
y
MUX MUX 02(y02,i3,i4,s0); i3 y2
MUX MUX 03(y,y01,y02,s1); M02
i4
s0
endmodule

IIT Patna 9
Specifying connectivity

• There are two alternate ways of specifying connectivity:

∗ Positional association
— The connections are listed in the same order
add A1 (c out, sum, a, b, c in);

∗ Explicit association
— May be listed in any order
add A1 (.in1(a), .in2(b), .cin(c in), .sum(sum), .cout(c out));

IIT Patna 10
Port connectivity
module subMod(out1,out2,in1,in2);
...
endmodule

module Mod;

//positional association
subMod M1(O1,O2,I1,I2);

//explicit association
subMod M2(.out1(O1),.out2(O2),.in1(I1),.in2(I2));

endmodule

IIT Patna 11
Testbench

• A procedural block which executes only once

• Used for simulation
• Generates clock, reset, and the required test vectors

Module
under
test

Stimulus Compare
Logic

Test Bench

IIT Patna 12
How to write testbench

• Create a dummy module

∗ Declare inputs to the module-under-test (MUT) as ’reg’ and the outputs as ’wire’
∗ Instantiate the MUT
• Initialization
∗ Assign some known values to the MUT inputs
• Generate the clock
• Use simulator directives to print the results

IIT Patna 13
Testbench
module top;
reg a,b,c,d;
reg s1, s2;
wire y;
mux4x1 mux inst(y,a,b,c,d,s1,s2);

initial begin
a=b=c=d=s1=s2=1’b0;
$monitor("y=%b a=%b b=%b c=%b d=%b s0=%b s1=%b"
time=%2d,y,a,b,c,d,s0,s1,$time);
#1 a=1’b1; #1 s1=1’b1; #1 a=1’b0;
#1 c=1’b1; #1 s0=1’b1;
#10 $finish;
end
endmodule
IIT Patna 14
Logic values

• 0,1 – Binary value

• X – Unknown value
• Z – High impedance state
− All unconnected nets are set to ’z’
− All registers variables are set to ’x’

IIT Patna 15
Functional table for primitive gates

AND XOR
0 1 x z 0 1 x z
0 0 0 0 0 0 0 1 x x
1 0 1 x x 1 1 0 x x
x 0 x x x x x x x x
z 0 x x x z x x x x

IIT Patna 16
Verilog operator

• Arithmetic operator: *,/,+,-

• Logical operator: !, &&, ||
• Relational operator: >, <, >=, <=, ==, ! =
• Bitwise operator: &,|, etc.
• Reduction operator: Operate on all the bits within a word (&, ˜&, etc.)
• Shift operator: <<, >>
• Concatenation operator: {}
• Replication operator: {{}}
• Conditional: expr? exp1 : exp2;

IIT Patna 17
Data types
• Net: Represents the continuous updating of outputs with respect to their changing
inputs.
∗ wire, supply0, supply1
∗ wire wire01,wire02;
• reg: Has to be assigned values explicitly. Value is held until a new assignment is
made
∗ reg out1, out2;
• Integer: integer intparam;
• Real: real realparam;
• Vector: reg [3:0] output;
• Arrays: reg data [7:0];
• 1K memory of 16 bit elements –
reg [15:0] mem16 1024 [0:1023]

IIT Patna 18
Data type: wire
• wire elements are used to connect input and output ports of a module instantiation
together with some other element in your design.
• wire elements are used as inputs and outputs within an actual module declaration.
• wire elements must be driven by something, and cannot store a value without being
driven.
• wire elements cannot be used as the left-hand side of an = or <= sign in an always@
block.
• wire elements are the only legal type on the left-hand side of an assign statement.
• wire elements are a stateless way of connecting two pieces in a Verilog-based design.
• wire elements can only be used to model combinational logic.
• wire, wor, wand, tri, supply0, supply1

IIT Patna 19
Data type: reg
• It can be connected to the input port of a module instantiation.
• It cannot be connected to the output port of a module instantiation.
• It can be used as outputs within an actual module declaration.
• It cannot be used as inputs within an actual module declaration.
• It is the only legal type on the left-hand side of an always@ block = or <= sign.
• It is the only legal type on the left-hand side of an initial block = sign (used in Test
Benches).
• It cannot be used on the left-hand side of an assign statement.
• It can be used to create registers when used in conjunction with always@(posedge
Clock) blocks.
• It can, therefore, be used to create both combinational and sequential logic.

IIT Patna 20
Data type: reg
• Different ‘register’ types supported for synthesis:
∗ reg, integer
• The ‘reg’ declaration explicitly specifies the size.
∗ reg x, y; // single-bit register variables
∗ reg [15:0] bus; // 16-bit bus, bus[15] MSB
• For ‘integer’, it takes the default size, usually 32-bits.
∗ Synthesizer tries to determine the size.
• Arithmetic expressions
∗ An ‘integer’ is treated as a 2’s complement signed integer.
∗ A ‘reg’ is treated as an unsigned quantity.
• General rule of thumb
∗ reg used to model actual hardware registers such as counters, accumulator, etc.
∗ integer used for situations like loop counting.

IIT Patna 21
Port connectivity

net

net inout

input output net

net/reg net net/reg

IIT Patna 22
Specifying const values

• Values can be specified in sized or unsized form

∗ Syntax for sized form: <size>’<base><number>
• Examples
∗ 4’b0011 //4-bit binary number
∗ 12’hA2D //hexadecimal number
∗ 12’hCx5 //1100 xxxx 0101 in binary
∗ 25 //signed number 32 bits
∗ 1’b0 //Logic 0
∗ 1’b1 //Logic 1

IIT Patna 23
Parameters

• A parameter is a constant with name

• No size is allowed to be specified for a parameter
• The size gets decided from the constant itself. 32 bits if nothing is specified.
• Examples
∗ parameter HI = 25, LO = 5;
∗ parameter up = 1’b0;

IIT Patna 24
Note

• For all primitive gates:

∗ The output port must be connected to a net.
∗ The input port must be connected to a net or reg.
∗ Can have only single output but any number of inputs

• Boolean true/false
∗ true is equivalent to 1’b1;
∗ false is equivalent to 1’b0;

IIT Patna 25
Simple AND gate

module simple and(out, A, B);

input A, B;
output out;
assign out = A & B;
endmodule

IIT Patna 26
Two level circuits

module two level (a, b, c, d, f);

input a, b, c, d;
output f;
wire t1, t2;
assign t1 = a & b;
assign t2 = ~(c | d);
assign f = t1 ∧ t2;
endmodule

IIT Patna 27
Example: wire

module using wire (A, B, C, D, f);

input A, B, C, D;
output f;
// net f declared as ‘wire’
wire f;
assign f = A & B;
assign f = C | D;
endmodule

IIT Patna 28
Example: wire

module using wire (A, B, C, D, f);

input A, B, C, D;
output f;
// net f declared as ‘wand’
wand f;
assign f = A & B;
assign f = C | D;
endmodule

IIT Patna 29
MUX : Behavioral form

module MUX(out, A, B, SEL);

output out;
reg out;
input A, B, SEL; A G1
I2
S

always @(SEL, A, B) G2 out

G4
if(S)
out=A; I1

else B G3
I3

out=B;

endmodule

IIT Patna 30
MUX : Continuous assignment

module MUX(out, A, B, SEL); A G1

output out; S
I2

input A, B, SEL;
G2 out
G4
assign out = SEL ? A : B; I1

I3
endmodule B G3

IIT Patna 31
8-bit adder

module adder(sum,cout,in1,in2,cin);
input [7:0] in1, in2;
input cin;
output [7:0] sum;
output cout;
assign #20 {cout,sum} = in1 + in2 + cin;
endmodule

IIT Patna 32
Description styles

• Data flow
∗ Continuous assignment

• Behavioral
∗ Procedural assignment
— Blocking
— Non-blocking

IIT Patna 33
Description styles: Continuous assignment

• Identified by the word ’assign’

• assign a = b & c;
• The ’net’ is being assigned on the LHS, i.e. LHS must be of ’net’ type
• Expression is on the RHS. RHS may contain both ’reg’ or ’net’.
• Assignment is continuously active
• Exclusively used to model combinational logic
• A module can contain any number of continuous assignment statements

IIT Patna 34
Behavioral style: Procedural assignment

• A region of code containing sequential statements

• The statements execute in the order they are written
• Two types of procedural blocks
∗ ’always’ – Continuous loop that never terminate
∗ ’initial’ – Executed once at the beginning of simulation

IIT Patna 35
initial block

• An initial block consists of a statement or a group of statements enclosed in begin

... end which will be executed only once at simulation time 0.
• Multiple initial blocks in an design are executed in parallel
• Normally used for initialization, monitoring, generating wave forms (eg, clock pulses)
and processes which are executed once in a simulation.

IIT Patna 36
Procedural assignment: always

• A module can contain any number of ’always’ block

• Syntax for ’always’ block
always @(event expression)
begin
statement
end
• @(event expression) is required for both combinational and sequential logic

IIT Patna 37
only ’reg’ can be assigned within ’always’

• ’always’ block executes only when the event expression triggers

• At other time block is doing nothing
• An object being assigned to must therefore remember the last value assigned
• any kind of variable may appear in the event expression

IIT Patna 38
Sequential statements
• begin
sequential statements
end

• if(expression)
sequential statement
[else
sequential statement]

• case(expression)
expr: sequential statement
default: sequential statement
endcase

IIT Patna 39
Sequential statements (contd)

• forever
sequential statement

• repeat(expression)
sequential statement

• while(expression)
sequential statement

• for(expr1;expr2;expr3)
sequential statement

IIT Patna 40
Blocking vs Non-blocking

• Sequential statements within procedural blocks can use two types of assignments
∗ Blocking assignment : Use the ’=’ operator
∗ Nonblocking assignment : Use the ’<=’ operator

IIT Patna 41
Blocking

• Most commonly used type

• The target of assignment gets updated before the next sequential statement in the
procedural block
• It blocks the execution of the statements following it
• Recommended style for modeling combinational logic

IIT Patna 42
Nonblocking

• The assignment to the target gets scheduled for the end of the simulation cycle
∗ Normally occurs at the end of the sequential block
∗ Statement subsequent to the instruction under consideration are not blocked by the
assignment
• Recommended style for modeling sequential logic
∗ Can be used to assign several ’reg’ type variable synchronously, under the control of
a common clock.
• A variable cannot appear as the target of both blocking and a nonblocking assignment

IIT Patna 43
Example

reg aout, bout, cout;

wire ain, bin, cin;
always @(negedge clk)

begin A B C
+1 +1
aout<=ain;
bout<=aout+1;
cout<=bout+1;
end

IIT Patna 44
Example
reg aout, bout, cout;
wire ain, bin, cin;

always @(negedge clk)

begin
aout<=ain; A B C
bout<=bin; +1 +1

cout<=cin;
end

assign bin=aout+1;
assign cin=bout+1;

IIT Patna 45
Example
reg aout, bout, cout;
wire ain, bin, cin;

always @(negedge clk)

aout<=ain;

assign bin=aout+1;
A B C
+1 +1
always @(negedge clk)
bout<=bin;

assign cin=bout+1;

always @(negedge clk)

cout<=cin;

IIT Patna 46
Example

reg aout, bout, cout;

wire ain, bin, cin;

always @(negedge clk)

begin
aout=ain; A
+1
B
+1
C
bout=bin;
cout=cin;
end

assign bin=aout+1;
assign cin=bout+1;

IIT Patna 47
Example

reg aout, bout, cout;

wire ain, bin, cin;

always @(negedge clk)

begin
aout=ain; A
+1
B
+1
C
bout=bin;
cout=cin; NOT CORRECT
end

assign bin=aout+1;
assign cin=bout+1;

IIT Patna 47
Counter design
module counter(out,en,reset,clk);
output [3:0] out;
reg [3:0] out;
input en,reset,clk;
wire en,reset,clk;

always @(posedge clk)

begin :COUNTER
if(reset == 1’b1) out = 4’b0000;
else if(en == 1’b1) out = out + 1;
end // end of COUNTER

endmodule

IIT Patna 48
Clock generator
module cklGen(out);
output out;
reg out;

initial begin
out = 1’b0;
end

always
begin :CLK
out = #1 ~out;
end // end of CLK

endmodule

IIT Patna 49
Testbench

module top;
wire clk;
clkGen M1(clk);
counter M2(out,reset,en,clk);

initial begin
$monitor("out=%d time=%d\n",out,$time);
reset=1’b0; en=1’b0;
#5 en=1’b1;
#100 $finish;
end
endmodule

IIT Patna 50
Simulator directives

• $display – Similar to printf

• $monitor – Similar to $display, but prints whenever the value of some variables in
the given list changes
• $finish – Stop simulation
• $dumpfile, $dumpvar, $readmemb, $readmemh

IIT Patna 51
Synchronous up-down counter
module counter (mode, clr, ld, d in, clk, count);
input mode, clr, ld, clk; input [0:7] d in;
output [0:7] count;
reg [0:7] count;
always @ (posedge clk)
if(ld)
count <= d in;
else if(clr)
count <= 0;
else if(mode)
count <= count + 1;
else
count <= count − 1;
endmodule

IIT Patna 52
Multiple clocks
module multiple clk (clk1, clk2, a, b, c, f1, f2);
input clk1, clk2, a, b, c;
output f1, f2;
reg f1, f2;

always @ (posedge clk1)

f1 <= a & b;

always @ (negedge clk2)

f2 <= b ^ c;

endmodule

IIT Patna 53
Multiple edges of the clk
module multi phase clk (a, b, f, clk);
input a, b, clk;
output f;
reg f, t;

always @ (posedge clk)

f <= t & b;

always @ (negedge clk)

t <= a | b;

endmodule

IIT Patna 54
Ring counter
module ring counter (clk, init, count);
input clk, init;
output [7:0] count;
reg [7:0] count;
always @ (posedge clk)
begin
if(init)
count = 8’b10000000;
else begin
count = count << 1;
count[0] = count[7];
end
end
endmodule

IIT Patna 55
Ring counter (contd.)
module ring counter (clk, init, count);
input clk, init;
output [7:0] count;
reg [7:0] count;
always @ (posedge clk)
begin
if(init)
count = 8’b10000000;
else begin
count <= count << 1;
count[0] <= count[7];
end
end
endmodule

IIT Patna 56
Ring counter (contd.)
module ring counter (clk, init, count);
input clk, init;
output [7:0] count;
reg [7:0] count;
always @ (posedge clk)
begin
if(init)
count = 8’b10000000;
else begin
count = {count[6:0],count[7]};
end
end
endmodule

IIT Patna 57
Finite State Machine

NS OP
NS FF PS
Logic Logic

Moore m/c

NS OP
NS FF PS
Logic Logic

Mealy m/c

IIT Patna 58
FSM: Traffic Light Controller

• Simplifying assumptions made

• Three lights only (RED, GREEN, YELLOW)
• The lights glow cyclically at a fixed rate
∗ Say, 10 seconds each
∗ The circuit will be driven by a clock of appropriate frequency

IIT Patna 59
Traffic light controller
module traffic light (clk, light);
input clk;
output [0:2] light;
reg [0:2] light;
parameter S0=0, S1=1, S2=2;
parameter RED=3’b100, GREEN=3’b010,
YELLOW=3’b001;
reg [0:1] state;

IIT Patna 60
Traffic light controller
module traffic light (clk, light);
input clk;
output [0:2] light;
reg [0:2] light;
parameter S0=0, S1=1, S2=2;
parameter RED=3’b100, GREEN=3’b010,
YELLOW=3’b001;
reg [0:1] state;
always @ (posedge clk)
case(state)
S0: begin //RED
light <= YELLOW;
state <= S1;
end

IIT Patna 60
Traffic light controller
module traffic light (clk, light); S1: begin //YELLOW
input clk; light <= GREEN;
output [0:2] light; state <= S2;
reg [0:2] light; end
parameter S0=0, S1=1, S2=2;
parameter RED=3’b100, GREEN=3’b010,
YELLOW=3’b001;
reg [0:1] state;
always @ (posedge clk)
case(state)
S0: begin //RED
light <= YELLOW;
state <= S1;
end

IIT Patna 60
Traffic light controller
module traffic light (clk, light); S1: begin //YELLOW
input clk; light <= GREEN;
output [0:2] light; state <= S2;
reg [0:2] light; end
parameter S0=0, S1=1, S2=2; S2: begin //GREEN
parameter RED=3’b100, GREEN=3’b010, light <= RED;
YELLOW=3’b001; state <= S0;
reg [0:1] state; end
always @ (posedge clk)
case(state)
S0: begin //RED
light <= YELLOW;
state <= S1;
end

IIT Patna 60
Traffic light controller
module traffic light (clk, light); S1: begin //YELLOW
input clk; light <= GREEN;
output [0:2] light; state <= S2;
reg [0:2] light; end
parameter S0=0, S1=1, S2=2; S2: begin //GREEN
parameter RED=3’b100, GREEN=3’b010, light <= RED;
YELLOW=3’b001; state <= S0;
reg [0:1] state; end
always @ (posedge clk) default: begin
case(state) light <= RED;
S0: begin //RED state <= S0;
light <= YELLOW; end
state <= S1; endcase
end endmodule

IIT Patna 60
Traffic light controller (contd.)
module traffic light nonlatched op
(clk, light);
input clk; output [0:2] light;
reg [0:2] light;
parameter S0=0, S1=1, S2=2;
parameter RED=3’b100,
GREEN=3’b010, YELLOW=3’b001;
reg [0:1] state;

IIT Patna 61
Traffic light controller (contd.)
module traffic light nonlatched op
(clk, light);
input clk; output [0:2] light;
reg [0:2] light;
parameter S0=0, S1=1, S2=2;
parameter RED=3’b100,
GREEN=3’b010, YELLOW=3’b001;
reg [0:1] state;
always @ (posedge clk)
case(state)
S0: state <= S1;
S1: state <= S2;
S2: state <= S0;
default: state <= S0;
endcase

IIT Patna 61
Traffic light controller (contd.)
module traffic light nonlatched op
(clk, light);
input clk; output [0:2] light;
reg [0:2] light;
always @ (state)
parameter S0=0, S1=1, S2=2;
case(state)
parameter RED=3’b100,
S0: light = RED;
GREEN=3’b010, YELLOW=3’b001; S1: light = YELLOW;
reg [0:1] state; S2: light = GREEN;
always @ (posedge clk) default: light = RED;
case(state) endcase
S0: state <= S1; endmodule
S1: state <= S2;
S2: state <= S0;
default: state <= S0;
endcase

IIT Patna 61
Verilog: function & task
• These allow the designers to abstract Verilog code that is used at many places in the
design
• function
∗ Can enable other functions but no task
∗ Executes in 0 simulation time
∗ Must have at least one input argument
∗ Returns a single value
• task
∗ Can enable other functions and tasks
∗ May execute in non-zero simulation time
∗ May have zero or more argument
∗ Does not return value but can pass value through inout or output

IIT Patna 62
Example: Task
module op;
...
always @(...) begin
...
bitwiseOpr(AB AND,A,B)
end

task bitwiseOpr
input A,B;
output AB AND
begin
AB AND = A & B;
end
endtask
endmodule
IIT Patna 63
Example: Function
module op;
reg X;
always @(...) begin
...
X=bitwiseOpr(A,B)
end

function bitwiseOpr;
input A,B;
begin
bitwiseOpr = A & B;
end
endfunction
...
endmodule
IIT Patna 64
Verilog PLI

• The Verilog PLI is a simulation interface

∗ Reads/modifies simulation data structures
∗ Does not read Verilog source code
∗ Does not work with synthesis compilers or other tools
• The PLI is a protecting layer between user programs and simulation data structure
∗ Indirect access through PLI libraries
— C program cannot directly read or modify the simulation data
— Protects the simulator from bad C programs
— Protects C programs from bad Verilog code

IIT Patna 65
Verilog PLI

C/C++ code Verilog code

void hello() $hello

shared object or
static linked
verilog simulator

IIT Patna 66
Example: GCD in C
int GCD(int A, int B){
int done=0; int tmpA = A, tmpB = B;
while(done != 1){
if(A < B){
int tmp = B; B = A; A = tmp;
}else if(B != 0){
A = A - B;
}else{
done = 1;
}
}
return A;
}

IIT Patna 67
Example: GCD in verilog
module GCD#(parameter W=8) (out, A, B);
input [w-1:0] A, B; output [w-1:0] out;
reg [w-1:0] tmpA, tmpB, out, swap; integer done;
always @(*) begin
done=0; tmpA = A; tmpB = B;
while(!done) begin
if(tmpA<tmpB)
swap = tmpA; tmpA = tmpB; tmpB = swap;
else if(tmpB!=0)
tmpA = tmpA - tmpB;
else
done = 1;
end
out = tmpA
end
endmodule
IIT Patna 68
GCD: Top level view

inpRDY resRDY
resTaken
A results
B
clk reset

IIT Patna 69
GCD: Datapath & Control module

Control in/out Control Control in/out

Data in Datapaths Data out

IIT Patna 70
GCD: Datapath & Control module

Asel Aen Bsel Ben B=0 A<B

Zero lt

SUB

IIT Patna 71
GCD: Datapath module
module GCDDP#(parameter W=8) (.....){
input [w-1:0] A, B; output [w-1:0] results;
input Aen, Ben, Asel, Bsel;
output bZero, A lt B;
input clk;

AMUX();
AFF();
BMUX();
BFF();
B EQ 0();
LessThan();
Subtractor();

endmodule
IIT Patna 72
GCD: FSM

Swapping and Wait for result

Wait for inputs subtracting to be grabbed
Reset
Wait Calc Done
B=0
inpRDY

resTaken

IIT Patna 73
GCD: Control module
module GCDControl (.....)
input inpRDY, resTaken; output resRDY;
output Aen, Ben, Asel, Bsel;
input bZero, A lt B;
input clk, reset;

reg nextState; wire state

DFF(nextState -> state);
always @(*)
WAIT: set various signal lines
CALC: set various signal lines
DONE: set various signal lines
endcase

IIT Patna 74
GCD: Control module

always @(*)
case(state)
WAIT: if(inpRDY) nextState = CALC
CALC: if(bZero) nextState = DONE
DONE: .....
default: nextState = state
endcase
endmodule

IIT Patna 75
FIR Filter

• Let us consider car engine temperature (X ) in every second: 180, 181, 180, 240,
180, 181
• 240 is spurious value, needs to be ignored
• Y (t) = c0 × x(t) + c1 × x(t − 1) + c2 × x(t − 2)

IIT Patna 76
FIR Filter

X Y
Digital Filter
clk

IIT Patna 77
FIR Filter

3 Tap Filter
x(t) x(t−1) x(t−2)
X Y
xt0 xt1 xt2

clk

IIT Patna 78
FIR Filter
3 Tap Filter
c0 c1 c2

x(t) x(t−1) x(t−2)

X xt0 xt1 xt2
clk

* * *
Y

IIT Patna 79
FIR Filter
3 Tap Filter
c0 c1 c2

x(t) x(t−1) x(t−2)

X xt0 xt1 xt2
clk

✱ ✱ ✱

+ +
Y

IIT Patna 80
FIR Filter
CL
3 Tap Filter
e
s0 2
1
2x4
s1 0

c0 c1 c2
x(t) x(t−1) x(t−2)
X xt0 xt1 xt2
clk

✱ ✱ ✱

+ +
Y

IIT Patna 81
 Thank you!

IIT Patna 82