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Logic Synthesis and Timing Analysis Guide

The document outlines key concepts and questions related to logic synthesis, including assumptions, timing analysis, hold violations, and the differences between targeting FPGAs and ASICs. It also discusses the importance of specifying constraints in SDC files and the impact of various changes on timing paths and slack values. Additionally, it addresses methods for fixing setup violations and estimating interconnect parasitics.

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Serajeldeen Ghalyoub 201-801-104
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96 views4 pages

Logic Synthesis and Timing Analysis Guide

The document outlines key concepts and questions related to logic synthesis, including assumptions, timing analysis, hold violations, and the differences between targeting FPGAs and ASICs. It also discusses the importance of specifying constraints in SDC files and the impact of various changes on timing paths and slack values. Additionally, it addresses methods for fixing setup violations and estimating interconnect parasitics.

Uploaded by

Serajeldeen Ghalyoub 201-801-104
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Assignment 3

1- What are the assumptions we make at logic synthesis stage? What design aspects do we
address as well?
2- At which design stage we start analyzing timing with propagated clocks?
3- At which design stage we start fixing hold violations?
4- How do we choose worst and best corners? EMIR worst corner?
5- What is logic synthesis? What are the main steps of it and the objective of each of
them?
6- Please describe logic synthesis inputs and output?
7- What is the difference between target library and link library?
8- What is the main difference between logic synthesis targeting FPGAs, and logic synthesis
targeting ASIC?
9- How do we model external top-level design delays, while developing the block in-hand,
so that when merging our design into top-level no setup-hold violations are reported?
10- Why do we have to specify false paths for optimization and analysis tools?
11- What is a multi-cycle path?
12- How do we estimate interconnect parasitics at logic synthesis?
4ns For all FFs:
Buf2 1ns 2ns 3ns 1ns 1ns 2ns
- Tcq=0.04ns
- Tsetup=0.05ns
10 fF
- Thold=0.03ns

4ns 2ns
2ns 2ns

PLL jitter= 0.1ns

/2 /2

Write and SDC file for each of BLOCK A and BLOCK B


- For each input port; specify a suitable I/P delay constraint and boundary conditions.
- For each output port; specify a suitable O/P delay constraint and boundary conditions.
- For each clock and generated clock, specify it properly for each block.
- Clarify that CK1 and CK2 don’t have inter-clk paths.
3
For the following timing path, what is the new slack value for each of the following changes:
Startpoint: FF1 (rising edge-triggered flip-flop clocked by Clk)
Endpoint: FF2 (rising edge-triggered flip-flop clocked by Clk)
Path Group: Clk
Path Type: max

Point Incr Path


-----------------------------------------------------------
clock Clk (rise edge) 0.00 0.00
clock network delay (propagated) 1.10 * 1.10
FF1/CLK (fdef1a15) 0.00 1.10 r
FF1/Q (fdef1a15) 0.50 * 1.60 r
U2/Y (buf1a27) 0.11 * 1.71 r
U3/Y (buf1a27) 0.11 * 1.82 r
FF2/D (fdef1a15) 0.05 * 1.87 r
data arrival time 1.87

clock Clk (rise edge) 4.00 4.00


clock network delay (propagated) 1.00 * 5.00
FF2/CLK (fdef1a15) 5.00 r
library setup time -0.21 * 4.79
data required time 4.79
------------------------------------------------------------
data required time 4.79
data arrival time -1.87
------------------------------------------------------------
slack (MET) 2.92

• Clk network delay of data required section increased to 1.5ns


• Clk network delay of data arrival section decreased to 0.2ns
• Incremental combinational delay of data arrival section is increased to 1ns.
• Clk frequency changed to 1GHZ.
• If you have a setup violation, how to fix using clock paths only?

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