H. K. E. Society’s S. M.

V College of Engineering
(Affiliated to VTU, Approved by AICTE, Accredited by NAAC)
Yeramarus Camp, Raichur-584135.
Department of Electronics and Communication Engineering

Scheme & Solution for CIE- I

Subject Name with Academi
MICROCONROLLERS(BEC405A) 2023-24
Code: c Year:
Name of the Faculty: Prof. Sangamesh H

Ques. CO RBT
Solutions Marks Mapped Levels
No.
1. Microprocessor Microcontroller 1*5=5 CO-1 L4
Microprocessor contains ALU, Microcontroller contains the
General purpose registers, stack circuitry of microprocessor, and
pointer, program counter, clock in addition it has built in ROM,
timing circuit, interrupt circuit RAM, I/O Devices,
Timers/Counters etc.
It has many instructions to move It has few instructions to move
data between memory and CPU data between memory and CPU
Few bit handling instruction It has many bit handling
instructions
Less number of pins are More number of pins are
multifunctional multifunctional
Single memory map Separate memory map for data
for data and and code (program)
code (program)

2  Eight bit CPU 0.5*10 CO-1 L2

 On chip clock oscillator =5
 4Kbytes of internal program memory (code
memory) [ROM]
 128 bytes of internal data memory [RAM]
 64 Kbytes of external program memory address
space.
 64 Kbytes of external data memory address space.
 32 bi directional I/O lines (can be used as four 8
bit ports or 32 individually addressable I/O lines)
 Two 16 Bit Timer/Counter :T0, T1
 Full Duplex serial data receiver/transmitter
 Four Register banks with 8 registers in each bank.
 Sixteen bit Program counter (PC) and a data pointer
(DPTR)
 8 Bit Program Status Word (PSW)
 8 Bit Stack Pointer
 Five vector interrupt structure (RESET not
considered as an interrupt.)
  8051 CPU consists of 8 bit ALU with
associated registers like accumulator ‘A’ , B
register, PSW, SP, 16 bit program counter, stack
pointer.
 ALU can perform arithmetic and logic functions on
8 bit variables.
 8051 has 128 bytes of internal RAM which is
divided into
o Working registers [00 – 1F]
o Bit addressable memory area [20 – 2F]
o General purpose memory area (Scratch pad
memory) [30-7F]
3
RISC CISC
Instruction takes one or two Instruction takes multiple cycles
cycles
Only load/store instructions are In additions to load and store
used to access memory instructions, memory access is
possible with other instructions
also.
Instructions executed by Instructions executed by the
hardware micro program
Fixed format instruction Variable format instructions
4 Few addressing modes Many addressing modes

Von-Neumann (Princeton Harvard architecture

architecture)
It uses single memory It has separate program
space for both memory and data memory
instructions and data.
It is not possible to fetch Instruction code and data can
instruction code and data be fetched simultaneously
Execution of instruction takes Execution of instruction
more machine cycle takes less machine cycle
Uses CISC architecture Uses RISC architecture
Instruction pre-fetching is a Instruction parallelism is a
main feature main feature
Also known as control flow or Also known as data flow or
control driven computers data driven computers
Simplifies the chip design Chip design is complex due to
because of single memory separate memory space
space
Eg. 8085, 8086, MC6800 Eg. General purpose
microcontrollers, special DSP
chips etc.
Ques. CO RBT
Solutions Marks
No. Mapped Levels

6. 05 CO-1 L2
R7 1F
R6 1E
R5 1D
R4 1C Bank3
R3 1B
BANK 2
3R2 1A
R1 19 7F 78
R0 18
77 70
R7 17
R6 16 6F 68
R5 15 67 60
R4 14 Bank2
R3 13 5F 58
R2 12 57 50
BANK 2
R1 11 4F 48
R0 10 47 40
R7 0F
R6 0E 3F 38
R5 0D 37 30
R4 0C Bank1
2F 28
R3 0B
BANK 1 27 20
R2 0A
R1 09 1F 18
R0 08 17 10
R7 07
0F 08
R6 06
R5 05 07 00
R4 04 Bank0
R3 03
BANK 0

R2 02
01
R1
R0 00

Working Registers (20h-2Fh)Bit addressable

memory

7F
7E
.
.
.
.
.
.
.
.
32
31
30
General Purpose
5

The lower order address and data bus are multiplexed.

De-multiplexing is done by the latch. Initially the address
will appear in the bus and this latched at the output of
latch using ALE signal. The output of the latch is directly
connected to the lower byte address lines of the memory.
Later data will be available in this bus. Still the latch
output is address it self. The higher byte of address bus is
directly connected to the memory. The number of lines
connected depends on the memory size.

The RD and WR (both active low) signals are connected to

RAM for reading and writing the data.

PSEN of microcontroller is connected to the output enable

of the ROM to read the data from the memory.

EA (active low) pin is always grounded if we use only

external memory. Otherwise, once the program size
exceeds internal memory the microcontroller will
automatically switch to external memory.
Ques. CO RBT
Solutions Marks
No. Mapped Levels
7
Pins 1-8 PORT 1. Each of these pins can be configured as an
input or an output
Pin 9 A logic one on this pin disables the microcontroller
and clears the contents of most registers
Pins10-17 Similar to port 1, each of these pins can serve as
general input or output. Besides, all of them have
alternative functions
Pin 10 RXD. Serial asynchronous communication input or
Serial synchronous communication output.
Pin 11 TXD. Serial asynchronous communication
output or Serial synchronous
communication clock output.
Pin 12 INT0.External Interrupt 0 input
Pin 13 INT1. External Interrupt 1 input
Pin 14 T0. Counter 0 clock input
Pin 15 T1. Counter 1 clock input
Pin 16 WR. Write to external (additional) RAM
Pin 17 RD. Read from external RAM
Pin 18, 19 XTAL2, XTAL1.
Pin 20 GND. Ground.
Pin 21-28 Port2 and (A15-A8)
Pin 29 If external ROM is used for storing program then
a logic zero (0) appears on it every time the
microcontroller reads a byte from memory
Pin 30 ALE.(Address Latch Enable)
Pin 30 EA(External Access)
Pin 32-39 Port 0
Pin 40 VCC. +5V power supply.

8 PSW (Program Status Word). This is an 8 bit register which

contains the arithmetic status of ALU and the bank select bits
of register banks.
CY AC F0 RS1 RS0 OV - P
CY-Carry
AC-Auxiliary Carry
F0-User defined Flag
RS1-RS0:Register Select Bank
Ov-Over Flow Flag
P-Parity flag
9 Various methods of accessing the data are called addressing
modes.
1. Immediate addressing.
In this addressing mode the data is provided as a
part of instruction itself. In other words data immediately
follows the instruction.
Eg. MOV A,#30H
ADD A, #83

2.Register addressing.
In this addressing mode the register will hold the
data. One of the eight general registers (R0 to R7) can be
used and specified as the operand
R0 – R7 will be selected from the current selection of register bank. The
default register bank will be bank 0.
3. . Direct addressing:In direct addressing, an 8 bit internal data memory
address is specified as part of the instruction and hence, it can specify the
address only in the range of 00H to FFH.
4. Indirect addressing
The indirect addressing mode uses a register to hold the
actual address that will be used in data movement. Registers R0 and
R1 and DPTR are the only registers that can be used as data
pointers. Indirect addressing cannot be used to refer to SFR
registers. Both R0 and R1 can hold 8 bit address and DPTR can hold
16 bit address.

5.Bit Inherent Addressing

In this addressing, the address of the flag which

contains the operand, is implied in the opcode of the
instruction.

Signature of Staff Signature of HOD