The 8051 Microcontroller

Prepared By, R-THANDAIAH PRABU M.E., Lecturer - ECE

thandaiah@[Link]

Disadvantages of microprocessor
The overall system cost is high A large sized PCB is required for assembling all the components Overall product design requires more time Physical size of the product is big A discrete components are used, the system is not reliable
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Advantages of Microcontroller based System

As the peripherals are integrated into a single chip, the overall system cost is very less The product is of small size compared to micro processor based system The system design now requires very little efforts As the peripherals are integrated with a microprocessor the system is more reliable Though microcontroller may have on chip ROM,RAM and I/O ports, addition ROM, RAM I/O ports may be interfaced externally if required On chip ROM provide a software security

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Three criteria in Choosing a Microcontroller

meeting the computing needs of the task efficiently and cost effectively
speed, the amount of ROM and RAM, the number of I/O ports and timers, size, packaging, power consumption easy to upgrade cost per unit Noise of environment

availability of software development tools

assemblers, debuggers, C compilers, emulator, simulator, technical support

wide availability and reliable sources of the microcontrollers

 ROM type
8031 80xx 87xx 89xx

Comparison of the 8051 Family Members

no ROM mask ROM EPROM Flash EEPROM

89xx
8951 8952 8953 8955 898252 891051 892051

Example (AT89C51,AT89LV51)
AT= ATMEL(Manufacture) C = CMOS technology LV= Low Power(3.0v)

Comparison some of the 8051 Family Members

ROM
8051 8031 8751 8052 8032 8752 4k 4k eprom 8krom 8k eprom

RAM
128 128 128 256 256 256

Timer
2 2 2 3 3 3

8051 Basic Component

4K bytes internal ROM 128 bytes internal RAM Four 8-bit I/O ports (P0 - P3). Two 16-bit timers/counters One serial interface 64k external memory for code 64k external memory for data Microcontroller 210 bit addressable

The basic 8051 Core

8-bit CPU optimized for control applications Capability for single bit Boolean operations. Supports up to 64K of program memory. Supports up to 64K of data memory. 4 K bytes of on-chip program memory. Newer devices provide more. 128 or 256 bytes of on-chip data RAM Four 8 bit ports. Two 16-bit timer/counters UART Interrupts On-chip clock oscillator
8

Block Diagram
External interrupts Interrupt Control On-chip ROM for program code
Timer/Counter

On-chip RAM

Timer 1 Timer 0

Counter Inputs

CPU
Serial Port

OSC

Bus Control

4 I/O Ports

P0 P1 P2 P3

TxD RxD

Address/Data

8051 Internal Block Diagram

8051 Schematic Pin out

8051 Foot Print

P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST (RXD)P3.0 (TXD)P3.1 (INT0)P3.2 (INT1)P3.3 (T0)P3.4 (T1)P3.5
(WR)P3.6 (RD)P3.7 XTAL2 XTAL1 GND

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

8051
(8031) (8751) (8951)

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

Vcc P0.0(AD0) P0.1(AD1) P0.2(AD2) P0.3(AD3) P0.4(AD4) P0.5(AD5) P0.6(AD6) P0.7(AD7) EA/VPP ALE/PROG PSEN P2.7(A15) P2.6(A14) P2.5(A13) P2.4(A12) P2.3(A11) P2.2(A10) P2.1(A9) P2.0(A8)

Power-On RESET Circuit

Vcc

+ 10 uF 31 30 pF 11.0592 MHz 8.2 K 30 pF 18 X2 9 RST EA/VPP X1

19

Port 0 with Pull-Up Resistors

Vcc
10 K

P0.0 DS5000 P0.1 P0.2 8751 P0.3 P0.4 8951 P0.5 P0.6 P0.7

Port 0

IMPORTANT PINS (IO Ports)

One of the most useful features of the 8051 is that it contains four I/O ports (P0 - P3) Each port can be used as input or output (bi-direction)

Port 0 pins 32-39 P0.0P0.7

8-bit R/W - General Purpose I/O Or acts as a multiplexed low byte address and data bus for external memory design

IMPORTANT PINS (IO Ports)

Port 1 pins 1-8

P1.0P1.7

Only 8-bit R/W General Purpose I/O

IMPORTANT PINS (IO Ports)

Port 2 pins 21-28P2.0 P2.7

8-bit R/W General Purpose I/O Or high byte of the address bus for external memory design

IMPORTANT PINS (IO Ports)

Port 3 pins 10-17 P3.0P3.7

General Purpose I/O if not using any of the internal peripherals (timers) or external interrupts.

Port 3 Alternate Functions

 ALE

- Address latch enable to select valid address EA/Vpp - External access enable EA-0 execute program in external memory EA-1 execute program in internal memory Vpp it receives 21 V for on chip EPROM PSEN Program store enable store to read the external program memory
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Registers
A B R0 R1 R2 R3 R4 R5 R6 Some 8051 16-bit Register PC PC DPTR DPH DPL

R7 Some 8-bitt Registers of the 8051

Parallel I/O Ports

Each port can be input or output Direction is set in Special Function Registers

Port0 latch Port0

Port1 latch Port1

Port2 latch Port2

Port3 latch Port3

DPTR
The data pointer consists of a high byte(DPH) and a low byte (DPL). Its function is to hold a 16 bit address. It may be manipulated as a 16 bit data register or two independent 8 bit register. It serves as a base register in indirect jumps, lookup table instructions and external data transfer.
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PROGRAM STATUS WORD (PSW)

CY AC F0 RS1 RS0 OV P

RS0 0 0 1 1

RS1 0 1 0 1

BANK SELECTION 00H 07H BANK0 08H 0FH BANK 1 10H 17H BANK2 18H 1FH BANK 3

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Stack in the 8051

7FH

The register used to access the stack is called SP (stack pointer) register. 30H
2FH

Scratch pad RAM

The stack pointer in the 8051 is only 8 bits wide, which means that it can take value 00 to FFH. When 8051 powered up, the SP register contains value 07.

Bit-Addressable RAM
20H 1FH 18H 17H 10H 0FH 08H 07H 00H

Register Bank 3 Register Bank 2 (Stack) Register Bank 1 Register Bank 0

Memory Organization
The 8051 memory organization is rather complex. The 8051 has separate address spaces for Program Memory, Data Memory, and external RAM. This is refereed to as a Harvard architecture. The early Mark I (1944) computer developed at Harvard was of this type of architecture. Von Neumann at Princeton pointed out that it was not necessary to put instructions and data in separate memories. Most machines have been Princeton architecture. Recently Harvard architecture has been employed to help alleviate the memory bottleneck. Both program memory and external data memory are 8 bits wide and use 16 bits of address. The internal data memory is accessed using an 8-bit address. Since the same address can refer to different locations the specific location is determined by the type of instruction.

Program or Code Memory

May consist of internal or external program memory. The amount of internal program memory varies depending on the device. 4K bytes typical in older devices. The Silicon Labs C8051F310 contains 16K of flash memory for programs. The Silicon Labs C8051F020 which is on the University Daughter Card (UDC) contains 4K bytes of program memory. The MOVC instruction can be use to read code memory. To reference code memory I will use the notation: CM = CM(0,,FFFFH) = CM(0,,FFFFH; 7,,0) This notation can be used to specify particular bits and bytes of code memory. For example CM(1234H) refers to the byte of code memory at address 1234H. CM(1234H;7) refers to the most significant bit in that address.

MOVC A,@A + DPTR ;A CM(A+DPTR) MOVC A,@A + PC ;A CM(A+PC)

CM

PC = PC(15..0) DPTR = DPTR(15..0)

 Supports up to 64K bytes external memory.

XM(0000,,FFFF) = XM(0000,,FFFF; 7,,0) Accessed by using the MOVX instruction.

External Memory

On the original using external memory reduces number of available I/O ports. On some new devices this is not the case.
For example in C8051F020 64K bytes of external memory has been included in the chip. The 4 standard 8051 ports are available and three additional ports have been added.
MOVX MOVX MOVX MOVX A,@DPTR ;A XM(DPTR) A,@Rn ;A XM(P2|Rn) @DPTR,A ;XM(DPTR) A @Rn,A ;XM(P2|Rn) A

Data Memory
The original 8051 had 128 bytes of on-chip data RAM.
This memory includes 4 banks of general purpose registers at DM(00..1F) Only one bank can be active at a time. If all four banks are used, DM(20..7F) is available for program data. DM(20..2F) is bit addressable as BADM(00..7F).

DM(80,,FF) contains the special function registers such as I/O ports, timers, UART, etc.
Some of these are bit addressable using BADM(80..FF)

On newer versions of the 8051, DM(80,,FF) is also use as data memory. Thus, the special functions registers and data memory occupy the same address space. Which is accessed is determined by the instruction being used.

MOV A,0A2H MOV R1,#0A2H MOV A@R1

XM

MOV A,62H
MOV R1,#62H MOV A@R1

DM

Data memory

Data Memory (DM)

Intel 8051: Timers/Counters

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Timer

Timer/Counter Mode Control Register TMOD

A timer is a counter that is increased with every time an instruction is executed e.g. 8051 with 12MHz increases a counter every 1.000 s

General 8051 has 3 timer:

Timer/Counter Control Register TCON

2 16-bit timer 1 16-bit timer with extra-functionality (introduced with the 8052)

Uses of Timers & Counters - Interval Timing - Periodic event timing - Time base for measurements - Event Counting -Baud Rate Generation 8051 Timers - 2 timers (Timer 0 and Timer 1) - 16-bit timers (65,535) max - Flag is set when the timer overflows -Timers can be based on internal clock (OSC/6) or from external source (counter mode). TMOD - Timer/Counter mode register TCON - Timer/Counter control register
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TMOD Register:

Gate : When set, timer only runs while INT(0,1) is C/T : Counter/Timer select bit. M1 : Mode bit 1. M0 : Mode bit 0.

high.

TCON Register:
TF: Overflow flag Set by hardware on Timer/Counter overflow Cleared by hardware when processor vectors to interrupt routine TR: Run control bit Set/Cleared by software to turn Timer/Counter on/off IE: Interrupt Edge flag Set by hardware when external interrupt edge detected Cleared when interrupt processed IT: Interrupt Type control bit Set/Cleared by software to specify falling edge/low level triggered external interrupts

TF1: Timer 1 overflow flag. TR1: Timer 1 run control bit. TF0: Timer 0 overflag. TR0: Timer 0 run control bit. IE1: External interrupt 1 edge flag. IT1: External interrupt 1 type flag. IE0: External interrupt 0 edge flag. IT0: External interrupt 0 type flag.

Internal clock
To Counter/Timer

Falling edge-trigger

External clock

Timer Modes - 0: 13 bit timer - 1: 16-bit timer - 2: 8-Bit auto reload -3: Split timer mode

Mode 0: 13-Bit Timer - Lower byte (TL0/TL1) + 5 bits of upper bytes (TH0/TH1). - Backward compatible to the 8048 - Not generally used
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Mode 1: 16-bit - All 16 bits of the timer (TH0/TL0, TH1,TL1) are used. - Maximum count is 65,536 -At 12Mhz, maximum interval is 65536 microseconds or 65.536 milliseconds - TF0 must be reset after each overflow - THx / TLx must be manually reloaded after each overflow.

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Mode 2: 8-bit Auto Reload

- Only the lower byte (TLx) is used for counting. - Upper byte (THx) holds the value to reload into TLx after an overflow. - TFx must be manually cleared. - Maximum count is 256 - Maximum interval is 256 Microseconds or .256 milliseconds

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Mode 3- Split Timer - Splits Timer 0 into two 8-bit timers - TL0 sets TF0 - TH0 sets TF1 - Timer 1 is available for other 3 modes, but the TF1 is not available.

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Timer Delay and Timer Reload Value

Timer Delay = Delay Value Timer Clock Cycle Duration

Delay Value = how many counts before register(s) roll over Timer Clock Cycle Duration = 6/oscillator frequency Delay Value = Maximum Register Count Timer Reload Value Maximum Register Count = 65535

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