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Rev 0; 9/07

Dual-Channel, I2C Adjustable

Sink/Source Current DAC
General Description Features

DS4412
The DS4412 contains two I2C adjustable-current DACs ♦ Two Current DACs
that are each capable of sinking or sourcing current. Each ♦ Full-Scale Current 500µA to 2mA
output has 15 sink and 15 source settings that are pro-
♦ Full-Scale Range for Each DAC Determined by
grammed by I2C interface. The full-scale range and step
External Resistors
size of each output is determined by an external resistor
that can adjust the output current over a 4:1 range. ♦ 15 Settings Each for Sink and Source Modes
The output pins, OUT0 and OUT1, power-up in a high- ♦ I2C-Compatible Serial Interface
impedance state. ♦ Low Cost
♦ Small Package (8-Pin µSOP)
Applications ♦ -40°C to +85°C Temperature Range
Power-Supply Adjustment ♦ 2.7V to 5.5V Operation
Power-Supply Margining
Adjustable Current Sink or Source

Ordering Information
Pin Configuration
PART TEMP RANGE PIN-PACKAGE
DS4412U+ -40°C to +85°C 8 μSOP
TOP VIEW
DS4412U+T&R -40°C to +85°C 8 μSOP
+ +Denotes a lead-free package.
SDA 1 8 VCC T&R = Tape and reel.
SCL 2 7 OUT1
FS1 3 DS4412 6 OUT0
GND 4 5 FS0

μSOP

Typical Operating Circuit

VCC VOUT0

VOUT1

4.7kΩ 4.7kΩ VCC OUT OUT

SDA DC-DC DC-DC

R0A R1A
SCL CONVERTER CONVERTER
OUT0 FB FB
DS4412 OUT1
GND R0B R1B

FS0 FS1

RFS0 RFS1

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Dual-Channel, I2C Adjustable

Sink/Source Current DAC
ABSOLUTE MAXIMUM RATINGS
DS4412

Voltage Range on VCC, SDA, and SCL Operating Temperature Range ...........................-40°C to +85°C
Relative to Ground.............................................-0.5V to +6.0V Storage Temperature Range .............................-55°C to +125°C
Voltage Range on OUT0, OUT1 Relative to Soldering Temperature .....................................Refer to IPC/JEDEC
Ground ................-0.5V to (VCC + 0.5V) (Not to exceed 6.0V.) J-STD-020 Specification

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

(TA = -40°C to +85°C)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Voltage VCC (Note 1) 2.7 5.5 V
0.7 x VCC +
Input Logic 1 (SDA, SCL) VIH V
VCC 0.3
0.3 x
Input Logic 0 (SDA, SCL) VIL -0.3 V
VCC

DC ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +5.5V, TA = -40°C to +85°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Supply Current ICC VCC = 5.5V (Note 2) 500 μA
Input Leakage (SDA, SCL) I IL VCC = 5.5V 1 μA
Output Leakage (SDA) IL 1 μA
VOL = 0.4V 3
Output Current Low (SDA) I OL mA
VOL = 0.6V 6
RFS Voltage VRFS 0.607 V

OUTPUT CURRENT CHARACTERISTICS

(VCC = +2.7V to +5.5V, TA = -40°C to +85°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output Voltage for Sinking VOUT:SINK VCC > V OUT:SINK (Note 3) 0.5 3.5 V
Output Voltage for Sourcing VCC -
VOUT:SOURCE (Note 3) 0 V
Current 0.75
Full-Scale Sink Output Current IOUT:SINK (Note 3) 0.5 2.0 mA
Full-Scale Source Output Current IOUT:SOURCE (Note 3) -2.0 -0.5 mA
+25°C, VCC = 4.0V; using 0.1% RFS
Output-Current Full-Scale
I OUT:FS resistor (Note 4) ±6 %
Accuracy
VOUT0 = VOUT1 = 1.2V
Output-Current Temperature
I OUT:TC (Note 5) ±75 ppm/°C
Coefficient
Output-Current Variation due to DC source +0.36
%/V
Power-Supply Change DC sink +0.12

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Dual-Channel, I2C Adjustable

Sink/Source Current DAC
OUTPUT CURRENT CHARACTERISTICS (continued)

DS4412
(VCC = +2.7V to +5.5V, TA = -40°C to +85°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output-Current Variation due to DC source, V OUT measured at 1.2V -0.02
%/V
Output Voltage Change DC sink, VOUT measured at 1.2V +0.12
Output Leakage Current at Zero
I ZERO -1 +1 μA
Current Setting
Output-Current Differential
DNL (Note 6) 0.5 LSB
Linearity
Output-Current Integral Linearity INL (Note 7) 1 LSB

I2C AC ELECTRICAL CHARACTERISTICS

(VCC = +2.7V to +5.5V, TA = -40°C to +85°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCL Clock Frequency fSCL (Note 8) 0 400 kHz
Bus Free Time Between STOP
tBUF 1.3 µs
and START Conditions
Hold Time (Repeated) START
tHD:STA 0.6 µs
Condition
Low Period of SCL tLOW 1.3 µs
High Period of SCL tHIGH 0.6 µs
Data Hold Time tDH:DAT 0 0.9 µs
Data Setup Time tSU:DAT 100 ns
START Setup Time tSU:STA 0.6 µs
20 +
SDA and SCL Rise Time tR (Note 9) 300 ns
0.1CB
20 +
SDA and SCL Fall Time tF (Note 9) 300 ns
0.1CB
STOP Setup Time tSU:STO 0.6 µs
SDA and SCL Capacitive Loading CB (Note 9) 400 pF

Note 1: All voltages with respect to ground, currents entering the IC are specified positive and currents exiting the IC are negative.
Note 2: Supply current specified with all outputs set to zero current setting with all inputs driven to well-defined logic levels. SDA and
SCL are connected to VCC. Excludes current through RFS resistors (IRFS). Total current includes ICC + 2.5 x (IRFS0 + IRFS0).
Note 3: The output voltage range must be satisfied to ensure the device meets its accuracy and linearity specifications.
Note 4: Input resistors RFS must be between 2.25kΩ and 9.0kΩ to ensure the device meets its accuracy and linearity specifications.
Note 5: Temperature drift excludes drift caused by external resistor.
Note 6: Differential linearity is defined as the difference between the expected incremental current increase with respect to position
and the actual increase. The expected incremental increase is the full-scale range divided by 15.
Note 7: Integral linearity is defined as the difference between the expected value as a function of the setting and the actual value.
The expected value is a straight line between the zero and the full-scale values proportional to the setting.
Note 8: Timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I2C standard-mode timing.
Note 9: CB—total capacitance of one bus line in pF.

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Dual-Channel, I2C Adjustable

Sink/Source Current DAC
Pin Description
DS4412

NAME PIN FUNCTION

SDA 1 I2C Serial Data. Input/output for I2C data.
SCL 2 I2C Serial Clock. Input for I2C clock.
FS1 3 Full-Scale Calibration Inputs. A resistor to ground on these pins determines the full-scale current
FS0 5 for each output. FS0 controls OUT0, FS1 controls OUT1.
GND 4 Ground
OUT0 6 Current Outputs. Sinks or sources the current determined by the register settings and the
OUT1 7 resistance connected to FS0 and FS1.
VCC 8 Power Supply

Typical Operating Characteristics

(Applies to OUT0 and OUT1. VCC = 2.7V to 5.0V, SDA = SCL = VCC, TA = +25°C, and no loads on OUT0, OUT1, FS0, or FS1, unless
otherwise noted.)

SUPPLY CURRENT SUPPLY CURRENT

vs. SUPPLY VOLTAGE vs. TEMPERATURE VOLTCO (SOURCE)
0.5 0.35 2.5

DS4412 toc03
DS4412 toc01

DS4412 toc02
VCC = 5.0V 2.2kΩ LOAD ON FS0 AND FS1
0.30
0.4 2.4
SUPPLY CURRENT (mA)

SUPPLY CURRENT (mA)

DOES NOT INCLUDE CURRENT DRAWN BY 0.25

RESISTORS CONNECTED TO FS0 AND FS1.
0.3 2.3
IOUT (mA)

0.20 VCC = 3.3V

0.15 2.2
0.2 VCC = 2.7V
0.10
0.1 DOES NOT INCLUDE CURRENT DRAWN BY 2.1
0.05 RESISTORS CONNECTED TO FS0 AND FS1.

0 0 2.0
2.7 3.2 3.7 4.2 4.7 5.2 -40 -20 0 20 40 60 80 0 1 2 3 4 5
SUPPLY VOLTAGE (V) TEMPERATURE (°C) VOUT (V)

TEMPERATURE COEFFICIENT TEMPERATURE COEFFICIENT

VOLTCO (SINK) vs. SETTING (SOURCE) vs. SETTING (SINK)
-2.0 80 80
DS4412 toc04

DS4412 toc05

DS4412 toc06

2.2kΩ LOAD ON FS0 AND FS1

+25°C TO -40°C
TEMPERATURE COEFFICIENT (°C/ppm)

TEMPERATURE COEFFICIENT (°C/ppm)

70 70
-2.1
60 60 +25°C TO -40°C
+25°C TO +85°C
-2.2 50 50
IOUT (mA)

40 40
-2.3 +25°C TO +85°C
30 30

20 RANGE FOR THE 0.5mA TO 2.0mA 20 RANGE FOR THE 0.5mA TO 2.0mA
-2.4 CURRENT-SOURCE RANGE. CURRENT-SOURCE RANGE.
10 10

-2.5 0 0
0 1 2 3 4 0 5 10 15 0 5 10 15
VOUT (V) SETTING (DEC) SETTING (DEC)

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Dual-Channel, I2C Adjustable

Sink/Source Current DAC
Typical Operating Characteristics (continued)

DS4412
(Applies to OUT0 and OUT1. VCC = 2.7V to 5.0V, SDA = SCL = VCC, TA = +25°C, and no loads on OUT0, OUT1, FS0, or FS1, unless
otherwise noted.)

INTEGRAL LINEARITY DIFFERENTIAL LINEARITY

1.0000 1.0

DS4412 toc07

DS4412 toc08
RANGE FOR THE 0.5mA TO 2.0mA RANGE FOR THE 0.5mA TO 2.0mA
0.7500 0.8 CURRENT SOURCE AND SINK RANGE
CURRENT SOURCE AND SINK RANGE
0.6
0.5000
0.4
0.2500 0.2

DNL (LSB)
INL (LSB)

0.0000 0

-0.2500 -0.2
-0.4
-0.5000
-0.6
-0.7500 -0.8
-1.0000 -1.0
0 5 10 15 0 5 10 15
SETTING (DEC) SETTING (DEC)

Block Diagram

SDA SCL

VCC
I2C-COMPATIBLE
SERIAL INTERFACE
DS4412
VCC

F8h F9h
SOURCE OR
15 POSITIONS
SINK MODE
EACH FOR SINK
GND CURRENT AND SOURCE CURRENT
DAC0 MODE DAC1

FS0 OUT0 FS1 OUT1

RFS0 RFS1

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Dual-Channel, I2C Adjustable

Sink/Source Current DAC
Detailed Description Memory Organization
DS4412

The DS4412’s current sources are controlled by writing

The DS4412 contains two I 2 C adjustable-current
to the memory addresses in Table 1.
sources that are each capable of sinking and sourcing
current. Each output, OUT0 and OUT1, has 15 sink and
15 source settings that are programmed through the
Table 1. Memory Addresses
I2C interface. The full-scale ranges and corresponding MEMORY ADDRESS
step sizes of the outputs are determined by external CURRENT SOURCE
(HEXADECIMAL)
resistors, connected to pins FS0 and FS1, which can
0xF8 OUT0
adjust the output currents over a 4:1 range. The formula
to determine the positive and negative full-scale current 0xF9 OUT1
ranges for each of the four outputs is given by:

RFS = (VRFS / IFS) x (15 / 1.974) The format of each output control register is given by:
where V RFS is the R FS voltage (see DC Electrical MSB LSB
Characteristics), and RFS is the external resistor value. S X X X D3 D2 D1 D0
On power-up, the DS4412 outputs zero current. This is
done to prevent it from sinking or sourcing an incorrect Where:
current before the system host controller has had a
chance to modify the device’s setting. POWER-ON
BIT NAME FUNCTION
As a source for biasing instrumentation or other cir- DEFAULT
cuits, the DS4412 provides a simple and inexpensive
Determines if DAC sources
current source with an I2C interface for control. The or sinks current. For sink
S Sign Bit 0b
adjustable full-scale range allows the application to get
S = 0, for source S = 1.
the most out of its 4-bit sink or source resolution.
X Reserved Reserved. XXX
When used in adjustable power-supply applications
(see Typical Operating Circuit), the DS4412 does not 4-Bit Data Word Controlling
affect the initial power-up supply voltage because it DAC Output. Setting 0000b
defaults to providing zero output current on power-up. DX Data outputs zero current 0000b
As it sources or sinks current into the feedback voltage regardless of the state of the
node, it changes the amount of output voltage required sign bit.
by the regulator to reach its steady state operating
point. Using the external resistor, RFS, to set the output
current range, the DS4412 provides some flexibility for Example: RFS0 = 4.8kΩ and register 0xF8h is written to
adjusting the range over which the power supply can a value of 0x8Ah. Calculate the output current.
be controlled or margined.
IFS = (0.607V / 4.8kΩ) x (15 / 1.974) = 949.85µA

The MSB of the output register is 1, so the output is

sourcing the value corresponding to position Ah (10 dec-
imal). The magnitude of the output current is equal to:

949.85µA x (10 / 15) = 633.23µA

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Dual-Channel, I2C Adjustable

Sink/Source Current DAC
I2C Serial Interface Description new data transfer following the current one. Repeated

DS4412
starts are commonly used during read operations to
I2C Slave Address identify a specific memory address to begin a data
The DS4412’s slave address is 90h. transfer. A repeated START condition is issued identi-
cally to a normal START condition. See Figure 1 for
I2C Definitions applicable timing.
The following terminology is commonly used to describe
I2C data transfers: Bit Write: Transitions of SDA must occur during the
low state of SCL. The data on SDA must remain valid
Master Device: The master device controls the slave and unchanged during the entire high pulse of SCL,
devices on the bus. The master device generates plus the setup and hold time requirements (Figure 1).
SCL clock pulses and START and STOP conditions. Data is shifted into the device during the rising edge
Slave Devices: Slave devices send and receive of the SCL.
data at the master’s request. Bit Read: At the end of a write operation, the master
Bus Idle or Not Busy: Time between STOP and must release the SDA bus line for the proper amount
START conditions when both SDA and SCL are inac- of setup time (Figure 1) before the next rising edge of
tive and in their logic-high states. When the bus is SCL during a bit read. The device shifts out each bit of
idle it often initiates a low-power mode for slave data on SDA at the falling edge of the previous SCL
devices. pulse and the data bit is valid at the rising edge of the
START Condition: A START condition is generated current SCL pulse. Remember that the master gener-
by the master to initiate a new data transfer with a ates all SCL clock pulses, including when it is reading
slave. Transitioning SDA from high to low while SCL bits from the slave.
remains high generates a START condition. See Acknowledgement (ACK and NACK): An
Figure 1 for applicable timing. Acknowledgement (ACK) or Not Acknowledge
STOP Condition: A STOP condition is generated by (NACK) is always the ninth bit transmitted during a
the master to end a data transfer with a slave. byte transfer. The device receiving data (the master
Transitioning SDA from low to high while SCL during a read or the slave during a write operation)
remains high generates a STOP condition. See performs an ACK by transmitting a zero during the
Figure 1 for applicable timing. ninth bit. A device performs a NACK by transmitting
a one during the ninth bit. Timing for the ACK and
Repeated START Condition: The master can use a NACK is identical to all other bit writes (Figure 2). An
repeated START condition at the end of one data ACK is the acknowledgment that the device is prop-
transfer to indicate that it will immediately initiate a erly receiving data. A NACK is used to terminate a

SDA

tBUF tSP
tHD:STA
tLOW
tR tF

SCL

tHD:STA tHIGH tSU:STA

STOP START tSU:DAT REPEATED tSU:STO

START
tHD:DAT

NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN).

Figure 1. I2C Timing Diagram

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Dual-Channel, I2C Adjustable

Sink/Source Current DAC
DS4412

TYPICAL I2C WRITE TRANSACTION

MSB LSB MSB LSB MSB LSB

START 1 0 0 1 0 0 0 R/W SLAVE b7 b6 b5 b4 b3 b2 b1 b0 SLAVE b7 b6 b5 b4 b3 b2 b1 b0 SLAVE STOP
ACK ACK ACK

SLAVE READ/ REGISTER/MEMORY ADDRESS DATA

ADDRESS WRITE

EXAMPLE I2C TRANSACTIONS

90h F9h
A) SINGLE BYTE WRITE
START 1 0 0 1 0 0 0 0 SLAVE 1 1 1 1 1 0 0 1 SLAVE 0 0 0 0 0 0 0 0 SLAVE STOP
-WRITE RESISTOR ACK ACK ACK
F9h TO 00h
90h F8h 90h DATA
B) SINGLE BYTE READ MASTER
START 1 0 0 1 0 0 0 0 SLAVE 1 1 1 1 1 0 0 0 SLAVE REPEATED 1 0 0 1 0 0 0 1 SLAVE STOP
-READ RESISTOR F8h ACK ACK START ACK NACK

Figure 2. I2C Communication Examples

read sequence or as an indication that the device is When the R/W bit is 0 (such as in 90h), the master is
not receiving data. indicating it will write data to the slave. If R/W = 1
Byte Write: A byte write consists of 8 bits of informa- (91h in this case), the master is indicating it wants to
tion transferred from the master to the slave (most sig- read from the slave. If an incorrect slave address is
nificant bit first) plus a 1-bit acknowledgement from written, the DS4412 assumes the master is commu-
the slave to the master. The 8 bits transmitted by the nicating with another I2C device and ignores the
master are done according to the bit-write definition, communication until the next START condition is
and the acknowledgement is read using the bit-read sent.
definition. Memory Address: During an I2C write operation,
Byte Read: A byte read is an 8-bit information trans- the master must transmit a memory address to iden-
fer from the slave to the master plus a 1-bit ACK or tify the memory location where the slave is to store
NACK from the master to the slave. The 8 bits of the data. The memory address is always the second
information that are transferred (most significant bit byte transmitted during a write operation following
first) from the slave to the master are read by the the slave address byte.
master using the bit read definition above, and the I2C Communication
master transmits an ACK using the bit write defini- Writing to a Slave: The master must generate a START
tion to receive additional data bytes. The master condition, write the slave address byte (R/W = 0), write
must NACK the last byte read to terminated commu- the memory address, write the byte of data, and gener-
nication so the slave will return control of SDA to the ate a STOP condition. Remember that the master must
master. read the slave’s acknowledgement during all byte-write
Slave Address Byte: Each slave on the I2C bus operations.
responds to a slave address byte sent immediately fol- Reading from a Slave: To read from the slave, the
lowing a START condition. The slave address byte master generates a START condition, writes the slave
contains the slave address in the most significant 7 address byte with R/W = 1, reads the data byte with a
bits and the R/W bit in the least significant bit. The NACK to indicate the end of the transfer, and generates
DS4412’s slave address is 90h. a STOP condition.

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Dual-Channel, I2C Adjustable

Sink/Source Current DAC
Application Information Where:

DS4412
VFB
Example Calculation IR0B =
for an Adjustable Power Supply R 0B
In this example, the Typical Operating Circuit is used And
as a base to create Figure 3, a 2.0V voltage supply with
±20% margin. The adjustable power supply has a VOUT − VFB
IR0 A =
DC-DC converter output voltage, VOUT, of 2.0V and a R 0A
DC-DC converter feedback voltage, VFB, of 0.8V. To
determine the relationship of R0A and R0B, we start with To create a 20% margin in the supply voltage, the value
the equation: of VOUT is set to 2.4V. With these values in place, R0B is
calculated to be 267Ω, and R0A is calculated to be 400Ω.
R 0B The current DAC in this configuration allows the output
VFB = × VOUT
R 0 A + R 0B voltage to be moved linearly from 1.6V to 2.4V using 15
settings. This corresponds to a resolution of 25.8mV/step.
Substituting VFB = 0.8V and VOUT = 2.0V, the relation-
ship between R0A and R0B is determined to be: VCC Decoupling
To achieve the best results when using the DS4412,
R0A = 1.5 x R0B decouple the power supply with a 0.01µF or 0.1µF
capacitor. Use a high-quality ceramic surface-mount
IOUT0 is chosen to be 1mA (midrange source/sink cur- capacitor if possible. Surface-mount components mini-
rent for the DS4412). Summing the currents into the mize lead inductance, which improves performance,
feedback node, we have the following and ceramic capacitors tend to have adequate high-
frequency response for decoupling applications.
I OUT0 = IR0B − IR0 A

VCC VOUT = 2.0V

4.7kΩ 4.7kΩ VCC OUT

SDA DC-DC IR0A R0A = 400Ω

SCL CONVERTER
OUT0 FB
DS4412 VFB = 0.8V

GND IR0B R0B = 267Ω

FS0

IOUT0
RFS0 = 4.612kΩ

Figure 3. Example Application Circuit

Package Information
For the latest package outline information, go to
www.maxim-ic.com/DallasPackInfo.

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implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

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