LOW SKEW, 1-TO-2 8302I

LVCMOS / LVTTL FANOUT BUFFER Data Sheet

GENERAL DESCRIPTION FEATURES

The 8302I is a low skew, 1-to-2 LVCMOS Fanout Buffer. The • 2 LVCMOS / LVTTL outputs
8302I has a single ended clock input. The single ended clock
• LVCMOS / LVTTL clock input accepts LVCMOS
input accepts LVCMOS or LVTTL input levels. The 8302I features
or LVTTL input levels
a pair of LVCMOS outputs. The 8302I is characterized at full
3.3V for input VDD, and mixed 3.3V and 2.5V for output operating • Maximum output frequency: 200MHz
supply modes (VDDO). Guaranteedoutput and part-to-part skew
• Output skew: 40ps (typical)
c h a r a c t e r i s t i c s m a k e t h e 8 3 0 2 I i d e a l fo r c l o c k
distribution applications demanding well defined performance • Part-to-part skew: 250ps (typical)
and repeatibility.
• Small 8 lead SOIC package saves board space
• Full 3.3V or 3.3V core, 2.5V supply modes
• -40°C to 85°C ambient operating temperature
• Lead-Free package fully RoHS compliant

BLOCK DIAGRAM PIN ASSIGNMENT

VDDO 1 8 Q0
VDD 2 7 GND
CLK 3 6 VDDO
Q0 Q1
GND 4 5
CLK
Q1 8302I
8-Lead SOIC
3.8mm x 4.8mm, x 1.47mm package body
M Package
Top View

©2016 Integrated Device Technology, Inc 1 Revision A March 4, 2016

 8302I Data Sheet

TABLE 1. PIN DESCRIPTIONS

Number Name Type Description
1, 6 VDDO Power Output supply pins.
2 VDD Power Core supply pin.
3 CLK Input Pulldown LVCMOS / LVTTL clock input.
4,7 GND Power Power supply ground.
5 Q1 Output Single clock output. LVCMOS / LVTTL interface levels.
8 Q0 Output Single clock output. LVCMOS / LVTTL interface levels.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.

TABLE 2. PIN CHARACTERISTICS

Symbol Parameter Test Conditions Minimum Typical Maximum Units
CIN Input Capacitance 4 pF
Power Dissipation Capacitance VDD, VDDO = 3.465V 22 pF
CPD
(per output) VDD = 3.465V, VDDO = 2.625V 16 pF
RPULLDOWN Input Pulldown Resistor 51 kΩ
ROUT Output Impedance 7 Ω

©2016 Integrated Device Technology, Inc 2 Revision A March 4, 2016

 8302I Data Sheet

ABSOLUTE MAXIMUM RATINGS

Supply Voltage, VDD 4.6V
NOTE: Stresses beyond those listed under Absolute
Inputs, VI -0.5V to VDD + 0.5 V Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
Outputs, VO -0.5V to VDDO + 0.5V
operation of product at these conditions or any conditions
Package Thermal Impedance, θJA 112.7°C/W (0 lfpm) beyond those listed in the DC Characteristics or AC Charac-
teristics is not implied. Exposure to absolute maximum rating
Storage Temperature, TSTG -65°C to 150°C
conditions for extended periods may affect product reliability.

TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD Core Supply Voltage 3.135 3.3 3.465 V
VDDO Output Power Supply Voltage 3.135 3.3 3.465 V
IDD Power Supply Current 14 mA
IDDO Output Supply Current 5 mA

TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD Core Supply Voltage 3.135 3.3 3.465 V
VDDO Output Supply Voltage 2.375 2.5 2.625 V
IDD Power Supply Current 14 mA
IDDO Output Supply Current 5 mA

TABLE 3C. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH Input High Voltage 2 VDD + 0.3 V
VIL Input Low Voltage -0.3 1.3 V
IIH Input High Current CLK VDD = VIN = 3.465V 150 µA
IIL Input Low Current CLK VDD = 3.465V, VIN = 0V -5 µA
50Ω to VDDO/2 2.6 V
VOH Output High Voltage
IOH = -100µA 2.9 V
50Ω to VDDO/2 0.5 V
VOL Output Low Voltage
IOL = 100µA 0.2 V

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 8302I Data Sheet

TABLE 3D. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH Input High Voltage 2 VDD + 0.3 V
VIL Input Low Voltage -0.3 1.3 V
IIH Input High Current CLK VDD = VIN = 3.465V 150 µA
IIL Input Low Current CLK VDD = 3.465V, VIN = 0V -5 µA
50Ω to VDDO/2 1.8 V
VOH Output High Voltage
IOH = -100µA 2.2 V
50Ω to VDDO/2 0.5 V
VOL Output Low Voltage
IOL = 100µA 0.2 V

TABLE 4A. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40°C TO 85°C

Symbol Parameter Test Conditions Minimum Typical Maximum Units
fMAX Output Frequency 200 MHz
tpLH Propagation Delay, Low-to-High; NOTE 1 ƒ ≤ 200MHz 1.9 2.35 2.8 ns
tsk(o) Output Skew; NOTE 2, 4 40 105 ps
tsk(pp) Part-to-Part Skew; NOTE 3, 4 250 800 ps
tR Output Rise Time 20% to 80% 300 800 ps
tF Output Fall Time 20% to 80% 300 800 ps
ƒ ≤ 133MHz 45 55 %
odc Output Duty Cycle
133MHz < ƒ ≤ 200MHz 40 60 %
Parameters measured at fMAX unless otherwise noted.
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.

TABLE 4B. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = -40°C TO 85°C

Symbol Parameter Test Conditions Minimum Typical Maximum Units
fMAX Output Frequency 200 MHz
tpLH Propagation Delay, Low-to-High; NOTE 1 ƒ ≤ 200MHz 2.3 3.3 ns
tsk(o) Output Skew; NOTE 2, 4 110 ps
tsk(pp) Part-to-Part Skew; NOTE 3, 4 250 800 ps
tR Output Rise Time 20% to 80% 250 650 ps
tF Output Fall Time 20% to 80% 250 650 ps
ƒ ≤ 133MHz 45 55 %
odc Output Duty Cycle
133MHz < ƒ ≤ 200MHz 40 60 %
See Table 4A above for notes.

©2016 Integrated Device Technology, Inc 4 Revision A March 4, 2016

 8302I Data Sheet

PARAMETER MEASUREMENT INFORMATION

3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT

PART-TO-PART SKEW OUTPUT SKEW

OUTPUT RISE/FALL TIME PROPAGATION DELAY

OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD

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 8302I Data Sheet

RELIABILITY INFORMATION

TABLE 5. θJAVS. AIR FLOW TABLE FOR 8 LEAD SOIC

θJA by Velocity (Linear Feet per Minute)

0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 153.3°C/W 128.5°C/W 115.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 112.7°C/W 103.3°C/W 97.1°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

TRANSISTOR COUNT
The transistor count for 8302I is: 322

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 8302I Data Sheet

PACKAGE OUTLINE - SUFFIX M FOR 8 LEAD SOIC

TABLE 6. PACKAGE DIMENSIONS

Millimeters
SYMBOL
MINIMUN MAXIMUM
N 8
A 1.35 1.75
A1 0.10 0.25
B 0.33 0.51
C 0.19 0.25
D 4.80 5.00
E 3.80 4.00
e 1.27 BASIC
H 5.80 6.20
h 0.25 0.50
L 0.40 1.27
α 0° 8°
Reference Document: JEDEC Publication 95, MS-012

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 8302I Data Sheet

TABLE 7. ORDERING INFORMATION

Part/Order Number Marking Package Shipping Packaging Temperature

8302AMILF 8302AMIL 8 lead “Lead Free” SOIC Tube -40°C to +85°C
8302AMILFT 8302AMIL 8 lead “Lead Free” SOIC Tape and Reel -40°C to +85°C

©2016 Integrated Device Technology, Inc 8 Revision A March 4, 2016

 8302I Data Sheet

REVISION HISTORY SHEET

Rev Table Page Description of Change Date

1 Features Section - added Lead-Free bullet.
A 3/24/05
T7 8 Ordering Information Table - added Lead-Free part number.
Updated datasheet’s header/footer with IDT from ICS.
A T7 8 Removed ICS prefix from Part/Order Number column. 7/29/10
10 Added Contact Page.
Removed ICS from the part numbers where needed.
T7 8 Ordering Information - removed quantity from tape and reel. Deleted LF note
A 3/4/16
below table.
Updated data sheet header and footer.

©2016 Integrated Device Technology, Inc 9 Revision A March 4, 2016

 8302I Data Sheet

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