Datasheet RS485 (2020 - 09 - 16 23 - 36 - 15 UTC)
Datasheet RS485 (2020 - 09 - 16 23 - 36 - 15 UTC)
U
TYPICAL APPLICATIO
Driver Outputs
RO1 VCC1
R
RE1
Rt A
DE1
DI1 D GND1
Rt
RO2 VCC2
R
RE2
DE2 B
DI2 D GND2
LTC485 • TA01
LTC485 • TA02
LTC485ff
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LTC485
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ABSOLUTE AXI U RATI GS PACKAGE/ORDER I FOR ATIO
(Note 1)
Supply Voltage ....................................................... 12V TOP VIEW
ORDER PART
Control Input Voltages ................... – 0.5V to VCC + 0.5V NUMBER
RO 1 8 VCC
R
Driver Input Voltage ....................... – 0.5V to VCC + 0.5V RE 2 7 B
LTC485CN8
Driver Output Voltage ........................................... ±14V DE 3 6 A
LTC485CS8
Receiver Input Voltage .......................................... ±14V DI 4 D
5 GND
LTC485IN8
Receiver Output Voltages .............. – 0.5V to VCC + 0.5V LTC485IS8
N8 PACKAGE S8 PACKAGE
Operating Temperature Range 8-LEAD PLASTIC DIP 8-LEAD PLASTIC SOIC S8 PART MARKING
LTC485I ...................................... – 40°C ≤ TA ≤ 85°C TJMAX = 100°C, θJA = 130°C/ W (N)
485
TJMAX = 100°C, θJA = 170°C/ W (S)
LTC485C ......................................... 0°C ≤ TA ≤ 70°C 485I
LTC485M (OBSOLETE) .......... – 55°C ≤ TA ≤ 125°C
Lead Temperature (Soldering, 10 sec)................. 300°C
J8 PACKAGE ORDER PART
8-LEAD CERAMIC DIP
TJMAX = 155°C, θJA = 100°C/ W (J)
NUMBER
LTC485CJ8
LTC485MJ8
OBSOLETE PACKAGE
Consider the N8 Package for Alternate Source
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 5V ±5%, unless otherwise noted. (Notes 2 and 3)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VOD1 Differential Driver Output Voltage (Unloaded) IO = 0 ● 5 V
VOD2 Differential Driver Output Voltage (with Load) R = 50Ω (RS422) ● 2 V
R = 27Ω (RS485), Figure 1 ● 1.5 5 V
∆VOD Change in Magnitude of Driver Differential R = 27Ω or R = 50Ω, Figure 1 ● 0.2 V
Output Voltage for Complementary States
VOC Driver Common Mode Output Voltage R = 27Ω or R = 50Ω, Figure 1 ● 3 V
∆VOC Change in Magnitude of Driver Common-Mode R = 27Ω or R = 50Ω, Figure 1 ● 0.2 V
Output Voltage for Complementary States
VIH Input High Voltage DE, DI, RE ● 2 V
VIL Input Low Voltage DE, DI, RE ● 0.8 V
IIN1 Input Current DE, DI, RE ● ±2 µA
IIN2 Input Current (A, B) DE = 0, VCC = 0V VIN = 12V ● ±1 mA
or 5.25V VIN = – 7V ● – 0.8 mA
VTH Differential Input Threshold Voltage – 7V ≤ VCM ≤ 12V ● – 0.2 0.2 V
for Receiver
∆VTH Receiver Input Hysteresis VCM = 0V ● 70 mV
VOH Receiver Output High Voltage IO = – 4mA, VID = 200mV ● 3.5 V
VOL Receiver Output Low Voltage IO = 4mA, VID = – 200mV ● 0.4 V
IOZR Three-State (High Impedance) Output VCC = Max, 0.4V ≤ VO ≤ 2.4V ● ±1 µA
Current at Receiver
RIN Receiver Input Resistance – 7V ≤ VCM ≤ 12V ● 12 kΩ
LTC485ff
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LTC485
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SWITCHI G CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.VCC = 5V ±5%, unless otherwise noted. (Notes 2 and 3)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
ICC Supply Current No Load, Pins 2, Outputs Enabled ● 500 900 µA
3, 4 = 0V or 5V Outputs Disabled ● 300 500 µA
IOSD1 Driver Short-Circuit Current, VOUT = HIGH VO = – 7V ● 35 100 250 mA
IOSD2 Driver Short-Circuit Current, VOUT = LOW VO = 10V ● 35 100 250 mA
IOSR Receiver Short-Circuit Current 0V ≤ VO ≤ VCC ● 7 85 mA
tPLH Driver Input to Output RDIFF = 54Ω, CL1 = CL2 = 100pF, ● 10 30 50 ns
tPHL Driver Input to Output (Figures 3 and 5) ● 10 30 50 ns
tSKEW Driver Output to Output ● 5 10 ns
tr, tf Driver Rise or Fall Time ● 3 15 25 ns
tZH Driver Enable to Output High CL = 100pF (Figures 4 and 6) S2 Closed ● 40 70 ns
tZL Driver Enable to Output Low CL = 100pF (Figures 4 and 6) S1 Closed ● 40 70 ns
tLZ Driver Disable Time from Low CL = 15pF (Figures 4 and 6) S1 Closed ● 40 70 ns
tHZ Driver Disable Time from High CL = 15pF (Figures 4 and 6) S2 Closed ● 40 70 ns
tPLH Receiver Input to Output RDIFF = 54Ω, CL1 = CL2 = 100pF, ● 30 90 200 ns
tPHL (Figures 3 and 7) ● 30 90 200 ns
tSKD tPLH – tPHL Differential Receiver Skew ● 13 ns
tZL Receiver Enable to Output Low CRL = 15pF (Figures 2 and 8) S1 Closed ● 20 50 ns
tZH Receiver Enable to Output High CRL = 15pF (Figures 2 and 8) S2 Closed ● 20 50 ns
tLZ Receiver Disable from Low CRL = 15pF (Figures 2 and 8) S1 Closed ● 20 50 ns
tHZ Receiver Disable from High CRL = 15pF (Figures 2 and 8) S2 Closed ● 20 50 ns
Note 1: Absolute maximum ratings are those beyond which the safety of Note 3: All typicals are given for VCC = 5V and TA = 25°C.
the device cannot be guaranteed. Note 4: The LTC485 is guaranteed by design to be functional over a supply
Note 2: All currents into device pins are positive; all currents out ot device voltage range of 5V ±10%. Data sheet parameters are guaranteed over the
pins are negative. All voltages are referenced to device ground unless tested supply voltage range of 5V ±5%.
otherwise specified.
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Receiver Output Low Voltage Receiver Output High Voltage Receiver Output High Voltage
vs Output Current vs Output Current vs Temperature
36 –18 4.8
TA = 25°C TA = 25°C I = 8mA
32 –16 4.6
28 –14 4.4
OUTPUT CURRENT (mA)
24 –12 4.2
20 –10 4.0
16 –8 3.8
12 –6 3.6
8 –4 3.4
4 –2 3.2
0 0 3.0
0 0.5 1.0 1.5 2.0 5 4 3 2 –50 –25 0 25 50 75 100 125
OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) TEMPERATURE (°C)
LTC485 • TPC01 LTC485 • TPC02 LTC485 • TPC03
LTC485ff
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LTC485
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TYPICAL PERFOR A CE CHARACTERISTICS
Receiver Output Low Voltage Driver Differential Output Voltage Driver Differential Output Voltage
vs Temperature vs Output Current vs Temperature
0.9 72 2.4
I = 8mA TA = 25°C RI = 54Ω
0.8 64 2.3
0.6 48 2.1
0.5 40 2.0
0.4 32 1.9
0.3 24 1.8
0.2 16 1.7
0.1 8 1.6
0 0 1.5
–50 –25 0 25 50 75 100 125 0 1 2 3 4 –50 –25 0 25 50 75 100 125
TEMPERATURE (°C) OUTPUT VOLTAGE (V) TEMPERATURE (°C)
LTC485 • TPC03 LTC485 • TPC05 LTC485 • TPC06
Driver Output Low Voltage Driver Output High Voltage TTL Input Threshold
vs Output Current vs Output Current vs Temperature
90 –108 1.64
TA = 25°C TA = 25°C
80 –96 1.63
60 –72 1.61
50 –60 1.60
40 –48 1.59
30 –36 1.58
20 –24 1.57
10 –12 1.56
0 0 1.55
0 1 2 3 4 0 1 2 3 4 –50 –25 0 25 50 75 100 125
OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) TEMPERATURE (°C)
LTC485 • TPC07 LTC485 • TPC08 LTC485 • TPC09
DRIVER ENABLED
6.0 3.6 460
TIME (ns)
TIME (ns)
3.0 0 100
–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
LTC485 • TPC10 LTC485 • TPC11 LTC485 • TPC12
LTC485ff
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LTC485
U U U
PI FU CTIO S
RO (Pin 1): Receiver Output. If the receiver output is DI (Pin 4): Driver Input. If the driver outputs are enabled
enabled(RE low), then if A > B by 200mV, RO will be high. (DE high), then a low on DI forces the outputs A low and
If A < B by 200mV, then RO will be low. B high. A high on DI with the driver outputs enabled will
force A high and B low.
RE (Pin 2): Receiver Output Enable. A low enables the
receiver output, RO. A high input forces the receiver GND (Pin 5): Ground Connection.
output into a high impedance state. A (Pin 6): Driver Output/Receiver Input.
DE (Pin 3): Driver Outputs Enable. A high on DE enables B (Pin 7): Driver Output/Receiver Input.
the driver output. A and B, and the chip will function as a
line driver. A low input will force the driver outputs into a VCC (Pin 8): Positive Supply; 4.75 < VCC < 5.25.
high impedance state and the chip will function as a line
receiver.
TEST CIRCUITS
A
R TEST POINT S1 1k
RECEIVER VCC
OUTPUT
VOD
CRL 1k
S2
R VOC 15pF
LTC485 • F02
B
LTC485 • F01
DE S1
A
A CL1 VCC
DI RO 500Ω
RDIFF OUTPUT
B UNDER TEST S2
B CL2 RE
CL
15pF
LTC485 • F02
LTC485 • F03
Figure 3. Driver/Receiver Timing Test Circuit Figure 4. Driver Timing Test Load #2
U W W
SWITCHI G TI E WAVEFOR S
3V
DI 1.5V f = 1MHz, t r ≤ 10ns, t f ≤ 10ns 1.5V
0V
t PLH t PLH 1/2 VO
B
VO
A
1/2 VO tSKEW t SKEW
VO 90%
80% VDIFF = V(A) – V(B)
0V
10% 20%
–VO
LTC485 • F05
tr tf
5
LTC485
U W W
SWITCHI G TI E WAVEFOR S
3V
DI 1.5V f = 1MHz, t r ≤ 10ns, t f ≤ 10ns 1.5V
0V
t ZL t LZ
5V
A, B 2.3V OUTPUT NORMALLY LOW 0.5V
VOL
VOH
OUTPUT NORMALLY HIGH 0.5V
A, B 2.3V
0V
t ZH t HZ LTC485 • F06
VOH
R 1.5V OUTPUT 1.5V
VOL
t PHL f = 1MHz, t r ≤ 10ns, t f ≤ 10ns t PLH
VOD2
A, B 0V INPUT
–VOD2 LTC485 • F07
3V
RE 1.5V f = 1MHz, t r ≤ 10ns, t f ≤ 10ns 1.5V
0V
t ZL t LZ
5V
R 1.5V OUTPUT NORMALLY LOW 0.5V
U U
FU CTIO TABLES
LTC485 Transmitting LTC485 Receiving
INPUTS LINE OUTPUTS INPUTS OUTPUTS
RE DE DI CONDITION B A RE DE A–B R
X 1 1 No Fault 0 1 0 0 ≥ 0.2V 1
X 1 0 No Fault 1 0 0 0 ≤ – 0.2V 0
X 0 X X Z Z 0 0 Inputs Open 1
X 1 X Fault Z Z 1 0 X Z
LTC485ff
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LTC485
U U W U
APPLICATIO S I FOR ATIO
Basic Theory of Operation (D1) or the N + /P-substrate diode (D2) respectively will
turn on and clamp the output to the supply. Thus, the
Previous RS485 transceivers have been designed using
output stage is no longer in a high impedance state and is
bipolar technology because the common-mode range of
not able to meet the RS485 common-mode range require-
the device must extend beyond the supplies and the device
ment. In addition, the large amount of current flowing
must be immune to ESD damage and latchup. Unfortu-
through either diode will induce the well known CMOS
nately, the bipolar devices draw a large amount of supply
current, which is unacceptable for the numerous applica- latchup condition, which could destroy the device.
tions that require low power consumption. The LTC485 is The LTC485 output stage of Figure 9 eliminates these
the first CMOS RS485/RS422 transceiver which features problems by adding two Schottky diodes, SD3 and SD4.
ultra-low power consumption without sacrificing ESD and The Schottky diodes are fabricated by a proprietary modi-
latchup immunity. fication to the standard N-well CMOS process. When the
output stage is operating normally, the Schottky diodes
The LTC485 uses a proprietary driver output stage, which
allows a common-mode range that extends beyond the are forward biased and have a small voltage drop across
power supplies while virtually eliminating latchup and them. When the output is in the high impedance state and
is driven above VCC or below ground, the parasitic diodes
providing excellent ESD protection. Figure 9 shows the
D1 or D2 still turn on, but SD3 or SD4 will reverse bias and
LTC485 output stage while Figure 10 shows a conven-
prevent current from flowing into the N-well or the sub-
tional CMOS output stage.
strate. Thus, the high impedance state is maintained even
When the conventional CMOS output stage of Figure 10 with the output voltage beyond the supplies. With no
enters a high impedance state, both the P-channel (P1) minority carrier current flowing into the N-well or sub-
and the N-channel (N1) are turned off. If the output is then strate, latchup is virtually eliminated under power-up or
driven above VCC or below ground, the P + /N-well diode power-down conditions.
VCC
VCC
SD3
P1 P1
D1 D1
OUTPUT
LOGIC LOGIC OUTPUT
SD4
N1 D2 N1 D2
Figure 9. LTC485 Output Stage Figure 10. Conventional CMOS Output Stage
LTC485ff
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LTC485
U U W U
APPLICATIO S I FOR ATIO
The LTC485 output stage will maintain a high impedance Propagation Delay
state until the breakdown of the N-channel or P-channel is Many digital encoding schemes are dependent upon the
reached when going positive or negative respectively. The difference in the propagation delay times of the driver and
output will be clamped to either VCC or ground by a Zener the receiver. Using the test circuit of Figure 13, Figures 11
voltage plus a Schottky diode drop, but this voltage is way and 12 show the typical LTC485 receiver propagation
beyond the RS485 operating range. This clamp protects delay.
the MOS gates from ESD voltages well over 2000V.
Because the ESD injected current in the N-well or substrate The receiver delay times are:
consists of majority carriers, latchup is prevented by tPLH – tPHL = 9ns Typ, VCC = 5V
careful layout techniques.
The driver skew times are:
Skew = 5ns Typ, VCC = 5V
10ns Max, VCC = 5V, TA = – 40°C to 85°C
A A
DRIVER DRIVER
OUTPUTS OUTPUTS
B B
RECEIVER RECEIVER
RO RO
OUTPUT OUTPUT
100pF
BR
RECEIVER
TTL IN D R
R OUT
t r, t f < 6ns 100Ω
LTC485 • F13
100pF
LTC485ff
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LTC485
U U W U
APPLICATIO S I FOR ATIO
LTC485 Line Length vs Data Rate Figures 17 and 18 show that the LTC485 is able to
comfortably drive 4000 feet of wire at 110kHz.
The maximum line length allowable for the RS422/RS485
standard is 4000 feet.
RO
100Ω
A C
TTL COMMON MODE
LTC485 LTC485
D OUT
VOLTAGE (A + B)/2
B
4000 FT 26AWG
NOISE
TTL TWISTED PAIR
GENERATOR
IN DI
LTC485 • F17
RO
DI
1k
RO
DIFFERENTIAL 100
VOLTAGE A – B
DI
10
10k 100k 1M 2.5M 10M
MAXIMUM DATA RATE
LTC485 • F16 LTC485 • F19
Figure 16. System Differential Voltage at 19.2kHz Figure 19. Cable Length vs Maximum Data Rate
LTC485ff
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LTC485
U
TYPICAL APPLICATIO S
Rt Rt
LTC485 • TA03
U
PACKAGE DESCRIPTIO
J8 Package
8-Lead CERDIP (Narrow .300 Inch, Hermetic)
(Reference LTC DWG # 05-08-1110)
0.015 – 0.060
(0.381 – 1.524)
0.008 – 0.018
0° – 15°
(0.203 – 0.457)
0.045 – 0.065
0.125
NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE (1.143 – 1.651)
OR TIN PLATE LEADS 3.175
0.014 – 0.026 MIN
0.100
(0.360 – 0.660) (2.54)
BSC J8 1298
OBSOLETE PACKAGE
LTC485ff
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LTC485
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PACKAGE DESCRIPTIO
N8 Package
8-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
0.400*
(10.160)
MAX
8 7 6 5
0.255 ± 0.015*
(6.477 ± 0.381)
1 2 3 4
0.065
(1.651)
0.009 – 0.015 TYP
(0.229 – 0.381) 0.125
(3.175) 0.020
+0.035 MIN (0.508)
0.325 –0.015
( )
0.100 0.018 ± 0.003 MIN
+0.889
8.255 (2.54) (0.457 ± 0.076)
–0.381 BSC
N8 1098
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
8 7 6 5
SO8 1298
1 2 3 4
0.010 – 0.020
× 45° 0.053 – 0.069
(0.254 – 0.508)
(1.346 – 1.752)
0.004 – 0.010
0.008 – 0.010
0°– 8° TYP (0.101 – 0.254)
(0.203 – 0.254)
0.016 – 0.050
0.014 – 0.019 0.050
(0.406 – 1.270)
(0.355 – 0.483) (1.270)
TYP BSC
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
LTC485ff
11
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC485
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LTC485ff
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