tpd3s716-q1

TPD3S716-Q1
SLVSDH9D – MARCH 2016 – REVISED AUGUST 2020
TPD3S716-Q1 Automotive USB 2.0 Interface Protection with Adjustable Current Limit
and Short-to-Battery, Short-Circuit Protection
1 Features 3 Description
• AEC-Q100 Qualified (Grade 1) The TPD3S716-Q1 is a single-chip solution for short-
– Operating Temperature Range: –40°C to to-battery, short-circuit, and ESD protection with
+125°C an adjustable current-limit for the USB connector’s
• Functional Safety-Capable VBUS and data lines in automotive applications.
– Documentation available to aid functional safety The integrated data switches provide best-in-class
system design bandwidth for minimal signal degradation while
• Short-to-Battery (up to 18 V) and Short-to-Ground simultaneously providing 18 V short-to-battery
Protection on VBUS_CON protection. The high bandwidth of 1 GHz allows for
• Short-to-Battery (up to 18 V) and Short-to-VBUS USB2.0 high-speed data rates for applications like
Protection on VD+, VD– Car Play. Extra margin in bandwidth above 720-MHz
• IEC 61000-4-2 ESD Protection on VBUS_CON, also helps to maintain a clean USB 2.0 eye diagram
VD+, VD– with the long captive cables that are common in
– ±8-kV Contact Discharge the automotive USB environment. The short-to-battery
– ±15-kV Air Gap Discharge protection isolates the internal system circuits from
• ISO 10605 330-pF, 330-Ω ESD Protection on any over-voltage conditions at the VBUS_CON, VD+,
VBUS_CON, VD+, VD– and VD– pins. On these pins, the TPD3S716-Q1 can
handle over-voltage protection up to 18 V for hot plug
– ±8-kV Contact Discharge
and DC events. The over-voltage protection circuit
– ±15-kV Air Gap Discharge
provides the most reliable short-to-battery isolation
• Low RON nFET VBUS Switch (63 mΩ typical)
in the industry, shutting off the data switches in 200
• High Speed Data Switches (1-GHz, 3-dB
ns and protecting the upstream circuitry from harmful
Bandwidth)
voltage and current spikes.
• Adjustable Hiccup Current Limit up to 2.4 A
• Fast Over-voltage Response Time The VBUS_CON pin also provides an adjustable current
– 2-µs typical (VBUS switch) limited load switch and handles short-to-ground
– 200-ns typical (Data switches) protection. The device supports VBUS currents up to
• Independent VBUS and Data enable pins for 2.4 A, allowing support for charging USB BC1.2, USB
configuring both Host and Client/OTG mode Type-C 5V/1.5A, and proprietary charging schemes
• Fault Output Signal up to 2.4 A. The separate enable pins for data
• Thermal Shutdown Feature and VBUS allow for both host and client-OTG
• Flow-through layout in 16-Pin SSOP Package mode. TPD3S716-Q1 also integrates system level
(4.9 mm x 3.9 mm) IEC 61000-4-2 and ISO 10605 ESD protection on its
VBUS_CON, VD+, and VD– pins removing the need to
2 Applications provide external high voltage, low capacitance diodes.
• End Equipment Device Information(1)
– Head Units PART NUMBER PACKAGE BODY SIZE (NOM)
– Rear Seat Entertainment
TPD3S716-Q1 SSOP (16) 4.90 mm × 3.90 mm
– Telematics
– USB Hubs (1) For all available packages, see the orderable addendum at
– Navigation Modules the end of the data sheet.
– Media Interface TPD3S716-Q1
5V
• Interfaces VBUS
1 µF
100 V
VBUS_CON
VBUS_SYS
10 NŸ
100 µF
7V
– USB 2.0
X7R
FLT
USB
D± VDt Dt Transceiver
10 nH
D+ VD+ D+
USB2.0 10 nH
CMC
GND VEN From Processor
GND
DEN From Processor
IADJ
VIN 3.3 V
RADJ
1 µF
7V
Copyright © 2016, Texas Instruments Incorporated
Typical Application Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPD3S716-Q1
SLVSDH9D – MARCH 2016 – REVISED AUGUST 2020 www.ti.com
Table of Contents
1 Features............................................................................1 8.3 Feature Description...................................................13
2 Applications..................................................................... 1 8.4 Device Functional Modes..........................................16
3 Description.......................................................................1 9 Application and Implementation.................................. 18
4 Revision History.............................................................. 2 9.1 Application Information............................................. 18
5 Pin Configuration and Functions...................................3 9.2 Typical Application.................................................... 18
Pin Functions.................................................................... 3 10 Power Supply Recommendations..............................23
6 Specifications.................................................................. 4 10.1 VBUS Path................................................................23
6.1 Absolute Maximum Ratings........................................ 4 10.2 VIN Pin.....................................................................23
6.2 ESD Ratings—AEC Specification............................... 4 11 Layout........................................................................... 23
6.3 ESD Ratings—IEC Specification................................ 4 11.1 Layout Guidelines................................................... 23
6.4 ESD Ratings—ISO Specification................................ 4 11.2 Layout Example...................................................... 23
6.5 Recommended Operating Conditions.........................4 11.3 Layout Optimized for Thermal Performance........... 24
6.6 Thermal Information....................................................5 12 Device and Documentation Support..........................26
6.7 Electrical Characteristics.............................................5 12.1 Documentation Support.......................................... 26
6.8 Timing Characteristics.................................................7 12.2 Support Resources................................................. 26
6.9 Typical Characteristics................................................ 9 12.3 Trademarks............................................................. 26
7 Parameter Measurement Information.......................... 12 12.4 Electrostatic Discharge Caution..............................26
8 Detailed Description......................................................13 12.5 Glossary..................................................................26
8.1 Overview................................................................... 13 13 Mechanical, Packaging, and Orderable
8.2 Functional Block Diagram......................................... 13 Information.................................................................... 26
4 Revision History
Changes from Revision C (June 2016) to Revision D (August 2020) Page
• Added functional safety link to the Features section.......................................................................................... 1
• Updated the numbering format for tables, figures and cross-references throughout the document...................1
Changes from Revision B (April 2016) to Revision C (June 2016) Page

• Changed Adjustable Hiccup Current Limit from 1.7 A to 2.4 A in the Features section..................................... 1
• Updated Description section...............................................................................................................................1
• Changed Current through VBUS switch from 1.7 A to 2.4 A................................................................................ 4
• Updated the RADJ minimum resistance to 57 kΩ in Recommended Operating Conditions table....................... 4
• aDDED new current limit values to Electrical Characteristics table ...................................................................5
• Updated Figure 8-1 ..........................................................................................................................................14
• Updated IVBUS Operating Maximum in Figure 9-7 to go up to 2.4 A.................................................................21
Changes from Revision A (April 2016) to Revision B (April 2016) Page

• Made changes to the Electrical Characteristics table......................................................................................... 1
Changes from Revision * (March 2016) to Revision A (April 2016) Page

• Changed device status from Product Preview to Production Data .................................................................... 1
2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: TPD3S716-Q1

TPD3S716-Q1
www.ti.com SLVSDH9D – MARCH 2016 – REVISED AUGUST 2020
5 Pin Configuration and Functions
NC 1 16 IADJ
VBUS_CON 2 15 VBUS_SYS
VBUS_CON 3 14 VBUS_SYS
GND 4 13 GND
VD± 5 12 D±
VD+ 6 11 D+
VEN 7 10 FLT
DEN 8 9 VIN
Figure 5-1. DBQ Package 16-Pin SSOP Top View
Pin Functions
PIN
TYPE DESCRIPTION
NO. NAME
1 NC NC No connect, leave floating or connect to ground. Do not connect to VBUS_CON
2 VBUS_CON O
Connect to USB connector VBUS; provides IEC 61000-4-2 ESD protection
3 VBUS_CON O
4 GND Ground Connect to PCB ground plane
5 VD– I/O Connect to USB connector D–; provides IEC 61000-4-2 ESD protection
6 VD+ I/O Connect to USB connector D+; provides IEC 61000-4-2 ESD protection
Enable Active-Low Input. Drive VEN low to enable the VBUS path of the device. Drive VEN high to
7 VEN I
disable the VBUS path of the device
Enable Active-Low Input. Drive DEN low to enable the data path of the device. Drive DEN high to
8 DEN I
disable the data path of the device
9 VIN I Connect to 3.3-V I/O. Controls the OVP threshold for VD+/VD–
10 FLT O Open-Drain fault pin. See the Detailed Description section for operation
11 D+ I/O Connect to the internal transceiver D+ pin
12 D– I/O Connect to the internal transceiver D– pin
13 GND Ground Connect to PCB ground plane
14 VBUS_SYS I
Connect to internal VBUS plane
15 VBUS_SYS I
16 IADJ I Connect to a resistor to GND to adjust the current limit threshold
Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 3

TPD3S716-Q1
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN MAX UNIT
VBUS_CON Supply voltage from USB connector –0.3 18 V
VBUS_SYS Internal Supply DC voltage Rail on the PCB –0.3 6 V
VD+, VD– Voltage range from connector-side USB data lines –0.3 18 V
D+, D– Voltage range for internal USB data lines –0.3 VIN + 0.3 V
VIN Voltage range for VIN supply input –0.3 4 V
DEN 7 V
Voltage on enable pins
VEN 7 V
IBUS Maximum DC output current on VBUS_CON pin(3) 2.4 A
VVBUS_SYS +
VIADJ Voltage range for IADJ pin –0.3 V
0.3
VFLT Voltage range for the FLT pin –0.3 7 V
TA Operating free air temperature(3) –40 125 °C
TSTG Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum.
(3) Thermal limits and power dissipation limits must be observed.
6.2 ESD Ratings—AEC Specification

VALUE UNIT
Human-body model (HBM), per AEC Q100-002(1) ±4000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per AEC Q100-011 ±1500
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 ESD Ratings—IEC Specification

VALUE UNIT
IEC 61000-4-2, VBUS_CON, Contact discharge(1) ±8000

VD+, VD– pins Air-gap discharge(1) ±15000
(1) See Figure 7-2 for details on system level ESD testing setup.
6.4 ESD Ratings—ISO Specification

VALUE UNIT
ISO 10605 (330 pF, 330 Ω), Contact discharge(1) ±8000

VBUS_CON, VD+, VD– pins Air-gap discharge(1) ±15000
(1) See Figure 7-2 for details on system level ESD testing setup.
6.5 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VBUS_CON Supply voltage from USB connector 5.9 V
VBUS_SYS Internal supply DC voltage Rail on the PCB 4.75 5.9 V
VD+, VD– Voltage range from connector-side USB data lines 0 VIN + 0.3 V

TPD3S716-Q1
6.5 Recommended Operating Conditions (continued)

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
D+, D– Voltage range for internal USB data lines 0 VIN + 0.3 V
VIN Voltage range for VIN supply 3 3.6 V
IBUS Current through VBUS switch(1) 2.4 A
VEN, DEN Voltage range for enable 0 5.9 V
CSYS Input capacitance(2) VBUS_SYS pin 100 µF
CLOAD Output load capacitance(2) VBUS_CON pin 1 µF
CVIN VIN capacitance(2) VIN pin 1 µF
RADJ Resistance of RADJ resistor(2) IADJ pin 57 kΩ
(1) Depending on your IBUS current level, maximum operating junction temperature derating may be required. For IBUS > 1.5A, care
should be taken in the PCB design to improve the board's thermal coefficient. Please see both the Power Dissipation and Junction
Temperature and Layout Optimized for Thermal Performance sections for more details.
(2) See the Figure 9-1 for configuration details.
6.6 Thermal Information

TPD3S716-Q1
THERMAL METRIC(1) DBQ (SSOP) UNIT
16 PINS
θJA Junction-to-ambient thermal resistance 98.8 °C/W
θJCtop Junction-to-case (top) thermal resistance 48.0 °C/W
θJB Junction-to-board thermal resistance 41.6 °C/W
ψJT Junction-to-top characterization parameter 8.5 °C/W
ψJB Junction-to-board characterization parameter 41.2 °C/W
θJCbot Junction-to-case (bottom) thermal resistance N/A °C/W
θJA(Custom) See the Layout Optimized for Thermal Performance section 57.0 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.7 Electrical Characteristics

over operating free-air temperature range, VEN = 0 V, DEN = 0 V, VBUS_SYS = 5 V, VIN = 3.3 V, VD+/VD–/D+/D–/VBUS_CON =
float (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT CONSUMPTION
IVBUS_SLEEP VBUS Sleep current consumption Measured at VBUS_SYS pin, VEN = 5 V, DEN = 5 V 45 150 µA
IVBUS VBUS Operating current consumption Measured at VBUS_SYS pin 285 380 µA
IVIN Leakage current for VIN Measured at VIN pin, VIN = 3.6 V 12 20 µA
Leakage into VBUS_SYS while shorted to Measured flowing into VBUS_SYS pin, VBUS_SYS = 5
ION(LEAK) 225 300 µA
battery and powered on V, VBUS_CON = 18 V
Leakage through VBUS path while Measured flowing out of VBUS_SYS pin, VBUS_SYS = 0
IOFF(LEAK) 50 µA
shorted to battery and unpowered V, VBUS_CON = 18 V
Leakage out of data path while shorted Measured flowing out of D+ or D– pins, VBUS_SYS =
ID(OFF_LEAK) –1 1 µA
to battery and unpowered 0 V, VD+ or VD– = 18 V, VIN = 0 V, D+/D– = 0 V
Leakage out of data path while shorted Measured flowing out of D+ or D– pins, VBUS_SYS =
ID(ON_LEAK) –1 1 µA
to battery and powered on 5 V, VD+ or VD– = 18 V, VIN = 3.3 V, D+/D– = 0 V
Leakage into data path while shorted to Measured flowing in to VD+ or VD– pins, VBUS_SYS
IVD(OFF_LEAK) 85 µA
battery and unpowered = 0 V, VD+ or VD– = 18 V, VIN = 0 V, D+/D– = 0 V
Leakage into data path while shorted to Measured flowing in to VD+ or VD– pins, VBUS_SYS
IVD(ON_LEAK) 85 µA
battery and powered on = 5 V, VD+ or VD– = 18 V, VIN = 3.3 V D+/D– = 0 V
VIN PIN

TPD3S716-Q1
6.7 Electrical Characteristics (continued)

Undervoltage lockout Ramp VIN up until VBUS and Data FETs turn on,
VUVLO(RISING) 2.6 2.7 2.9
rising for VIN VEN =0 V, DEN = 0 V
VIN V
Undervoltage lockout Ramp VIN down until VBUS and Data FETs turn off,
VUVLO(FALLING) 2.5 2.6 2.8
falling for VIN VEN =0 V, DEN = 0 V
VEN, DEN, FLT PINS
Set VEN ( DEN)= 0 V; Sweep VEN ( DEN) to 1.4 V;
VIH High-level input voltage VEN, DEN 1.2 V
Measure when VBUS (Data) FET turns off
Set VEN ( DEN) = 3.3 V; Sweep VEN ( DEN) from
VIL Low-level input voltage VEN, DEN 3.3 V to 0.5 V; Measure when VBUS (Data) FET 0.8 V
turns on
V( VEN) (V( DEN))= 3.3 V ; Measure Current into VEN
IIL Input Leakage Current VEN, DEN 1 µA
( DEN) pin
VOL Low-level output voltage FLT IOL = 3 mA 0.4 V
OCP CIRCUIT—VBUS
Overcurrent limit, RADJ = Progressively load VBUS_CON until device asserts
ILIM VBUS 505 620 mA
280 kΩ ± 1% FLT
ILIM VBUS 0.905 1.1 A
158 kΩ ± 1% FLT
143 kΩ ± 1% FLT
93.1 kΩ ± 1% FLT
76.8 kΩ ± 1% FLT
66.5 kΩ ± 1% FLT
57.6 kΩ ± 1% FLT
Overcurrent limit, IADJ = Progressively load VBUS_CON until device asserts
ILIM VBUS 550 700 850 mA
GND FLT
Overcurrent limit, IADJ = Progressively load VBUS_CON until device asserts
ILIM VBUS 1.1 1.4 1.7 A
VBUS_SYS FLT
OVER TEMPERATURE PROTECTION
The rising over-temperature protection VBUS_SYS = 5 V, VEN = 0 V, DEN = 0 V, No Load on
TSD(RISING) 150 165 180 ℃
shutdown threshold VBUS_CON, TA stepped up until FLT is asserted
VBUS_SYS = 5 V, VEN = 0 V, DEN = 0 V, No Load on
The falling over-temperature protection
TSD(FALLING) VBUS_CON, TA stepped down from TSD(RISING) until 125 130 142 ℃
shutdown threshold
FLT is deasserted
The over-temperature protection
TSD(HYST) TSD(RISING) – TSD(FALLING) 10 35 55 ℃
shutdown threshold hysteresis
OVP CIRCUIT—VBUS
Input overvoltage Increase VBUS_CON from 5 V to 7 V. Measure when
VOVP(RISING) VBUS_CON 5.6 5.8 6 V
protection threshold FLT is asserted
Difference between rising and falling OVP
VHYS(OVP) Hysteresis on OVP VBUS_CON 50 mV
thresholds on VBUS_CON
Input overvoltage Decrease VBUS_CON from 7 V to 5 V. Measure when
VOVP(FALLING) VBUS_CON 5.52 5.75 5.98 V
protection threshold FLT is deasserted
Set VBUS_SYS to 5 V. Increase VBUS_CON from
Reverse supply VBUS_CON – VBUS_SYS to VBUS_SYS + 300 mV. Measure the value
VREV_SUPPLY(RISING) 140 200 260 mV
detection threshold VBUS_SYS of VBUS_CON – VBUS_SYS when FLT asserts.
25°C ≤ TA ≤ 125°C
Set VBUS_SYS to 5 V. Decrease VBUS_CON from
Reverse supply VBUS_CON – VBUS_SYS + 300 mV to VBUS_SYS. Measure the value
VREV_SUPPLY(FALLING) 70 120 165 mV
detection threshold VBUS_SYS of VBUS_CON – VBUS_SYS when FLT deasserts.
25°C ≤ TA ≤ 125°C
Hysteresis on reverse VBUS_CON – Difference between rising and falling reverse supply
VREV_SUPPLY(HYST) 80 mV
supply detection VBUS_SYS detection thresholds

TPD3S716-Q1
6.7 Electrical Characteristics (continued)

Undervoltage lockout
VUVLO(SYS_RISING) VBUS_SYS VBUS_SYS voltage rising from 0 V to 5 V 3.1 3.3 3.6 V
rising for VBUS_SYS
VBUS_SYS UVLO Difference between rising and falling UVLO
VHYS(UVLO_SYS) VBUS_SYS 50 75 100 mV
Hysteresis thresholds on VBUS_SYS
Undervoltage lockout
VUVLO(SYS_FALLING) VBUS_SYS VBUS_SYS voltage falling from 5 V to 2.9 V 3 3.2 3.5 V
falling for VBUS_SYS
Short-to-ground Increase VBUS_CON voltage from 0 V until the device
VSHRT(RISING) comparator rising VBUS_CON transitions from the short-circuit to over-current 2.5 2.6 2.7 V
threshold mode of operation
Set VBUS_SYS = 5 V; VIN = 3.3 V; VEN = 0 V, DEN
Short-to-ground
= 0 V; Decrease VBUS_CON voltage from 5 V until
VSHRT(FALLING) comparator falling VBUS_CON 2.4 2.5 2.6 V
the device transitions from the over-current to short-
threshold
circuit mode of operation
Short-to-ground Difference between VSHRT(RISING) and
VSHRT(HYST) VBUS_CON 125 mV
comparator hysteresis VSHRT(FALLING)
Short-to-ground current Current sourced from VBUS_SYS when device is in
ISHRT VBUS_CON 150 350 mA
source short-circuit mode
OVP CIRCUIT—VD+/VD–
Increase VD+ or VD– (with D+ and D–) from 3.3
Input overvoltage
VOVP(RISING) VD+/VD– V to 4.5 V. Measure the value at which FLT is VIN + 0.6 VIN + 0.8 VIN + 1 V
protection threshold
asserted
Difference between rising and falling OVP
VHYS(OVP) Hysteresis on OVP VD+/VD– 50 mV
thresholds on VD+/VD–
Input overvoltage Decrease VD+ or VD– (with D+ or D–) from 4.5 V to VIN + VIN + VIN +
VOVP(FALLING) VD+/VD– V
protection threshold 2 V. Measure the value at FLT is deasserted 0.525 0.75 0.975
SHORT TO BATTERY
VBUS hotplug short-to-
V(VBUS_STB) VBUS_CON Charge battery-equivalent capacitor to test voltage 18 V
battery tolerance
then discharge to pin under test through a 1 meter,
Data line hotplug short- 18 gauge wire. (See Figure 7-1 for more details)
V(DATA_STB) VD+/VD– 18 V
to-battery tolerance
DATA LINE SWITCHES—VD+ to D+ or VD– to D–
Capacitance of D+/D– switches when enabled –
CON Equivalent On Capacitance 6.9 pF
measure on connector side at VDx = 0.4 V
Measure resistance between D+ and VD+ or D–
RON On Resistance 4 6.5 Ω
and VD–, voltage between 0 V and 0.4 V
Measure resistance between D+ and VD+ or D–
RON(Flat) On Resistance flatness 0.2 1 Ω
and VD–, sweep voltage between 0 V and 0.4 V
Measure S21 bandwidth from D+ to VD+ or D– to
BWON On Bandwidth (–3dB) 910 MHz
VD– with voltage swing = 400 mVpp, VCM= 0.2 V
Measure SDD21 bandwidth from D+ to VD+ and D–
BWON_DIFF On Bandwidth (–3dB) to VD– with voltage swing = 800 mVpp differential, 1050 MHz
VCM= 0.2 V
Measure S21 bandwidth from D+ to VD– or D– to
Xtalk Crosstalk VD+ with voltage swing = 400 mVpp. Make sure to –28 dB
terminate open sides to 50 ohms. f = 480 MHz
nFET SWITCH—VBUS
VEN = 5 V, DEN = 5 V, Set VBUS_CON = 5 V and
R(DISCHARGE) Output discharge resistance 18 30 kΩ
measure current flow to ground
VBUS_CON = 5 V, IOUT = 1.5 A. See Figure 9-8 for a
RON VBUS path ON resistance plot of the maximum VBUS RON possible at a given 63 135 mΩ
junction temperature
6.8 Timing Characteristics

over operating free-air temperature range, VEN = 0 V, DEN = 0 V, VBUS_SYS = 5 V, VIN = 3.3 V, D+/D– = 45 Ω to GND,
VD+/VD–/VBUS_CON = float (unless otherwise noted)
ENABLE PIN

TPD3S716-Q1
over operating free-air temperature range, VEN = 0 V, DEN = 0 V, VBUS_SYS = 5 V, VIN = 3.3 V, D+/D– = 45 Ω to GND,
VD+/VD–/VBUS_CON = float (unless otherwise noted)
Time between VEN and DEN asserted low and VBUS and
tON_HOST Host mode enable on time 5.7 ms
Data FETs turn on, CVBUS_CON = 0 µF
Time between DEN asserted low and Data FETs turn on.
tON_CLIENT Client mode enable on time 2.4 ms
VEN remains high
Time between VEN and DEN deasserted high and VBUS
tOFF_HOST Host mode disable time 30 µs
and Data FETs turn off, CVBUS_CON = 0 µF
Time between DEN deasserted high and Data FETs turn
tOFF_CLIENT Client mode disable time 5 µs
off. VEN remains high
tHOST_TO_CLIE Host to Client mode transition Time between VEN deasserted high and VBUS FET turns
70 µs
NT time off. DEN remains low, CVBUS_CON = 0 µF
tCLIENT_TO_HO Client to Host mode transition Time between VEN asserted low and VBUS FET turns on.
3.4 ms
ST time DEN remains low, CVBUS_CON = 0 µF
OVER CURRENT PROTECTION
Time from overcurrent condition until FLT assertion and
tBLANK Overcurrent blanking time 2 ms
VBUS FET turn off
Time from overcurrent FET shut off until FET turns back
tRETRY Overcurrent retry time 100 ms
on
Time from end of tRETRY until FLT deassertion if
tRECV Overcurrent recovery time 8 ms
overcurrent condition is removed
OVER VOLTAGE PROTECTION
tOVP_response OVP Response time – VBUS Measured from OVP Condition to FET turnoff 2 4 µs
OVP Response time – data
tOVP_response Measured from OVP Condition to FET turnoff 200 ns
switches
tOVP_
OVP FLT assertion time Measured from an OVP Condition to FLT assertion 14 µs
FLT_ASSERT
SHORT TO GROUND PROTECTION

Time from short condition until current falls below 120%
tSHRT Short to ground response time 2 4 µs
of ISHRT, CVBUS_CON = 0 µF
Short to ground FLT assertion Time from short condition until FLT is asserted,
tSHRT_FLTZ 20 µs
time CVBUS_CON = 0 µF
REVERSE SUPPLY DETECTION
tREV_SUPPLY_
Reverse supply blanking time Time from reverse current condition until FLT assertion 2 ms
BLANK

TPD3S716-Q1
6.9 Typical Characteristics
140 80
120 60
100
40
80
20
60
Voltage (V)
Voltage (V)
40 0
20 -20
0 -40
-20
-60
-40
VD- -80 VD-
-60 D-
D-
-80 -100
-10 0 10 20 30 40 50 60 70 80 90 100 110 -10 0 10 20 30 40 50 60 70 80 90 100 110
Time (ns) Time (ns) D002
D001
Figure 6-1. 8-kV IEC Contact Waveform Figure 6-2. –8-kV IEC Contact Waveform
1 8
VBUS_CON
0.75 7 /VEN
/FLT
0.5 6
Current (mA)
0.25 5
Voltage (V)
0 4
-0.25 3
-0.5 2
-0.75 VD+ 1
VD-
-1
0
-5 0 5 10 15 20 25
Voltage (V)
-15 -10 -5 0 5
D003 Time (ms) D004
D003
Figure 6-3. Data Line I-V Curve Figure 6-4. VBUS tON Time
100 6
5
80
Leakage Current (PA)
4
60
RON (:)
3
40
2
-40 C
20
1 25 C
Unpowered 85 C
Powered, Enabled 130 C
0 0
-40 -20 0 20 40 60 80 100 120 140 0 0.1 0.2 0.3 0.4
Temperature (qC) D007 Bias Voltage (V) D008
Figure 6-5. VD± Leakage Current at 18-V across Figure 6-6. Data Switch RON vs Bias Voltage
Temperature

TPD3S716-Q1
8 1600 6 1500
VBUS_CON VBUS_CON
7 IVBUS_CON 1400 IVBUS_CON
/FLT 5 /FLT 1250
6 1200
4 1000
Current (mA)
Current (mA)
5 1000
Voltage (V)
Voltage (V)
4 800 3 750
3 600
2 500
2 400
1 250
1 200
0 0 0 0
-4.8 -4.4 -4 -3.6 -3.2 -2.8 -2.4 -2 -1.6 -1.2 -0.8 -40 -20 0 20 40 60 80 100 120 140 160
Time (ms) D009
Time (ms) D010
Figure 6-7. Overcurrent tBLANK Response Figure 6-8. Overcurrent tBLANK_RETRY Response
Waveform Waveform
9.5 50 12.5
VBUS_CON VBUS_CON
Voltage (V) or Current (A) on VBUS_CON

8.5 IVBUS_CON 10
IVBUS_CON
Voltage (V) on VBUS_SYS and /FLT

40
7.5 VBUS_SYS VBUS_SYS
/FLT
Voltage (V) or Current (A)
6.5 /FLT 30 7.5

5.5
4.5 20 5
3.5
10 2.5
2.5
1.5 0 0
0.5
-10 -2.5
-0.5
-1.5 -20 -5
-2.5 -10 0 10 20 30 40
Time (Ps)
-8 -3 2 7 12 17 22 27 30 D012
Time (Ps) D011 Figure 6-10. VBUS Short-to-18 V Response
Figure 6-9. VBUS Short-to-Ground Response Waveform
Waveform
12.5 25
VD- VD-
10.5 IVD- IVD-
D- 20 D-
/FLT /FLT
8.5
15
6.5
10
4.5
5
2.5
0.5 0
-1.5 -5
-0.75 -0.25 0.25 0.75 -0.5 0 0.5 1
Time (Ps) D014 Time (Ps) D005
Figure 6-11. Data Switch Short-to-5 V Response Figure 6-12. Data Switch Short-to-18 V Response
Waveform Waveform

TPD3S716-Q1
29 12.5 0
VD-
IVD- -10
Voltage (V) or Current (A) on VD-
24 D- 10
Voltage (V) on D- and FLT

/FLT
-20
19 7.5
Crosstalk (dB)
-30
14 5
-40
9 2.5 -50
4 0 -60
-70 D- to VD+
-1 -2.5 D+ to VD-
-1 4 9 14 19 -80
Time (Ps) D013 0 1E+9 2E+9 3E+9
Figure 6-13. Data Switch Short-to-18 V Response Frequency (Hz) D017
Waveform (Long) Figure 6-14. Data Switch Crosstalk
Figure 6-15. USB2.0 Eye Diagram (no TPD3S716- Figure 6-16. USB2.0 Eye Diagram (with TPD3S716-
Q1) Q1)
0 0
-1
-3
Instertion Loss (dB)
Insertion Loss (dB)
-2
-3 -6
-4
-9
-5
-6 -12
1E+7 1E+8 1E+9 3E+9 1E+7 1E+8 1E+9 3E+9
Frequency (Hz) D015
Frequency (Hz) D016
Figure 6-17. Data Switch Differential Bandwidth Figure 6-18. Data Switch Single-Ended Bandwidth

TPD3S716-Q1
7 Parameter Measurement Information

5V
VBUS_SYS
VBUS_CON 100 µF
1 µF 10 NŸ 7V
STB Strike Points

100 V
X7R
FLT
VD± D±
10 nH 45 Ÿ
VD+ D+
USB2.0 10 nH
45 Ÿ
CMC
GND VEN
1-m Cable From GPIO
STB DEN
Strike IADJ From GPIO
DC Power
Output VIN 3.3 V
Supply RADJ
22 mF TPD3S716-Q1
35 V 1 µF
7V
STB Test Aparatus

Figure 7-1. Short-to-Battery System Test Setup
5V
VBUS_SYS
VBUS_CON 100 µF
1 µF 10 NŸ 7V
ESD Strike Points
100 V
X7R
FLT
VD± D±
10 nH 45 Ÿ
VD+ D+
USB2.0 10 nH
45 Ÿ
CMC
GND VEN
From GPIO
DEN
IADJ From GPIO
VIN 3.3 V
RADJ TPD3S716-Q1
1 µF
7V
Figure 7-2. ESD System Test Setup

TPD3S716-Q1
8 Detailed Description
8.1 Overview
The TPD3S716-Q1 provides a single-chip ESD protection and over voltage protection solution for automotive
USB interfaces. It offers short to battery protection up to 18 V and short to ground protection on VBUS_CON.
The TPD3S716-Q1 also provides a FLT pin that indicates to the system if a fault condition has occurred. The
TPD3S716-Q1 offers ESD clamps on the VBUS_CON, VD+, and VD– pins, therefore eliminating the need for
external TVS clamp circuits in the application.
The TPD3S716-Q1 has internal circuitry that controls the turnon of the internal nFET switches. An internal
oscillator controls the timers that enable the switches and resets the open-drain FLT output. If VBUS_CON and
VD+/VD– are less than VOVP, the switches are enabled. After an internal delay the charge-pump starts-up and
turns on the internal nFET switches through a soft start. At any time, if any of the external USB pins rise above
their respective VOVP thresholds, the nFET switches are turned OFF and the FLT pin is pulled LOW.
8.2 Functional Block Diagram
VBUS_CON VBUS_SYS
Short to
Ground - Undervoltage
ESD Detection Lockout
+
Clamp RADJ
Overcurrent IADJ
Detection
Over-
voltage Control Logic VEN
Protection FLT
DEN
VIN
VD+ D+
ESD
Clamps
VD± D±
8.3 Feature Description

8.3.1 AEC-Q100 Qualified
The TPD3S716-Q1 is an automotive qualified device according to the AEC-Q100 standards. The TPD3S716-Q1
is qualified to operate from –40 to +125°C ambient temperature.
8.3.2 Short-to-Battery and Short-to-Ground Protection on VBUS_CON
The VBUS_CON pin is protected against shorts to battery and shorts to ground.
If a voltage on VBUS_CON is detected as too low (below the VSHRT threshold) after the device is enabled, the
device enters short-circuit protection mode and asserts FLT. It sources the ISHRT current until it detects the
voltage rising above the VSHRT threshold, where it resumes standard operating mode and deasserts FLT.
If a voltage above the VOVP threshold is detected by the device, it shuts off all FETs and assert a fault on the FLT
pin. When the excessive voltage is removed, the device automatically re-enables and FLT deasserts.
8.3.3 Short-to-Battery and Short-to-VBUS Protection on VD+, VD–
The VD+ and VD– pins are protected against shorts to battery and shorts to bus. The OVP threshold on the VD+
and VD– pins is low enough that it protects against shorts to VBUS.

TPD3S716-Q1
When a voltage above the VOVP threshold is detected by the device, it shuts off all FETs and asserts a fault on
the FLT pin. When the excessive voltage is removed, the device automatically re-enables and FLT deasserts.
8.3.4 ESD Protection on VBUS_CON, VD+, VD–
The protected pins (VBUS_CON, VD+, VD–) are tested to pass the IEC 61000-4-2 ESD standard up to Level
4 ESD protection. Additionally, these pins are tested against ISO 10605 with the 330-pF, 330- Ω equivalent
network. This guarantees passing of at least ±8-kV contact discharge and ±15-kV air gap discharge according to
both standards. See Figure 7-2 for the test set-up used for testing IEC 61000-4-2 and ISO 10605.
8.3.5 Low RON nFET VBUS Switch
The VBUS switch has a low RON that provides minimal voltage droop from system to connector. Typical
resistance is 63 mΩ and is specified for 135 mΩ at 150°C junction temperature.
8.3.6 High Speed Data Switches
The D+ and D– switches have a very low capacitance and a high bandwidth (1-GHz typical), allowing for a clean
USB 2.0 eye diagram.
8.3.7 Adjustable Hiccup Current Limit up to 2.4-A
The VBUS path of this device has an integrated overcurrent protection circuit. The current limit threshold for the
overcurrent protection is adjustable via an external resistor RADJ to GND on the IADJ pin. Equation 1 to Equation
3 approximate the minimum, nominal, and maximum current limit values for TPD3S716-Q1 assuming a 1%
tolerant resistor:
ILIM(TYP) = 143 × RADJ (–0.983) (1)
ILIM(MIN) = 129 × RADJ (–0.981) – 0.02 (2)
ILIM(MAX) = 141.5 × RADJ (–0.962) + 0.015 (3)
where
• ILIM(TYP) is the nominal current limit value in (A)
• ILIM(MIN) is the minimum current limit value in (A)
• ILIM(MAX) is the maximum current limit value in (A)
• RADJ is the nominal resistor to GND on the IADJ pin in (Ω)
3
2.8 ILIM(MIN)
ILIM(TYP)
2.6 ILIM(MAX)
2.4
2.2
2
ILIM (A)
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
50 70 90 110 130 150 170 190 210 230 250 270
RADJ (k:) D009
Figure 8-1. TPD3S716-Q1 Current Limit Thresholds vs. RADJ
Equation 1, Equation 2 and Equation 3 are useful for approximating the current limit threshold of TPD3S716-Q1;
however, they do not constitute as part of TI's published device specifications for purposes of TI's product
warranty. For the officially tested current limit threshold values, see the Electrical Characteristics table.

TPD3S716-Q1
When the VBUS current exceeds the overcurrent threshold, the device goes into a fault state where it limits the
current to the overcurrent threshold value and asserts the FLT pin. After a short blanking time, the device cycles
on and off to try to check if the connected device is still in overcurrent.
8.3.8 Fast Over-Voltage Response Time
The over-voltage FETs are designed to have a fast turnoff time to protect the upstream SoC as quickly as
possible. Typical response time for complete turnoff is 2 µs for the VBUS path and 200 ns for the data path.
8.3.9 Independent VBUS and Data Enable Pins for Configuring both Host and Client/OTG Mode
The TPD3S716-Q1 has two enable inputs to turn on and off the device's internal FETs. The VEN pin disables
and enables the VBUS path. The DEN pin disables and enables the data path. Independent control of the VBUS
and data paths enables the TPD3S716-Q1 to be configured for both USB Host and Client/OTG mode. See Table
8-1.
8.3.10 Fault Output Signal
The TPD3S716-Q1 has a fault pin , FLT that indicates when there is any sort of fault condition because of an
OVP, OCP, short-circuit, reverse-current, or thermal shutdown event occurring.
8.3.11 Thermal Shutdown Feature
In the event that the device exceeds the maximum allowable junction temperature, the thermal shutdown circuit
disables the VBUS and data switches and assert the fault pin low.
8.3.12 16-Pin SSOP Package
The TPD3S716-Q1 is packaged in a standard 16-pin SSOP leaded package.
8.3.13 Reverse Current Detection
If VBUS_CON exceeds VBUS_SYS by a voltage greater than VREV_SUPPLY(RISING) for tREV_SUPPLY_BLANK, then
TPD3S716-Q1 detects this reverse current condition and asserts the fault pin. When VBUS_CON – VBUS_SYS
falls below VREV_SUPPLY(FALLING), the fault pin is be deasserted and TPD3S716-Q1 enters back into its normal
operating mode.

TPD3S716-Q1
8.4 Device Functional Modes

8.4.1 Normal Operation
The TPD3S716-Q1 operates in normal operation modes when enabled, both VBUS_SYS and VIN are above their
UVLO thresholds, and the device is not in any fault conditions. Table 8-1 shows the normal operating modes of
the TPD3S716-Q1.
Table 8-1. Device Normal Operating Mode Table
MODE VEN DEN VBUS PATH DATA PATH
USB Host 0 0 ON ON
Power Only 0 1 ON OFF
USB Client/OTG 1 0 OFF ON
Disabled 1 1 OFF OFF
8.4.2 Overvoltage Condition

When the VD+, VD–, or VBUS_CON pins exceed their OVP threshold, the device enters the overvoltage state. All
FETs are disabled and the FLT pin is asserted. When the protected pins drop below their OVP threshold, the
device automatically turns back on and deasserts the FLT pin. An overvoltage condition is only detected on an
enabled path. For example, if the data path is enabled and the VBUS path is disabled (USB Client/OTG mode),
if an overvoltage condition occurs on VBUS_CON, the fault pin is not be asserted. However, because the FETs of
disabled paths are already turned off, proper protection from overvoltage conditions are still guaranteed by the
device on disabled paths.
8.4.3 Overcurrent Condition
When the current through the VBUS path exceeds the ILIM current threshold, the device enters into the
overcurrent state. The TPD3S716-Q1 limits current to the ILIM threshold by dropping voltage across the VBUS
FET to maintain constant current. When it continues to sense an overcurrent condition for the blanking time
(tBLANK), the device disables itself for the retry time (tRETRY) and then retry automatically for the retry time
(tBLANK_RETRY). In the event that the current is below the overcurrent threshold, the device deasserts fault and
resumes normal operation.
8.4.4 Short-Circuit Condition
If the voltage on the VBUS_CON side is pulled below the VSHRT threshold while the device is enabled, the
TPD3S716-Q1 enters the short-circuit mode. It sources a constant current of ISHRT until it rises above the VSHRT
threshold. When that occurs, the device automatically re-enters normal operation and deasserts the fault pin.

TPD3S716-Q1
8.4.5 Device Logic Table

Table 8-2 shows the TPD3S716-Q1 logic table.
Table 8-2. TPD3S716-Q1 Logic Table
VBUS_SYS,
Mode VEN DEN VBUS_CON VDx IVBUS TJ FLT VBUS PATH DATA PATH
VIN
Unpowered X X X X None < UVLO X H OFF OFF
Disabled H H X X None > UVLO < TSD H OFF OFF
< OVP & <
VBUS_SYS +
Host L L < OVP < OCP > UVLO < TSD H ON ON
200 mV(typical) & >
VSHRT
Client/OTG H L X < OVP None > UVLO < TSD H OFF ON
< OVP & <
VBUS_SYS +
Power Only L H X < OCP > UVLO < TSD H ON OFF
200 mV(typical) & >
VSHRT
Thermal
X X X X None > UVLO > TSD L OFF OFF
Shutdown
Host: VBUS
L L > OVP X None > UVLO < TSD L OFF OFF
OVP Fault
Host: Data
L L X > OVP None > UVLO < TSD L OFF OFF
OVP Fault
< OVP & <
Host: OCP VBUS_SYS + CURRENT LIMITED,
L L X > OCP > UVLO < TSD L AUTO-RETRY
Fault 200 mV(typical) & > AUTO-RETRY
VSHRT
Host: Short- CURRENT LIMITED
L L < VSHRT X X > UVLO < TSD L OFF
Circuit Fault 250 mA (typical)
< OVP & >
Host: RCP
L L VBUS_SYS + X X > UVLO < TSD L ON ON
Fault
200 mV (typical)
OTG: Data
H L X > OVP None > UVLO < TSD L OFF OFF
OVP Fault
Power Only:
VBUS OVP L H > OVP X None > UVLO < TSD L OFF OFF
Fault
Power Only: CURRENT LIMITED,
L H X X > OCP > UVLO < TSD L OFF
OCP Fault AUTO-RETRY
Power Only:
CURRENT LIMITED
Short-Circuit L H < VSHRT X X > UVLO < TSD L OFF
250 mA (typical)
Fault
< OVP & >
Power Only:
L H VBUS_SYS + X X > UVLO < TSD L ON OFF
RCP Fault
200 mV (typical)

TPD3S716-Q1
9 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information

The TPD3S716-Q1 offers fully featured automotive USB2.0 protection including short-to-battery, overcurrent,
and ESD protection. Care must be taken during the implementation to make sure the device provides adequate
protection to the system.
9.2 Typical Application
Figure 9-1 shows a fully featured USB2.0 high speed port, with an 18-V short-to-battery requirement on the
connector side.
5V
TPD3S716-Q1
VBUS_SYS
VBUS VBUS_CON 100 µF
1 µF 10 NŸ 7V
100 V
X7R
FLT
USB
D± VDt Dt Transceiver
10 nH
D+ VD+ D+
USB2.0 10 nH
CMC
GND VEN From Processor
GND
DEN From Processor
IADJ
VIN 3.3 V
RADJ
1 µF
7V
Figure 9-1. Typical Application Configuration for TPD3S716-Q1
9.2.1 Design Requirements

Table 9-1 shows the TPD3S716-Q1 input parameters for this application example.
Table 9-1. Design Parameters
DESIGN PARAMETER EXAMPLE VALUE
Short-to-battery tolerance on VD+, VD–, VBUS_CON 18 V
Max current in normal operation on VBUS 1.5 A
Current Limit Setting on VBUS 1.505 A (minimum)
Maximum Ambient Temperature Requirement 105°C
USB Data Rate 480 Mbps

TPD3S716-Q1
9.2.2 Detailed Design Procedure

The following parameters must be known to the designer to begin the design process:
• Short-to-battery tolerance on connector pins
• Maximum current in normal operation on VBUS
• Maximum operating ambient temperature
• USB Data Rate
9.2.2.1 Short-to-Battery Tolerance
The TPD3S716-Q1 is capable of handling up to 18 V DC on the VD+, VD–, and VBUS_CON pins. In the event of
a short-to-battery on VBUS_CON, significant ringing would be expected because of the hot plug-like nature of the
short-to-battery event. In typical ceramic capacitor configurations, a standard RLC response is expected which
results in a ringing of nearly two times the applied DC voltage. The TPD3S716-Q1 is capable of withstanding the
transient ringing from hot plug-like events, assuming some precautions are taken.
Careful capacitor selection on the VBUS_CON pin must be observed. A capacitor with a low derating percentage
under the applied voltages must be used to prevent excess ringing. In the example, a 1-µF, 100-V tolerant
ceramic X7R capacitor is used. It is best practice to carefully select the capacitors used in this circuit to prevent
derating-based voltage spikes under hot plug events. See Figure 9-4 and Figure 9-5 to compare ringing of a
50-V capacitor to a 100-V capacitor. Figure 9-6 shows the 100-V capacitor with the TPD3S716-Q1 installed.
Another alternative to a high rated ceramic capacitor is to implement either a standard R-C snubber circuit, or a
small external TVS diode. Depending on the short-to-battery tolerance needed, no special precautions may be
needed.
9.2.2.2 Maximum Current on VBUS
The TPD3S716-Q1 is capable of operating up to 2.4 A maximum DC current. In this example, the maximum
current for USB2.0 BC1.2 of 1.5 A has been chosen.
9.2.2.3 Power Dissipation and Junction Temperature
This section demonstrates how to analyze the power dissipation and junction temperature of the TPD3S716-Q1
to validate that the application requirements of an IVBUS operating current level of 1.5 A and a maximum
operating ambient temperature of 105 °C can be met.
It is good design practice to estimate power dissipation and maximum expected junction temperature of
TPD3S716-Q1. This is important to insure the device does not go into thermal shutdown in normal operation and
that the long term reliability of the device is maintained. Using Equation 4 to Equation 6, the system designer can
control choices of the device's proximity to other power dissipating devices and the design of the printed circuit
board (PCB). These have a direct influence on maximum junction temperature. Other factors, such as airflow
and maximum ambient temperature, are often determined by system considerations. It is important to remember
that these calculations do not include the effects of adjacent heat sources, and enhanced or restricted air flow.
Addition of extra PCB copper area around these devices is recommended to reduce the thermal impedance and
maintain the junction temperature as low as practical.
For TPD3S716-Q1, the operating junction temperature must be kept below 150°C in order to prevent the device
from going into thermal shutdown. Equation 4 is used to calculate the junction temperature of the device:
TJ = TA + [(IOUT 2 × RON) × RθJA] (4)
where
• IOUT = Rated OUT pin current (A)
• RON = Power path on-resistance at an assumed TJ (Ω)
• TA = Maximum ambient temperature (°C)
• TJ = Maximum junction temperature (°C)
• RθJA = Thermal resistance (°C/W)

TPD3S716-Q1
This application example requires an IVBUS operating current level of 1.5 A. TPD3S716-Q1 has maximum
junction temperature derating requirements depending on the maximum operating current of the device
according to Equation 5:
TJ(MAX) = –15.6 × (IVBUS(MAX OPERATING)) + 161.5 (°C) (5)
where
• TJ(MAX) = Maximum allowed junction temperature (°C)
• IVBUS(MAX OPERATING) = Maximum IVBUS operating current (A)
See Figure 9-7 for a plot of the reliability curve equation. Using this equation, 138.1°C is the maximum allowed
junction temperature in this application.
This example requires a maximum operating ambient temperature of 105°C. To determine if this can be
supported using Equation 4, the maximum VBUS path RON must be determined. Equation 6 calculates the
maximum VBUS path RON possible for TPD3S716-Q1 for a given junction temperature:
RON(MAX) = (TJ + 183.15) / 2726.7 (Ω) (6)
where
• RON(MAX) = Maximum VBUS RON at a given junction temperature (Ω)
• TJ = Device junction temperature (°C)
See Figure 9-8 for a plot of the maximum VBUS path RON vs. Junction Temperature curve. Using the above
equation, the maximum VBUS RON possible for TPD3S716-Q1 at 138.1°C is RON(MAX) = 0.118 Ω.
Using the calculated parameters for this example and the standard datasheet RθJA for TPD3S716-Q1, the
maximum operating ambient temperature possible in this example is TA = 111°C. Because this is greater than
the application requirement of 105°C, TPD3S716-Q1 can safely be operated at 1.5 A with RθJA = 98.8 (°C/W).
If the resulting ambient temperature in the above calculations resulted in a TA < 105 °C, methods for improving
RθJA would need to be taken. See the Layout Optimized for Thermal Performance section for guidelines on
improving RθJA for TPD3S716-Q1. The example given in the Layout Optimized for Thermal Performance yields
an RθJA = 57 (°C/W). Excellent thermal performance of TPD3S716-Q1 can be achieved with the proper PCB
layout.
9.2.2.4 USB Data Rate
The TPD3S716-Q1 is capable of operating at the maximum USB2.0 High Speed data rate of 480-Mbps because
of the high data switch bandwidth of 1-GHz (typical). In this design example the maximum data rate of 480-Mbps
has been chosen.

TPD3S716-Q1
9.2.3 Application Curves
Figure 9-2. USB2.0 Eye Diagram (Board only, Figure 9-3. USB2.0 Eye Diagram (System from
Through Path) Typical Application Schematic)
60 40
Voltage Voltage
50 Current Current
30
40
20
30
20 10
10
0
0
-10
-10
-20 -20
-10 0 10 20 30 40 50 60 70 -10 0 10 20 30 40 50 60 70
Time (Ps) D018
Time (Ps) D018
Figure 9-4. 50-V, 1-µF X7R Ceramic Shorted to 18-V Figure 9-5. 100-V, 1-µF X7R Ceramic Shorted to 18
(Not Recommended) V
35 165
Voltage
Maximum Junction Temperature (qC)
30 Current 160
25 155
20
150
15
145
10
140
5
135
0
130
-5
-10 125
-15 120
-20 -10 0 10 20 30 40 50 60 70 80 0 0.4 0.8 1.2 1.6 2 2.4
Time (Ps) IVBUS Operating Maximum (A) D006
D018
Figure 9-6. TPD3S716-Q1 and 100-V, 1-µF X7R Figure 9-7. TPD3S716-Q1 IVBUS Temperature
Shorted to 18 V (Powered Off) Derating Curve

TPD3S716-Q1
130
120
110
VBUS RON (m:) Maximum

100
90
80
70
60
50
40
-40 -20 0 20 40 60 80 100 120 140
Temperature (qC) D006
Figure 9-8. TPD3S716-Q1 Maximum VBUS RON vs. Junction Temperature

TPD3S716-Q1
10 Power Supply Recommendations

10.1 VBUS Path
The VBUS_SYS pins provide power to the chip and supply current through the load switch to VBUS_CON. A 100-µF
bulk capacitor is recommended on VBUS_SYS to supply the USB port and maintain compliance. A 1-µF capacitor
is recommended on the VBUS_CON pin with adequate voltage rating to tolerate short-to-battery conditions. A
supply voltage above the UVLO threshold for VBUS_SYS must be supplied for the device to power on.
10.2 VIN Pin
The VIN pin provides a voltage reference for the data switch OVP level as well as a bypass for ESD clamping. A
1-µF capacitor must be placed as close to the pin as possible and the supply must be set to be above the UVLO
threshold for VIN.
11 Layout
11.1 Layout Guidelines
Proper routing and placement maintains signal integrity for high-speed signals. The following guidelines apply to
the TPD3S716-Q1:
• Place the bypass capacitors as close as possible to the VIN, VBUS_SYS, and VBUS_CON pins. Capacitors
must be attached to a solid ground. This minimizes voltage disturbances during transient events such as
short-to-battery, ESD, or overcurrent conditions.
• High speed traces (data switch path) must be routed as straight as possible and any sharp bends must be
minimized.
Standard ESD recommendations apply to the VD+, VD–, and VBUS_CON pins as well:
• The optimum placement is as close to the connector as possible.
– EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces,
resulting in early system failures.
– The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away
from the protected traces which are between the TVS and the connector.
• Route the protected traces as straight as possible.
• Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded
corners with the largest radii possible.
– Electric fields tend to build up on corners, increasing EMI coupling.
11.2 Layout Example
Figure 11-1 shows a full layout for a standard USB2.0 port. A common mode choke and inductors are used on
the high speed data lines, and the requisite bypassing caps are placed on VBUS_CON, VBUS_SYS, and VIN.

TPD3S716-Q1
VBUS
N.C. IADJ
VBUS_CON VBUS_SYS
VBUS_CON VBUS_SYS
D-
GND GND
TPD3S716-Q1
VD- D- To Transceiver
VD+ D+ To Transceiver
D+ To Processor VEN FLT To Transceiver
To Processor DEN VIN
Legend
GND
Pin to GND
VIA to 3.3V Plane
USB2.0 Connector VIA to 5V Plane
VIA to GND Plane
Figure 11-1. Typical Layout Example for TPD3S716-Q1
11.3 Layout Optimized for Thermal Performance

Figure 11-2 and Figure 11-3 show images from a real PCB design optimized for the best thermal performance
for TPD3S716-Q1. This PCB layout has 6 layers (2 signal and 4 plane layers). The 2 signal layers are the
outer layers of the PCB and constructed with 2-oz copper, and the 4 internal plane layers are constructed with
1-oz copper. Using this PCB layout yielded an RθJA(CUSTOM) = 57 (°C/W). The images contain rough dimensions
of the copper traces and pours used around the device. One key strategy to optimize thermal performance of
the device is to maximize the area of the copper pours and traces used to route the device power, GND, and
signal pins when possible. Another key strategy is to maximize the copper weight of the PCB metal layers. This
example demonstrates that excellent thermal performance can be achieved with TPD3S716-Q1 with the proper
PCB layout.

TPD3S716-Q1
Figure 11-2. Thermally Optimized PCB Layout Top Layer
Figure 11-3. Thermally Optimized PCB Layout Bottom Layer

TPD3S716-Q1
12 Device and Documentation Support

12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
TPD3S716-Q1 Evaluation Module, SLVUAL9
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
TPD3S716QDBQRQ1 ACTIVE SSOP DBQ 16 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 RJ716Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Feb-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPD3S716QDBQRQ1 SSOP DBQ 16 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Feb-2020
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPD3S716QDBQRQ1 SSOP DBQ 16 2500 367.0 367.0 35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBQ0016A SCALE 2.800
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE
SEATING PLANE
.228-.244 TYP
[5.80-6.19] .004 [0.1] C
A PIN 1 ID AREA
14X .0250
[0.635]
16
1
2X
.189-.197
[4.81-5.00] .175
NOTE 3 [4.45]
8
9
16X .008-.012
B .150-.157 [0.21-0.30] .069 MAX
[3.81-3.98] [1.75]
NOTE 4 .007 [0.17] C A B
.005-.010 TYP
[0.13-0.25]
SEE DETAIL A
.010
[0.25]
GAGE PLANE
.004-.010
0 -8 [0.11-0.25]
.016-.035
[0.41-0.88] DETAIL A
(.041 ) TYPICAL
[1.04]
4214846/A 03/2014
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 inch, per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MO-137, variation AB.
www.ti.com
EXAMPLE BOARD LAYOUT
DBQ0016A SSOP - 1.75 mm max height
16X (.063)
[1.6] SEE
SYMM
DETAILS
1
16
16X (.016 )
[0.41]
14X (.0250 )
[0.635] 8 9
(.213)
[5.4]
LAND PATTERN EXAMPLE

SCALE:8X
SOLDER MASK SOLDER MASK

METAL METAL
OPENING OPENING
.002 MAX .002 MIN

[0.05] [0.05]
ALL AROUND ALL AROUND
NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
SOLDER MASK DETAILS
4214846/A 03/2014
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBQ0016A SSOP - 1.75 mm max height
16X (.063)
[1.6]
SYMM
1
16
16X (.016 )
[0.41]
SYMM
14X (.0250 )
[0.635] 8 9
(.213)
[5.4]
SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:8X
4214846/A 03/2014
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

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SLVSDH9D – MARCH 2016 – REVISED AUGUST 2020

Copyright © 2016, Texas Instruments Incorporated

Typical Application Schematic

Changes from Revision B (April 2016) to Revision C (June 2016) Page

Changes from Revision A (April 2016) to Revision B (April 2016) Page

Changes from Revision * (March 2016) to Revision A (April 2016) Page

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Product Folder Links: TPD3S716-Q1

5 Pin Configuration and Functions

Figure 5-1. DBQ Package 16-Pin SSOP Top View

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 3

6.2 ESD Ratings—AEC Specification

6.3 ESD Ratings—IEC Specification

IEC 61000-4-2, VBUS_CON, Contact discharge(1) ±8000

6.4 ESD Ratings—ISO Specification

ISO 10605 (330 pF, 330 Ω), Contact discharge(1) ±8000

6.5 Recommended Operating Conditions

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6.5 Recommended Operating Conditions (continued)

6.6 Thermal Information

6.7 Electrical Characteristics

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 5

6.7 Electrical Characteristics (continued)

6 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: TPD3S716-Q1

6.7 Electrical Characteristics (continued)

6.8 Timing Characteristics

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 7

SHORT TO GROUND PROTECTION

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6.9 Typical Characteristics

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 9

Voltage (V) or Current (A) on VBUS_CON

Voltage (V) on VBUS_SYS and /FLT

6.5 /FLT 30 7.5

Voltage (V) or Current (A)

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Voltage (V) on D- and FLT

Waveform (Long) Figure 6-14. Data Switch Crosstalk

Insertion Loss (dB)

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 11

7 Parameter Measurement Information

STB Strike Points

STB Test Aparatus

Figure 7-1. Short-to-Battery System Test Setup

Copyright © 2016, Texas Instruments Incorporated

Figure 7-2. ESD System Test Setup

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Copyright © 2016, Texas Instruments Incorporated

8.3 Feature Description

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 13

ILIM(TYP) = 143 × RADJ (–0.983) (1)

ILIM(MIN) = 129 × RADJ (–0.981) – 0.02 (2)

ILIM(MAX) = 141.5 × RADJ (–0.962) + 0.015 (3)