MOTOROLA Order this document

SEMICONDUCTOR TECHNICAL DATA by MCM56824A/D

MCM56824A
DSPRAM
8K x 24 Bit Fast Static RAM
The MCM56824A is a 196,608 bit static random access memory organized as
8,192 words of 24 bits. The device integrates an 8K x 24 SRAM core with multiple
FN PACKAGE
chip enable inputs, output enable, and an externally controlled single address pin
52–LEAD PLCC
multiplexer. These functions allow for direct connection to the Motorola
CASE 778–02
DSP56001 Digital Signal Processor and provide a very efficient means for imple-
mentation of a reduced parts count system requiring no additional interface logic.
The availability of multiple chip enable (E1 and E2) and output enable (G) in-
puts provides for greater system flexibility when multiple devices are used. With
either chip enable input unasserted, the device will enter standby mode, useful 9 x 10 GRID
in low–power applications. A single on–chip multiplexer selects A12 or X/Y as the 86 BUMP PBGA
highest order address input depending upon the state of the V/S control input. CASE 896A–01
This feature allows one physical static RAM component to efficiently store pro-
gram and vector or scalar operands by dynamically re–partitioning the RAM
array. Typical applications will logically map vector operands into upper memory PIN ASSIGNMENTS
PLCC
with scalar operands being stored in lower memory. By connecting

V CC
A10

A12
DSP56001address A15 to the VECTOR/SCALAR (V/S) MUX control

A11

X/Y
V/S
NC

A0
A1
A2
A3
A4
A5
pin, such partitioning can occur with no additional components. This al-
lows efficient utilization of the RAM resource irrespective of operand 7 6 5 4 3 2 1 52 51 50 49 48 47
type. See application diagrams at the end of this document for addition- DQ0 8 46 DQ23
DQ1 9 45 DQ22
al information.
DQ2 10 44 DQ21
Multiple power and ground pins have been utilized to minimize effects
VSS 11 43 VSS
induced by output noise.
DQ3 12 42 DQ20
The MCM56824A is available in a 52 pin plastic leaded chip–carrier 41
DQ4 13 DQ19
(PLCC) and a 9 x 10 grid, 86 bump surface mount PBGA. DQ5 14 40 DQ18
• Single 5 V ± 10% Power Supply DQ6 15 39 DQ17
• Fast Access and Cycle Times: 20/25/35 ns Max DQ7 16 38 DQ16
DQ8 17 37 DQ15
• Fully Static Read and Write Operations
VSS 18 36 VSS
• Equal Address and Chip Enable Access Times DQ9 19 35 DQ14
• Single Bit On–Chip Address Multiplexer DQ10 20 21 22 23 24 25 26 27 28 29 30 31 32 3334 DQ13
• Active High and Active Low Chip Enable Inputs
VCC

NC
A9
A8
A7
A6

VSS
E1
E2
W
G

DQ12
•
DQ11

Output Enable Controlled Three State Outputs

• High Board Density PLCC Package
• Low Power Standby Mode
VIEW OF PBGA PACKAGE BOTTOM
• Fully TTL Compatible 10 9 8 7 6 5 4 3 2 1

PIN NAMES A
D13 VSS D16 D17 D18 D20 D21 D23
A0 – A11 . . . . . . . . . . . . . . . Address Inputs B
A12, X/Y . . . . . . . . . . Multiplexed Address W D12 D14 D15 D19 VSS D22 A5 A4
V/S . . . . . . . . . Address Multiplexer Control C
E1 E2 A3 A2
W . . . . . . . . . . . . . . . . . . . . . . . Write Enable
E1, E2 . . . . . . . . . . . . . . . . . . . Chip Enable D
VSS VSS A1 A0
G . . . . . . . . . . . . . . . . . . . . . . Output Enable
E
DQ0 – DQ23 . . . . . . . . . . Data Input/Output VCC VCC
VCC . . . . . . . . . . . . . . . +5 V Power Supply F
VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground G A6 V/S NC
NC . . . . . . . . . . . . . . . . . . . . No Connection G
A7 A8 A12 X/Y
For proper operation of the device, all VSS H
pins must be connected to ground. A9 D11 D9 D8 D4 VSS D1 A10 A11
J
D10 VSS D7 D6 D5 D3 D2 D0
DSPRAM is a trademark of Motorola, Inc.
Not to Scale
REV 2
4/95

 Motorola, Inc. 1995

MOTOROLA FAST SRAM MCM56824A
1
 BLOCK DIAGRAM
V/S
A12
X/Y 1
Q
A12 0 VCC
2 TO 1 MUX
A0 VSS
•
• MEMORY ARRAY
• ROW •
DECODER •
A5 •
512 ROWS x
384 COLUMNS
A10

A11

•••

DQ0
• INPUT • •
• DATA • COLUMN I/O •
• • •
CONTROL
DQ23
E1
COLUMN DECODER
E2
•••
W
G

A6 A9
(LSB)
(MSB)

TRUTH TABLE
Supply I/O
E1 E2 G W V/S Mode Current Status
H X X X X Not Selected ISB High–Z
X L X X X Not Selected ISB High–Z
L H H H X Output Disable ICC High–Z
L H L H H Read Using X/Y ICC Data Out
L H L H L Read Using A12 ICC Data Out
L H X L H Write Using X/Y ICC Data In
L H X L L Write Using A12 ICC Data In
NOTE: X=don’t care.

ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS = 0 V)

Rating Symbol Value Unit This device contains circuitry to protect
against damage due to high static voltages
Power Supply Voltage VCC – 0.5 to + 7.0 V
or electric fields; however, it is advised that
Voltage Relative to VSS for Any Pin Vin, Vout – 0.5 to VCC + 0.5 V normal precautions be taken to avoid appli-
Except VCC cation of any voltage higher than maximum
rated voltages to this high–impedance
Output Current (per I/O) Iout ± 20 mA
circuit.
Power Dissipation PD 1.75 W This CMOS memory circuit has been de-
signed to meet the dc and ac specifications
Temperature Under Bias Tbias – 10 to + 85 °C
shown in the tables, after thermal equi-
Operating Temperature TA 0 to + 70 °C librium has been established. The circuit is
Storage Temperature Tstg – 55 to + 125 °C assumed to be in a test socket or mounted
on a printed circuit board with at least 300
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are LFPM of transverse air flow being
exceeded. Functional operation should be restricted to RECOMMENDED OPER- maintained.
ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.

MCM56824A MOTOROLA FAST SRAM

2
 DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS (Voltages Referenced to VSS = 0 V)

Parameter Symbol Min Typ Max Unit
Supply Voltage (Operating Voltage Range) VCC 4.5 5.0 5.5 V
Input High Voltage VIH 2.2 — VCC + 0.3 V
Input Low Voltage VIL – 0.5* — 0.8 V
* VIL (min) = – 3.0 V ac (pulse width ≤ 20 ns)

DC CHARACTERISTICS
Parameter Symbol Min Max Unit
Input Leakage Current (All Inputs, Vin = 0 to VCC) Ilkg(i) — ± 1.0 µA
Output Leakage Current (G = VIH, E1 = VIH, E2 = VIL, Vout = 0 to VCC) Ilkg(O) — ± 1.0 µA
AC Supply Current (G = VIH, E1 = VIL, E2 = VIH, Iout = 0 mA, ICCA mA
All Other Inputs ≥ VIL = 0.0 V and VIH ≥ 3.0 V) MCM56824A–20 Cycle Time: ≥ 20 ns — 260
MCM56824A–25 Cycle Time: ≥ 25 ns — 220
MCM56824A–35 Cycle Time: ≥ 35 ns — 180
Standby Current (E1 = VIH, E2 = VIL, All Inputs = VIL or VIH) ISB1 — 15 mA
CMOS Standby Current (E1 ≥ VCC – 0.2 V, E2 ≤ 0.2 V, All Inputs ≥ VCC – 0.2 V or ≤ 0.2 V) ISB2 — 10 mA
Output Low Voltage (IOL = + 8.0 mA) VOL — 0.4 V
Output High Voltage (IOH = – 4.0 mA) VOH 2.4 — V

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)
Parameter Symbol Typ Max Unit
Input Capacitance All Pins Except DQ0 – DQ23 Cin 4 6 pF
Input/Output Capacitance DQ0 – DQ23 Cout 6 8 pF

+5V

480 Ω
RL = 50 Ω
OUTPUT OUTPUT

Z0 = 50 Ω 255 Ω 5 pF

VL = 1.5 V

(a) (b)

Figure 1. AC Test Loads

MOTOROLA FAST SRAM MCM56824A

3
 AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Output Load . . . . . . . . . . . . . See Figure 1a Unless Otherwise Noted
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns

READ CYCLE TIMING (See Notes 1, 2, and 3)

MCM56824A–20 MCM56824A–25 MCM56824A–35
Parameter Symbol Min Max Min Max Min Max Unit Notes
Read Cycle Time tAVAV 20 — 25 — 35 — ns
Address Access Time tAVQV — 20 — 25 — 35 ns
MUX Control Valid to Output Valid tVSVQV — 20 — 25 — 35 ns
Chip Enable to Output Valid tE1LQV — 20 — 25 — 35 ns 4
tE2HQV
Output Enable to Output Valid tGLQV — 8 — 10 — 15 ns
Output Active from Chip Enable tE1LQX 2 — 2 — 0 — ns 4, 5
tE2HQX
Output Active from Output Enable tGLQX 0 — 0 — 0 — ns 5
Output Hold from Address Change tAXQX 4 — 5 — 5 — ns
Output Hold from MUX Control Change tVSXQX 4 — 5 — 5 — ns
Chip Enable to Output High–Z tE1HQZ 0 10 0 15 0 15 ns 4, 5
tE2LQZ
Output Enable High to Output High–Z tGHQZ 0 8 0 15 0 15 ns 5
NOTES:
1. A read cycle is defined by W high.
2. All read cycle timings are referenced from the last valid address or vector/scalar transition to the first address or vector/scalar transition.
3. Addresses valid prior to or coincident with E1 going low or E2 going high.
4. E1 in the timing diagrams represents both E1 and E2 with E1 asserted low and E2 asserted high.
5. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1b. This parameter is sampled and not 100% tested. At any
given voltage and temperature, tE1HQZ max is less than tE1LQX min, tE2LQZ max is less than tE2HQX min, and tGHQZ max is less than
tGLQX min for a given device and from device to device.

READ CYCLE

tAVAV

A (ADDRESS)

tAVQV tAXQX

V/S (MUX CONTROL)

tVSVQV tVSXQX

E1 (CHIP ENABLE)

tE1LQV tE1HQZ

tGLQV

G (OUTPUT ENABLE)

tGLQX tGHQZ
HIGH–Z HIGH–Z
Q (DATA OUT) DATA VALID
tE1LQX

MCM56824A MOTOROLA FAST SRAM

4
WRITE CYCLE TIMING (Write Enable Initiated, See Note 1)
MCM56824A–20 MCM56824A–25 MCM56824A–35
Parameter Symbol Min Max Min Max Min Max Unit Notes
Write Cycle Time tAVAV 20 — 25 — 35 — ns
Address Setup Time tAVWL 0 — 0 — 0 — ns 2
MUX Control Setup Time tVSVWL 0 — 0 — 0 — ns
Address Valid to End of Write tAVWH 15 — 20 — 30 — ns
MUX Control Valid to End of Write tVSVWH 15 — 20 — 30 — ns
Write Pulse Width tWLWH 15 — 15 — 20 — ns 3
Write Enable to Chip Enable Disable tWLE1H 15 — 15 — 20 — ns 3, 4
tWLE2L
Chip Enable to End of Write tE1LWH 15 — 15 — 20 — ns 3, 4
tE2HWH
Data Valid to End of Write tDVWH 8 — 10 — 15 — ns
Data Hold Time tWHDX 0 — 0 — 0 — ns 5
Write Recovery Time tWHAX 0 — 0 — 0 — ns 2
MUX Control Recovery Time tWHVSX 0 — 0 — 0 — ns
Write High to Output Low–Z tWHQX 4 — 5 — 5 — ns 6
Write Low to Output High–Z tWLQZ 0 15 0 15 0 15 ns 6
NOTES:
1. A write cycle starts at the latest transition of E1 low, W low, or E2 high. A write cycle ends at the earliest transition of E1 high, W high, or E2
low.
2. Write must be high for all address transitions.
3. If W goes low coincident with or prior to E1 low or E2 high the outputs will remain in a high–impedance state.
4. E1 in the timing diagrams represents both E1 and E2 with E1 asserted low and E2 asserted high.
5. During this time the output pins may be in the output state. Signals of opposite phase must not be applied to the outputs at this time.
6. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1b. This parameter is sampled and not 100% tested. At any
given voltage and temperature, tE1HQZ max is less than tE1LQX min, tE2LQZ max is less than tE2HQX min, and tGHQZ max is less than
tGLQX min for a given device and from device to device.

WE INITIATED WRITE CYCLE

tAVAV

A (ADDRESS)

tAVWH tWHAX

V/S (MUX CONTROL)

tVSVWH tWHVSX
tE1LWH
E1 (CHIP ENABLE)

tVSVWL tWLWH

W (WRITE ENABLE)
tAVWL
tDVWH tWHDX

D (DATA IN) VALID DATA IN

tWLQZ tWHQX

HIGH–Z HIGH–Z
Q (DATA OUT)

tWLE1H

MOTOROLA FAST SRAM MCM56824A

5
WRITE CYCLE TIMING (Chip Enable Initiated, See Note 1)
MCM56824A–20 MCM56824A–25 MCM56824A–35
Parameter Symbol Min Max Min Max Min Max Unit Notes
Write Cycle Time tAVAV 20 — 25 — 35 — ns

Address Setup Time tAVE1L 0 — 0 — 0 — ns 2

tAVE2H

MUX Control Setup Time tVSVE1L 0 — 0 — 0 — ns 2

tVSVE2H

Address Valid to End of Write tAVE1H 15 — 20 — 30 — ns 2

tAVE2L

MUX Control Valid to End of Write tVSVE1H 15 — 20 — 30 — ns 2

tVSVE2L

Chip Enable to End of Write tE1LE1H 12 — 15 — 20 — ns 2, 3

tE2HE2L

Data Valid to End of Write tDVE1H 8 — 10 — 15 — ns 2

tDVE2L

Data Hold Time tE1HDX 0 — 0 — 0 — ns 2, 4

tE2LDX

Write Recovery Time tE1HAX 0 — 0 — 0 — ns 2

tE2LAX

MUX Control Recovery Time tE1HVSX 0 — 0 — 0 — ns 2

tE2LVSX
NOTES:
1. A write cycle starts at the latest transition of E1 low, W low, or E2 high. A write cycle ends at the earliest transition of E1 high, W high, or E2
low.
2. E1 in the timing diagrams represents both E1 and E2 with E1 asserted low and E2 asserted high.
3. If W goes low coincident with or prior to E1 low or E2 high the outputs will remain in a high–impedance state.
4. During this time the output pins may be in the output state. Signals of opposite phase must not be applied to the outputs at this time.

E1 OR E2 INITIATED WRITE CYCLE

tAVAV

A (ADDRESS)

tAVE1H tE1HAX

V/S (MUX CONTROL)

tVSVE1H tE1HVSX
tE1LE1H
E1 (CHIP ENABLE)
tAVE1L
tVSVE1L
W (WRITE ENABLE)

tDVE1H tE1HDX

D (DATA IN) DATA VALID

Q (DATA OUT) HIGH–Z

MCM56824A MOTOROLA FAST SRAM

6
 DSPRAM Multiplexed Vector/Scalar Address Maps 8K x 24 DSPRAM Used in Typical Application
DSP56001 MCM56824A DSP56001 MCM56824A
D0 – D23 D0 – D23

A0 – A11 A0 – A11 A0 – A11 A0 – A11

A12 RAM A12
MUX
X/Y A12 A12 MEMORY
A15 V/S MANAGEMENT
V/S X/Y PINS
X/Y

WR W

4K x 24
“X” OPERANDS
PROGRAM 8K x 24
MEMORY “X” OPERANDS
HIGH
4K x 24
“Y” OPERANDS
PROGRAM
MEMORY PROGRAM
LOW MEMORY

V/S = “1” V/S = “0”

ORDERING INFORMATION
(Order by Full Part Number)

MCM 56824A XX XX XX
Motorola Memory Prefix
Shipping Method (R2 = Tape and Reel, Blank = rails)
Part Number
Speed (20 = 20 ns, 25 = 25 ns, 35 = 35 ns)
Package (FN = PLCC, ZP = PBGA)

Full Part Numbers — MCM56824AFN20 MCM56824AFN25 MCM56824AFN35

MCM56824AZP20 MCM56824AZP25 MCM56824AZP35
MCM56824AZP20R2 MCM56824AZP25R2 MCM56824AZP35R2

MOTOROLA FAST SRAM MCM56824A

7
 PACKAGE DIMENSIONS
ZP PACKAGE
9 x 10 PBGA
CASE 896A–01

0.20 (0.008)
B -T-
-B- 10 9 8 7 6 5 4 3 2 1
NOTES:
A 1. DIMENSIONING AND TOLERANCING
B
G PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
C
MILLIMETERS INCHES
D DIM MIN MAX MIN MAX
A 16.16 16.36 0.637 0.644
A N E
B 17.68 17.88 0.697 0.703
F C 1.33 1.73 0.053 0.068
G D 0.69 0.81 0.028 0.031
G 1.524 BSC 0.060 BSC
H
L 1.84 2.44 0.073 0.096
J N 13.80 14.20 0.544 0.559
R 15.29 15.69 0.602 0.617

R G
C
L D 86 PL
-A- 0.50 (0.020) M T B S A S

MCM56824A MOTOROLA FAST SRAM

8
 FN PACKAGE
52–LEAD PLCC
CASE 778–02

-N- Y BRK B 0.18(0.007) M T N S –P S L S –M S

D U 0.18(0.007) M T N S –P S L S –M S

-L- 52 -M- NOTE 1

LEADS
ACTUAL Z1
W

D
(NOTE 1) 52 1

-P-
V G1

VIEW D–D 0.25(0.010) S T N S –P S L S –M S

A 0.25(0.010) S T L S –M S N S –P S

Z
0.18(0.007) M T L S –M S N S –P S
R 0.25(0.010) S T L S –M S N S –P S X H
0.18(0.007) M T N S –P S L S –M S

C K1
E
K
0.10 (0.004)
52 -T- SEATING 0.18(0.007) M T L S –M S N S –P S
G J PLANE F
(NOTE 1) 0.18(0.007) M T N S –P S L S –M S
DETAIL S DETAIL S
G
MILLIMETERS INCHES
1 DIM MIN MAX MIN MAX
0.25(0.010) S T L S –M S N S –P S A 19.94 20.19 0.785 0.795
B 19.94 20.19 0.785 0.795
C 4.20 4.57 0.165 0.180
E 2.29 2.79 0.090 0.110
F 0.33 0.48 0.013 0.019
G 1.27 BSC 0.050 BSC NOTES:
H 0.66 0.81 0.026 0.032 1. DUE TO SPACE LIMITATION, CASE 778-02 SHALL BE
J 0.51 — 0.020 — REPRESENTED BY A GENERAL (SMALLER) CASE
K 0.64 — 0.025 — OUTLINE DRAWING RATHER THAN SHOWING ALL 52
R 19.05 19.20 0.750 0.756 LEADS.
U 19.05 19.20 0.750 0.756 2. DATUMS -L-, -M-, -N-, AND -P- DETERMINED WHERE TOP
V 1.07 1.21 0.042 0.048 OF LEAD SHOULDER EXIT PLASTIC BODY AT MOLD
W 1.07 1.21 0.042 0.048 PARTING LINE.
X 1.07 1.42 0.042 0.056 3. DIM G1, TRUE POSITION TO BE MEASURED AT DATUM -T-,
SEATING PLANE.
Y — 0.50 — 0.020
4. DIM R AND U DO NOT INCLUDE MOLD PROTRUSION.
Z 2° 10° 2° 10° ALLOWABLE MOLD PROTRUSION IS 0.25 (0.010) PER SIDE.
G1 18.04 18.54 0.710 0.730 5. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M,
K1 1.02 — 0.040 — 1982.
Z1 2° 10° 2° 10° 6. CONTROLLING DIMENSION: INCH.

MOTOROLA FAST SRAM MCM56824A

9
 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.

Mfax is a trademark of Motorola, Inc.

How to reach us:
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MCM56824A ◊ MCM56824A/D
MOTOROLA FAST SRAM
10
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