Download as DOCX, PDF, TXT or read online from Scribd
Download as docx, pdf, or txt
You are on page 1/ 6
Lab 02
CMOS 0.25 micron Technology Inverter Characteristics and Layout
in Microwind. 1. Objectives: In this lab students will design and implement a CMOS Inverter. Different design Parameter’s effects like transistor sizing, supply voltages etc well be analyzed and delay, area, power and currents will be observed. This lab assumed that students are familiar with Microwind and Lambda based design rules. The tool used in this lab is Microwind. The tasks given in the lab include: • Design of CMOS Inverter and transistor sizing. • Layout Design using the tool. • Gate delay, area, power and current analysis and the effects of transistor sizing on these parameters. Tool used: Microwind, DSCH 2. Lab Description: CMOS Inverter CMOS Inverter/NOT gate is considered to be the heart of VLSI circuits, based on the understanding of NOT gate we can extend it easily to NAND and NOR gates which are the basic building blocks of more complex circuits e.g. multipliers and microprocessors. As per discussion and design on white board in the Lab, a NOT gate can be implemented using two FETs i.e. a pFET and an nFET both connected in series, in which Vdd is supplied to pFET and nFET is grounded, input x is applied to the gate terminals of both and the output is obtained at node y. Design/ Diagram/Circuit
As covered in the lectures we know that the mobility of the holes is less than that of electrons, and in CMOS inverter pFET is responsible for the conduction of current leading a logic “1” at the output, while nFET is responsible for the conduction of current leading a logic “0” at the output. This means that the gate delay form low to high will be greater than the gate delay for low to high voltage.
3. Lab Instructions Automated Layout from the Schematic Design 1. Open DSCH and select the foundry cmos025. 2. Save the design as “Save as” as Lab02. Save the design frequently during lab session. 3. Draw the circuit diagram of inverter. 4. Check for floating point if any. 5. Simulate the Design 6. Make a Verilog file of the design. 7. Open Microwind and select the foundry cmos025. 8. Compile the Verilog file of inverter “Lab02.txt” for Compile > Compile Verilog File command 9. Save the design. 10. Simulate the design using the Run command 11. Analyze configuration delay, gate delay, current, power, and midpoint voltage. 12. Repeat the design for different value of transistor size and supply voltage and carefully observe the changes in configuration delay, gate delay, current, power, and midpoint voltage. Manual Layout of Inverter 1. Open Microwind and select the foundry cmos025. 2. Save the design as “Save as” as “Lab02”, and save the design frequently during the Lab session. 3. Draw the layout of nMOS using MOS Generator 4. Draw the layout of pMOS using MOS Generator by setting the appropriate width of pMOS. 5. Connect the two transistors using Metal 1 as per design. 6. Draw the rails of V DD and ground rails above and below. 7. Connect the nWell to V DD 8. Check the design using DRC for any design rule violation and correct the design in case of error, again run the DRC and check for errors. Or run the DRC after each change in the layout. 9. Check for Electrical connections to be valid. 10. Add inputs and outputs to the design; also add virtual capacitance at the output in your design. 11. Simulate the Design. Observe the values of configuration delay, gate delay, power, current, VTC, and area. 12. Repeat the design using for different values of transistor’s dimensions, supply voltages. And observe the changes in configuration delay, gate delay, power, current, VTC, and area carefully. Make a conclusion of your observations. 4. Lab Report • Give a short description of the contents of the lab • Include block diagram/diagrams of your design in the lab report • Describe your layout design approach parameters and explain the effects of each the parameter • Include layout of your design also add your name on the design for evaluation purpose. • Include the results in timing waveform format in your report • Only follow the provided cover page format Simulation Analysis (Include in your Lab Report) You can increase the table and also the entries for in depth analysis. A properly presented in depth analysis with graph based on the table entries will be highly appreciated. Discuss the Effects of width design parameter of the MOS devices on their behavior 5. Lab Tasks: Task 1: Draw schematic (logic) diagram of CMOS inverter using the DSCH and analyze its functionality by simulation. Task 2: Generate the automated layout of the CMOS inverter from schematic diagram and analyze its functionality, Simulate the Design. Observe the values of configuration delay, gate delay, power, current, VTC, and area. Task 3: Manually design the layout of CMOS inverter, Simulate the Design. Observe the values of configuration delay, gate delay, power, current, VTC, and area. Task 4: Design the layout of 3-State Inverter. Task 5: Design the layout of Ring Oscillator.
