The document provides an overview of MOSFET structure and processing. It discusses the basic n-channel and p-channel MOSFET layout including the substrate, gate, gate oxide, source, drain and field oxide. It then describes the key fabrication steps like active region masking, field oxide growth, gate oxide and polysilicon deposition, source/drain implantation, dielectric and metal patterning. The effective channel length is determined by processing factors like source/drain implantation and diffusion.
The document provides an overview of MOSFET structure and processing. It discusses the basic n-channel and p-channel MOSFET layout including the substrate, gate, gate oxide, source, drain and field oxide. It then describes the key fabrication steps like active region masking, field oxide growth, gate oxide and polysilicon deposition, source/drain implantation, dielectric and metal patterning. The effective channel length is determined by processing factors like source/drain implantation and diffusion.
The document provides an overview of MOSFET structure and processing. It discusses the basic n-channel and p-channel MOSFET layout including the substrate, gate, gate oxide, source, drain and field oxide. It then describes the key fabrication steps like active region masking, field oxide growth, gate oxide and polysilicon deposition, source/drain implantation, dielectric and metal patterning. The effective channel length is determined by processing factors like source/drain implantation and diffusion.
The document provides an overview of MOSFET structure and processing. It discusses the basic n-channel and p-channel MOSFET layout including the substrate, gate, gate oxide, source, drain and field oxide. It then describes the key fabrication steps like active region masking, field oxide growth, gate oxide and polysilicon deposition, source/drain implantation, dielectric and metal patterning. The effective channel length is determined by processing factors like source/drain implantation and diffusion.
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97.
398*, Physical Electronics, Lecture 20
MOSFET Structure and
Processing Lecture Outline • To better understand how to model the behavior of the MOSFET, begin the same way as the diode and bipolar, consider fabrication of the basic structure • An important fundamental quantity, the oxide capacitance, will be identified from the structure • The layout of masks for the MOSFET structure will be considered, and the effective channel length identified from processing considerations
97.398*, Physical Electronics:
David J. Walkey Page 2 MOSFET Structure and Processing (20) Basic MOSFET Structure - Substrate • The substrate of the MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) is normally silicon, doped either p-type or n-type • p-type substrate → n-channel device • n-type substrate → p-channel device • Substrate is also termed bulk • Substrate is connected using metal on the back side and/or a highly doped region of similar type (substrate thickness is not shown to scale)
97.398*, Physical Electronics:
David J. Walkey Page 3 MOSFET Structure and Processing (20) Basic MOSFET Structure - Gate • The MOSFET gate is a conductive region electrically isolated from the substrate • Since the gate must provide an equipotential surface above the substrate, it must be constructed from a very conductive material • Older technology used metal (Al) gates, newer technology uses polysilicon, a material with grains of crystalline structure separated by grain boundaries
97.398*, Physical Electronics:
David J. Walkey Page 4 MOSFET Structure and Processing (20) Basic MOSFET Structure - Gate Oxide • The function of the gate oxide is to provide a high quality insulator between the conductive gate and the substrate • Although preventing current flow from gate to substrate, the oxide layer still allows penetration of electric field from gate to substrate • The gate oxide is usually silicon dioxide (hence the name), or can be other insulators such as Si3N4
97.398*, Physical Electronics:
David J. Walkey Page 5 MOSFET Structure and Processing (20) MOSFET Oxide Capacitance • If the thickness of the oxide insulating layer is labelled tox, the per unit area oxide capacitance associated with the layer is defined as ε C!ox ≡ ox tox
• The oxide permittivity εox is a
tabulated value, for SiO2 being 3.9 times the permittivity of free space
97.398*, Physical Electronics:
David J. Walkey Page 6 MOSFET Structure and Processing (20) Example 20.1: Oxide Capacitance Calculation
Calculate the per unit area oxide capacitance for a MOSFET
whose gate oxide is 20nm thick.
97.398*, Physical Electronics:
David J. Walkey Page 7 MOSFET Structure and Processing (20) Example 20.1: Solution • Converting the oxide thickness to cm gives
1 m 100 cm 20 nm ⋅ 9 ⋅ = 20 × 10 − 7 cm 10 nm 1 m
• The per unit area oxide capacitance is therefore
David J. Walkey Page 8 MOSFET Structure and Processing (20) Basic MOSFET Structure - Source and Drain • The source and drain of the MOSFET are two regions with high doping of opposite type to the substrate immediately adjacent to the edges of the gate • The source and drain regions are normally contacted with metal, separated from the gate and substrate by a dielectric isolation layer
97.398*, Physical Electronics:
David J. Walkey Page 9 MOSFET Structure and Processing (20) Basic MOSFET Structure - Field Oxide • The MOSFET structure is surrounded by a thick (≈1 µm) layer of insulator, normally silicon dioxide, called the field oxide • The field oxide isolates the gate from the substrate outside the active device region as well as preventing the formation of other parasitic MOSFET devices
97.398*, Physical Electronics:
David J. Walkey Page 10 MOSFET Structure and Processing (20) MOSFET Symbols • The symbols and potential definitions for the MOSFET are shown to the right • An n-channel device has – p-type substrate – n+ source and drain regions – substrate normally connected to the most negative potential in a circuit • A p-channel device has – n-type substrate – p+ source and drain regions – substrate normally connected to the most positive potential in a circuit
97.398*, Physical Electronics:
David J. Walkey Page 11 MOSFET Structure and Processing (20) MOSFET Fabrication - Active Region Masking • Using a mask, silicon nitride is patterned to remain in the areas which will form the active region of the MOSFET • A pad oxide is grown on the surface before deposition of the nitride to protect the silicon surface from damage induced by the different bonding structure of the nitride
97.398*, Physical Electronics:
David J. Walkey Page 12 MOSFET Structure and Processing (20) MOSFET Fabrication - Field Oxide Formation • Using wet oxidation (since the quality is not critical and a thick layer is required), the field oxide is grown on the wafer surface outside the active areas
97.398*, Physical Electronics:
David J. Walkey Page 13 MOSFET Structure and Processing (20) MOSFET Fabrication - Device Well Structure • After the nitride and pad oxide are stripped, the active area is surrounded by field oxide and therefore lies inside a “well” in the field oxide • This is the origin of the term device well to refer to the active area of the MOSFET • The active area mask is sometimes called the device well mask
97.398*, Physical Electronics:
David J. Walkey Page 14 MOSFET Structure and Processing (20) MOSFET Fabrication - Gate Oxide and Polysilicon • A thin (10-30 nm) gate oxide is then grown on the surface - since the quality of this oxide is critical and the thickness is not large, a dry oxidation is used • Polysilicon is then deposited using CVD and the oxide and poly are patterned using the polysilicon mask
97.398*, Physical Electronics:
David J. Walkey Page 15 MOSFET Structure and Processing (20) MOSFET Fabrication - Gate Connection • The gate within the MOSFET area as well as all other polysilicon lines are formed simulataneously • The gate is connected by running the polysilicon up onto the field oxide and to another point or eventually to a connection to metal
97.398*, Physical Electronics:
David J. Walkey Page 16 MOSFET Structure and Processing (20) MOSFET Fabrication - Source/Drain Implantation • The source and drain are then implanted with the gate in place • This process is called self aligned, since the source and drain do not need to be optically aligned with the gate • Some lateral diffusion occurs which makes the actually distance between the source and drain less than the length of the gate material
97.398*, Physical Electronics:
David J. Walkey Page 17 MOSFET Structure and Processing (20) MOSFET Fabrication - Dielectric Patterning • A second layer of dielectric is deposited using CVD and patterned to open windows to the source and drain • This step uses a contact cut mask
97.398*, Physical Electronics:
David J. Walkey Page 18 MOSFET Structure and Processing (20) MOSFET Fabrication - Metallization • Metal is deposited over the back side of the wafer to form the backside substrate contact • Metal is also deposited on the surface and patterned using the metal mask
97.398*, Physical Electronics:
David J. Walkey Page 19 MOSFET Structure and Processing (20) MOSFET Fabrication - Metallization • Metallization surrounds the contact cut area, which is normally constrained to be within the source drain region • Metal to polysilicon connection would have been made elsewhere (on top of field oxide)
97.398*, Physical Electronics:
David J. Walkey Page 20 MOSFET Structure and Processing (20) Simplfied MOSFET Layout • A simple four mask representation is shown to the right • Note that poly crosses the active region (riding up onto the field oxide) - wherever poly and active coincide, poly will be separated by gate oxide only • Because the process is self aligned, the source and drain will be formed in any active region not coincident with poly
97.398*, Physical Electronics:
David J. Walkey Page 21 MOSFET Structure and Processing (20) MOSFET Effective Channel Length • Lateral diffusion LD of the source and drain cause the distance between the source and drain edges to be less than the length of the gate polysilicon • The drawn channel length refers to the length of the gate material specified on the mask • The effective channel length L is the actual distance between the source and drain edges, which will be the electrical channel length
97.398*, Physical Electronics:
David J. Walkey Page 22 MOSFET Structure and Processing (20) MOSFET Geometry • The (effective) channel length L is the distance between the source and drain regions under the gate • The channel width W is the width of the source and drain, and hence the channel, regions • First order quantitative analysis will consider behaviour to be independent of location along W, therefore use a 2D analysis and multiply result by W
97.398*, Physical Electronics:
David J. Walkey Page 23 MOSFET Structure and Processing (20) Lecture Summary • The fabrication of a basic MOSFET structure was illustrated, and the oxide capacitance defined in terms of the gate oxide thickness • The self-aligned MOSFET structure avoids a difficult alignment of the gate and source/drain regions, allowing smaller devices - benefits will be discussed in lecture 27 • Because of lateral diffusion under the gate, the effective channel length is less than the drawn channel length • Internal quantities will be assumed independent of position along the MOSFET width (but not length)
97.398*, Physical Electronics:
David J. Walkey Page 24 MOSFET Structure and Processing (20)
