Verilog Interview
Questions Day 6
Welcome to the day 6 of Verilog interview questions.
These questions are designed to help you prepare for
your upcoming interview
by Manikanta Nagalla
1. What is the purpose of a Verilog testbench?
A testbench is used to verify the functionality of a design.
It applies test signals (inputs) to the design under test
(DUT) and observes the outputs, ensuring that the DUT
behaves as expected.
2. Explain how $monitor differs from $display?.
$monitor continuously monitors and displays values
whenever there’s a change in specified variables.
$display only shows values at the moment it’s called,
making it a one-time print.
3. How can you apply stimuli to inputs in a testbench?
Stimuli are applied by assigning values to the DUT inputs within
initial or always blocks. You can directly set values or use a sequence
of changes to simulate different conditions.
4. What does $finish do, and when should you use it?
$finish stops the simulation. Use it when the testbench
has completed all testing, so the simulator knows it’s time to
end the simulation.
5. Describe the use of #delay in Verilog?.
#delay adds a time delay before the next statement
is executed. It’s useful for simulating timing behaviors
and controlling the sequence of events in a testbench.
For example, #10; waits for 10 time units before
moving to the next line.
