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Assignment 1

The document outlines the structure and components of Verilog modules and testbenches, which are essential for designing and verifying hardware circuits. It includes examples of various gate designs (NOT, OR, NOR) along with their respective testbenches that simulate real-world scenarios. Each testbench includes signal declarations, stimulus generation, and simulation control to ensure the correctness of the design.

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Nishant
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6 views5 pages

Assignment 1

The document outlines the structure and components of Verilog modules and testbenches, which are essential for designing and verifying hardware circuits. It includes examples of various gate designs (NOT, OR, NOR) along with their respective testbenches that simulate real-world scenarios. Each testbench includes signal declarations, stimulus generation, and simulation control to ensure the correctness of the design.

Uploaded by

Nishant
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Q1)

A Verilog module represents the actual hardware design that will


eventually be synthesized into physical circuits. It defines the behavior of
the circuit and the connections between its components, serving as the
core representation of the intended hardware functionality.
Key Components of a Verilog Module (Design)
Module Declaration
module Name (input a, input b, output y);
Port List
• Inputs: Signals that provide data to the module.
• Outputs: Signals that carry the module's result.
Data Types and Parameters
• wire (for continuous assignments) and reg (for sequential logic).
endmodule
Test Bench
A testbench is used to simulate real-world scenarios to verify the
correctness of the
design before
implementing it in hardware.
Key Components of a Testbench
Testbench Module Declaration
Instantiation of the Design Under Test (DUT)
Signal Declarations
Stimulus Generation (Truth Table)
Monitoring and Verification
Simulation Control
Q2)

Q3)
3_Design
// S24CSEU1512
//Nishant Agarwal
module not_gate( input a, output y);
assign y =~a;
endmodule
3_Test Bench
// S24CSEU1512
//Nishant Agarwal
module tb_not_gate; reg A;
wire Y;
not_gate a1 (.a(A) ,
.y(Y)); initial begin
A = 0;
#5;
A = 1; #5;
end initial begin
$dumpfile("dump.vcd");
$dumpvars( 1); end endmodule

3_Waveform

Q4)
4_Design
// S24CSEU1512
//Nishant Agarwal
module or_gate( input a,b, output y);
assign y = a ||b;
endmodule

4_Test Bench
// S24CSEU1512
// Nishant Agarwal
module tb_or_gate; reg A,B; wire Y;
or_gate a1 (.a(A) ,.b(B),.y(Y));
initial begin
A = 0; B =0; #5;
A = 0; B =1; #5;
A = 1; B =0; #5;
A = 1; B =1; #5;
end initial begin
$dumpfile("dump.vcd");
$dumpvars( 1);
end endmodule

4_Waveform

Q5)
5_Design
// S24CSEU1512
//Nishant Agarwal
module nor_gate( input a,b, output y);
assign y = ~(a || b);
endmodule
5_Test Bench
// S24CSEU1512
//Nishant Agarwal
module
tb_nor_gate; reg A,B;
wire Y;
nor_gate a1 (.a(A) ,.b(B),.y(Y));
initial
begin
A = 0; B =0; #5;
A = 0; B =1; #5;
A = 1; B =0; #5;
A = 1; B =1; #5;
end initial begin
$dumpfile("dump.vcd");
$dumpvars( 1);
end
endmodule

5_Waveform

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