BANGLADESH Department of Computer Science and Engineering (CSE) COURSE OUTLINE
Part-A
1. Course Code: 0714-2109
2. Course Title: Digital Logic Design
3. Course Type (GEd/Core Course/Elective/Field Work/Project/Thesis): Core Course
4. Year/Semester: 2nd year 1st semester
5. Academic Session: FALL 2024
6. Programme: B.Sc. in Computer Science and Engineering (CSE)
7. Course Teacher: Afsana Sharmin Shanta Lecturer Dept. of CSE, Notre Dame University Bangladesh Contact: +88 01537431883 Email: sharmin@ndub.edu.bd
8. Prerequisite(s) (if any): N/A
9. Credit Value: 3.00
10. Contact Hours: 3 hours per week
11. Total Marks: 100
12. Rationale of the Course: The course covers the theories, guidelines, and methods of designing digital systems. The course imparts the principles of digital systems using approaches for logic design and development. The foundation for further coursework in topics like computer architecture and organization, microprocessor interface design, and VLSI design is provided by this course. The design of digital systems logic will be taught to students.
13. Course Objectives:
The course objectives are to- Introduce the students to fundamental concepts such as Boolean algebra, logic gates, truth tables, and binary arithmetic. Teach students how to analyze and design combinational logic circuits to perform specific tasks like arithmetic operations, code converters, and multiplexers. Equip the students with the skills to design and implement sequential logic circuits using flip-flops, counters and registers. Course Contents: Boolean Algebra, De Morgan’s theorem, Logic Gates and their truth tables, Boolean functions, number systems, canonical forms, minimization techniques, combinational logic circuits, Parallel adder, magnitude comparator, decoder, encoder, multiplexer, demultiplexer, ROM, PLA design, flip-flops, race around problems, synchronous and asynchronous counters and their applications, synchronous and asynchronous logic design, state diagram, Mealy and Moore machines, state minimization and assignments, Pulse mode logic.
14. Course Outcomes (CLOs) and Mapping of CLOs with Bloom’s Taxonomy Level:
By the end of this course, students will be expected to
Bloom’s Taxonomy Sl. No. CLOs C A P Explain the concepts of designing combinational and sequential CLO1 C2 logic circuits, and Programmable Logic Devices Apply Boolean algebraic concepts for designing combinational CLO2 C3 circuits. Apply Boolean algebraic principles and state transition CLO3 C3 techniques for designing sequential circuits. Analyze appropriate digital systems with acquired knowledge of CLO4 C4 small-scale digital logic circuits suitable for everyday use. 15. Mapping of CLOs with Program Outcomes (PLOs):
TLS1 Lectures on different topics twice a week using multimedia TLS2 Active discussion in class regarding efficient solving of critical problems. Group discussion and presentation regarding diverse problems and TLS3 corresponding lectures. TLS4 Evaluation of class performances to reach each student in a class for every topic.
17. Course Plan and Mapping of TLS and Assessment Strategy with CLOs:
Teaching- Corresponding Week Topic Learning Assessment Strategy CLO Strategy Number systems Class Performance, 1 TLS1, TLS2 CLO 1 Quiz, Mid Term Boolean Algebra, De Class Performance, 2 Morgan’s theorem, Logic TLS1, TLS2 CLO 1 Quiz, Mid Term Gates and their truth tables Boolean functions, TLS2, TLS1 Class Performance, 3 Canonical forms CLO 1 Quiz, Mid Term Minimization techniques TLS1, TLS2 Class Performance, 4 CLO 1 Quiz, Mid Term Combinational logic circuits TLS1, TLS3 Class Performance, CLO 1, CLO 2 5 Mid Term Parallel adder TLS1, TLS3 Class Performance, CLO 1, CLO 2 6 Mid- Term Magnitude comparator TLS1, TLS3 Class Performance, CLO 1, CLO 2 7 Mid Term Mid-Term Examination Decoder, Encoder TLS1, TLS3 Class Performance, CLO 2 8 Semester Final Multiplexer, Demultiplexer, TLS1, TLS3 Class Performance, CLO 2 9 ROM Semester Final Latches, Flip-flops, Race TLS1, TLS2 Class Performance, CLO 3 10 around problem Semester Final Synchronous and asynchronous TLS2, TLS3 Class Performance, CLO 3 11 logic design Semester Final Synchronous and asynchronous TLS2, TLS3 Class Performance, CLO 3 12 counters and their applications Semester Final State minimization and TLS1, TLS3 Class Performance, CLO 3 13 assignments, State diagram, Assignment, Semester Mealy and Moore machines Final 14 Presentation TLS1, TLS1 Class Performance CLO 4
Part-C
18. Assessment and Evaluation
1) Assessment Strategy: Class Performance, Quiz, Assignment, Project, Report, Spot Test, Presentation, Viva, Mid Term, and Semester Final 2) Marks distribution:
Components Grading Attendance/ Class 10% Performance
(CLO = Course Learning Outcome, C = Cognitive Domain, P = Psychomotor Domain, A =
Affective Domain)
Part D
19. Learning Materials
• M. M. Mano and M. D. Ciletti, Digital Design: With an Introduction to the Verilog HDL. New York: Pearson, 2019. • R. J. Tocci, Digital Systems: Principles and Applications.
