apn ea eed ve her ah rTEHO, AAT SURG NCHT College Computer Architecture (3-1-1) Evaluation : Theory Practical Total ‘Sessional 30 20 50 Final i 50 : 30 Tora 80. 220 1007 | ~ Course Objectives: + To acquaint the students with the fundamentals of compuier systems, + To apprise the studcats with the architectural and associated components of computer systems. : + To aware the students about the architecture of the computer systems available in the market. Course Contents: 1 Introduction hrs Computer Organization and Computer Architecture ‘ Review of Evolution of Computer System a Basic Structure of Computer System Examples of Computer Far Future Trends in Computer Review of Instruction Sets, Addressing Modes and Instruction Formats a Register Transfer and Micro Operations Zhrs Register Transfer and RTL. Micro operations Data Transfer Micro operations Arithoretic and Logical Micro operations Shift Micso operations Invoduction ‘© HDL and VHDL PNK Central Processing Unit 3hrs CPU Organization/Structure Reyister Organization and Data Paths Insizuction Cycle Arithmetic and Lovical Unit Design Principles for Modern Systems 4. Computer Arithmetic ened Binary Addition and Subtraction ged Binary Muhiplication Algorithm4s 4.6. 47. 48. 49. 6a. Booth’s Algorithm Unsigned Binary Division Floating Point Representation BCD Arithmetic Unit + BCD Adder Arithmetic Pipelining ‘Algorithm hrs Control Unit Control of the Processor Hardwired Control Usit © Control Unit Inputs Control Unit Logic ‘Micro programmed Control Unit ery Instructions and Its Types ture of Miero programmed ‘Micro Instruction Sequencing Micro Instruction Execution ‘Applications of Hardssired and Micro programme .d Control Units tion Bis ‘Memory Organi Memory Hierarchy Main Memory © RAY Auxiliary Mem Magnetic Dish st © Optical Disks + Flash Drives + Review of RAID Associative Memory = Hardwere Oreanization © Address Marching Lovie © Read/Write Operations Cache Memory @ Cache .sutistization + Mapping Cache Memory © Direct. Ase Mapping + Wnte Policy > Replacement Algorithms “ociative and Set Associative Memory Iuput Output Organization Extemal Devi VO Module Structure ie view of Prdzrammed /O ang Review of DMA. 1/0 Chanel ase Dy and 10? riven UO i rocessors7.5. External Interfaces A. Reduced Instruction Set Computers 8.1. RISC VS. CISC ae 8.2. RISC Pipelining 8.3. Instruction Pipelining 8.4. Conflicts in Instruction Pipelining and their Solutions 8.5. Introduction to Register Windows and Register Renaming Introduction to Parallel Processing 6hrs Parallelisms in Uniprocessor System " Multiprocessor Systems and their Characteristics Fiynn’s Classification 9.4. Interconnection Structures in Multiprocessors 9.5. Cache Coherence 9.6. Introduction to Vector Processing and Array Processors 9.7. Introduction to Multithreaded Architecture 16. Multicore Computers 3 brs 10.1. Hardware Performance Issues + Increase in Parallelism + Altemative Chip Organizations + Power Consumption 10.2. Software Performance Issues + Software on Multicore 10.3. Multicore Organization 10.4.” Dual Core and Quad Core Processors 10.5 Power efficient Processors Laboratory ‘The individual student should develop a project or perform a case study on Computer Architecture. The topic could be either initiated by the student or selected from a list Provided by the instrucior. An oral presentation with a demonstration in ease of project should be part of the laboratory. Reports must be prepared. Text Books: ce Stallings, W., “Computer Organization and Architecture”, Eighth Edition, 2011, Pears 2 Mano, M. M., “Comprter Systems Archirecture”, Third Edition, 2011. Pearson. References: 1 Tanenbaum, A.S.. “Structured Computer Crganizarion”, Fourth Edition, 2003. Pearsor Eduestion, “Comp sion and Archiiecture”, 2012, le Rejaraman, V. et all, “Computer Organization and Architeclure", 201. vi Sima, D. etal, “Advanced Compuser Architecture”, 2000, Addison Wesley. goers.POKHARA UNIVERSITY Level. Bachelor Semester ~ Fall Year 2013 Programme: BoE Full Marks: 100 Course: Computer Architecture Pass Marks: 45 Time Shes. Canilicdates are required to give their answers in their own words as far as practicable. The figures in the margin indicate full marks Wdlempt all the questions. 4) Differentiate between. Computer Architecture and Computer Organization. Draw the diagram of extended IAS computer. §) Define addressing modes and their purposes. Explain various addressing modes with their advantages and disadvantages. Haw Howchart for Booth's multiplication algorithm. Perform (7)io * (-2}ousing Booth's multiplication algorithm !xplain how the concept of micro-programming is used to implement «control unit? How the control word of the micro-instructions could be arranged in the control memory? 4) What are micro instructions? Explain different types of instruction based on number of address. by What are the drawbacks of programmed V/O and interrupt driven VO? Fxplain how DMA overcomes those drawbacks. sy Explain about communication between CPU and VO- processor Ppert you answer with the help of suitable example by Why mapping is needed in cache? Discuss any two mapping strategies use in cache 4) Explain the roles of overlapped register window in B'S processor. by What do you mean by pipelining? How pipelining increases the performance of system? Explain in detail 1) In cera se ions it is necessary to perform the awithnctic operation (4,*B,)+(C,)with a stream of numbers, Specify a pipeline configuration to carry out this task. List the contents of all registers in the pipeline for i=1 through 6.esti in dete’ also define catty 5) Explain about interconnection structure 1 detz# also define chy coherence, 7. Write short notes on amy twas le a) Instruction Cycle b) Application of Micro programming ¢) Virtual MemoryPOKHARA UNIVERSITY Level: Bachelor Qo Semester: Course: Computer Architecture (New Course) Pass Marks: 45 Time: Shs, as practicable. The figures in the margin indicate fuil marks, Attenipt all the questions, a) Diff pee between computer organization and architecture with 8 example, Define RTL Explain all micro operations with RTL code a) 7 Draw internal CPU structere and explain each part, 7 b) What is normalization in floating point operation? How do you & normalize the floating point after floating point operation? 3) Explain Booth algorithm and use it to multiply ($)io* (yo 8 ») Differentiate between hardwired and micro programmed control unit, 7 Which one is preferable and why? fllustrate, a) What are the various microinstruction sequencing techniques used in 8 control unit? §) Explain operation of magnetic disk with necessary diagram, 1 #) Define Cache memory. What is cache coherence? Explain associative 8 mapping technique. ») Differentiate between programmed I/O and interrupt driven /O. 7 8) What is pipelining? Explain major hurdles of pipelining, 7 by Why cache coherency occurs in multiprocessor system and how can 8 this problem be removed. Explain Write short notes on: (Auy two) 2x5 *) Dual core and Quad core Processor 5) Cache coherence ©) RAID jara Saad) sed vg Sapo oh © argu SAAR SUNN NeIT CollegePOKHARA UNIVERSITY a pastel Semester: Spring Year =; 2014 amme: BE 5 ee Computer Architecture ie ae ae a ass Marks: Time: 3hrs. candidates cre required t0 give their answers j cb ‘Sin their own words as far ‘he figures in the margin indicate Fall marks, Auempt all the questions, a) Differentiate between Computer Architecture and Computer 8 Organization. Explain the term SSI, LSI and VLSI. v) Define the term micro-operation. Write down the sequence of 7 microinstructions for fetch and interrupt cycle, a) What is the necessity of Booth’s algorithm? Draw the flowchart for 8 oating point division. b) What is microprogramming? Explain the function of micro programmed control unit with figure. Draw draft architecture of CPU and show the microinstruction and control signal for the following instruction: i. Load Accumulator ii, Store Accumulator iii, And to Accumulator iv. Jump if AC=0. 5) Why are external devices not connected directly with bus structure of coriyputer system? Draw an internal structure of /O module, ; ' a) What is writing policy in cache? Explain about direct mapping of cache memory with its pros and cons. a : — z }) Discuss Interrupt Driven I/O with necessary block diagram. , Explai on Structures in multiprocessor 8. °) Explain various types of interconnection system 1) Detine RISC processor and differentiate it with CISC — 4 : : . anches? 8 "Y What are different approaches for dealing wa tee dead With Describe how branch prediction and delay vendition branch.7 Pa t form the b) In certain scientific computations it is ices alee arithmetic operation (A, + B,)(C, + D,) with a is task. List the Specify a pipeline configuration to carry out this contents of all registers in the pipeline for i=1 through 6. iy Write short notes on: (Any two) a) Multicore organization b) VHDL ¢) Flynn's classification of, computera) ») s) POKHARA UNIVERSITY Level: Bachelor Semester: Fall Year 22015 Prograrame: BE 5 nas , Full Marks: 100 ‘ourse: Computer Architecture Pass Marks: 45 i Time: Shs, Candidat. i i ts prociteabin “eared 10 Rive their answers in their owni words as far The figures in the margin Indicate fidl marks, . Attempt all the questions, Diftereati ate between Computer Architecture and Computer Organization. Explain the term SSland VLSI. Define RTL. Describe ditferem types of Shift micro-operations, ‘struction Set? Explain the busie ‘component used in register organization, Divide (8) by (3) usin, Performed using binary numbers? Give an example. Differentiate between Hardwired and Micro-programmed control unit Explain the logic of Hi jardwired unit, Differentiate between direct, associative and set associative mapping technique. overcome the problems of | both these techniques? Which instruction set computers are used in today’s world? Differentiate between RISC and CISC. How Parallelism occurs in uniprocessor system? What are the Connections possible for multiprocessor system? Assume that pipeline has K=6 segment and execute n=120 tasks in Sequence Let the time taken to process a sub-operation in each Segment is 30 sec. Calculate the speed up ratio in the pipeline, Write shont notes on: (Any two) Dual Core and Quad Core Processors. BCD Adder. Register Windowing and Register Renaming. &POKHARA UNIVERSITY Level: Bachelor seese San Programme: BE Semester: Spring ‘Year 12015 Course: Comput ; Full Marks: 100 luke Pass Marks: 45 Time Shes Candidates we re. ir ei be practicable, e410 Bie their answers in their own words es for {he figures in the mer gin indicate full marks Altempt ul the questions, a) Differentiate between! “Organization with examp! Computer Architecture and Computer 8 b) What are the diffetent rey le. pistes used {0 ae 83 ed for storage and data transfer in 7 a) Perform 713 division using unsigned binary division. 8 ©) Explain arithmetic pipelining with examples. 1 a) Explain how Single address, two address and variable format differ 8 from each other? b) Define mapping function, Brie tly explain the Setassociative mapping 7 technique a) What are the limitations of programmed VO, how these az improved 7 in interrupt driven VO, and how the limitations of interrupt'driven VO are improved by DMA. b) Instruction pipelining increases system performance without 4 incieasing processor number, explain how? v) What are Pipelining hazanis and how can these be removed? 4 a) Assume that pipeline has K=8 segment and execute n=120 tasks in 8 sequence .Let the time taken { process a sub-uperation in each segment is 30 sec. Calculate the speed up ratio in the pipeline . b) Define parallelism? Draw different interconnection stuctue of 7 snultiprocessor system and describe it with necessary diagram ‘iets: % 8) Explain different types of hardware performance “cues in multicore § computers. b) What is cache coherency and how can they be removed? ie Write short nutes on: (Any b¥0) as y) BCD Add } Dual Cow and Quad Core Processors ©) VHDLa) b) b) a) ») a) b) b) a) by POKHARA UNIVERSITY Level: Bachelor Ser 7 Pabalice BE smester: Fall Yea 016 Coprse: Computer Architecture Full Mais: 100 st Time : Shrs. Candidates are re quired to giv swers in thei ces ive their answers in their own words as far The figures in the margin indicate full marks, Attempt all the questions, Define Coinputer Organization and what are the instruction used in IAS computer explain each in detail, Explain instruction cycle state diagram with interrupt. Compute (7):0%(-3),g where Rumbers are represented by 2s complement representation vol unit in implemented, block diagrams. Define cache. Explain set associative mapping with necessary diagrams, Define cache miss. Describe cache read operation with flowchart Define Extemal Interfaces. Explain how DMA improves. the limitations of Interrupt Driven VO. How Instruction pipelining can increases system performance? A non pipeline system takes SOns to process a task. The same task can be processed in a six segment pip: 1¢ with clock eyele of 10ns, Determine the speed up ratio of the pipeline for 100 tasks. What is the inaximum speedup that can be achieved? Mention the need of use of large register file in RISC. Explain overlapping r_zsster windows in RISC with example? Explain different interconnection structures systems. in multiprocessor What is cache coherence problem? Explain MESI protocol approach for the solution of this problem. : Explain different types of hardware and software performance issues in multicore computers.7. Write short notes on: (Any two) a) Register Transfer language (RTL) b) Dual and Quad Core Processor c) Addressing Modessa) vel Bachetor Semester: g,. prowfarmime: BE : "er Spring y guise! Computer Architecture Pa #2016 C ull Marks: 199 BSS Marks: 45 I i M Candidates are required 10 giy iheir is an acticable. NS Wer in theip asp! " own words The figures in the margin indicate Lull marks Auempt all the questions. " a) Write codes for the Operation Y {and 0 — address instruction for t) Write RUL tor fetch, indirect and interrupt cucles, 4) Describe the basic ALU with ite ‘ operational truth table, b) Draw Booth multiplication algorithm and perform multiplication between 5 and -6. =(A *B CY (EF) using 3,2. rat, functional block diagram and a) Design 2 bit array multiplier using combinational logic. b) Explain the operation of microprogram tnictoprogramming CU with its block diagram Draw memory hierarchy with their relative characteristics and differentiate between SRAM and DRAM. Describe the principle of associative cache mapping with its merits and demerits. sequencer used in »} 5a) Explain DMA with flowchart and interconnection of DMA controller ‘ices. ‘with processor, memory and I/O devie . sarang 5) Explain the major characteristics of CISC with its wacng esr 3) Describe different interconnection structures in : system. +e famille Eom 5) Describe hardware performance issues in mult Waite short notes on: (Any two) ®) Hardwired CU °) Array Processor ° Control Hazard in Instruction Pipeline *) 2x5“SERSITy 1 el; Bachelor Semester; Fall amme: BE y progtatt ter Archit eet 2017 course Computer Architecture. Full Macks: 100 Pass Marks: 45 ime; Candidates are required to * Shs. ive thei 81Ve their answers in their own words she figures in the margin indicate ful marks Attempt all the questions, : a practicable. as far 3) The terms “computer architect s ture” and an sume or diferent, explain with examplay, "PU eeanizaion” are 7 ) Define RTL. Describe differen ee tears t types of Shift micro-operations. ow cycle, explain instruction cycle state diagram with ») Multiply using Booth’s Algorithm: (-11)10*(15)i0 8 Describe ac algorithm used for the division of signed numbers. Find 8 the result of (-9)10 divided by (2),ousing same algorithm. Explain hardwired implementation of control unit. List out advantages 7 of using hardwired control unit. What is micro instruction sequencing? Explain single address field and variable format sequencing techniques used in micro-programmed implementation of control unit. 8 How can use of cache memory improve performance in any computer , aii gear in cache. system? Explain set-associative and direct mapping in ; ; 2) Define locality of reference. Differentiate between Static and Dynamic RAM. ver mod 8 Define DMA. Explain DMA transfer modes, ; ba a SC systems. ‘ 8 bryce wi be ni 4) Multi-core organization ) Parallelism in Uniprocessor Sys Register windowsramme: ‘ a : st Computer Architecture Bull Makan Pass Macks: 4 Pa 5 ea , Time + Shes, cones are required to give their answers tn the’, coe their own words as far ‘me figures in the margin indicate ull marks Attempt all the questions, 3) What is stored program Concept, computer. ty What is register in computer system? ah ae registers used in computer system, Explain diferent Syees} of 4) Perforn multiplication of -5*2, b) Explain working principle of micro-programmed implementation of control unit. Why it is slower th explain with reference to IAS A han hardwired implementation of control unit. a) Explain single address field and two address field sequencing techniques used in micro-programmed implementation of control unit. b) What is associative memory? Explain hardware organization of associative memory. 4 a) How redundancy is achieved in RAID, explain with any wo RAID levels. _— b) Explain the input output module in computer system along with its Block diagram, also write its importance. ., 7 5a) Mention the need of use of large register file in RISC. Explain overlapping register windows in RISC with example bd) al 3 ja ith What is pipelining hazards? Explain structural and dats hazard wi solutions ith its gereral block diagrams 4) Explain Flynn's classification, along with its Bie Of solving cache >) What is cache coherence? Explain any 0 " E coherence problem. Write short notes on: (Any two) a) OM hierarchy ister Transfer Language ar ‘) Dual core and Quad core proc’ o) 246 542Po KHARA UNIVERSity Level: Bachelor Sey " programme: BE Mester: aly ¥ Course: Computer Architecture Bull, i 018 arks: 100 88S Marks: 45, Candidates are reqi ans Shrs, The figures in the margin indicate fu fll Attempt all the questions, marks a) Explain different sta, 6) Explain instruction eyete state di it Nagram in a) How overflow be detected i mere b) Compare and Contrast between " ‘ r micro-program and hardwired control ‘nit. Explain the micro program sequencer with example, a) What is interrupt cycle? Explain how instruction be processed with | interrupt in computer along with necessary diagram. What is m-way interleaving? Explain different types of memory imerleaving. b) a) Consider a system with main memory (MM) consisting of 8K blocks, a cache memory consisting of 256 blocks and a block size of 16 words- what will be the word field, block filed and Tag field length? How many bits are there in main memory address? If the system uses i i i ng techniques. direct mapping and associative mapping, : ; , b) What ak te drawbacks of programmed VO and interrupt driven YO Explain hor DMA overcomes those dae: acini its ta 4) Assume that pipeline has K-8 Ee a sul-operaton in each is to pros i Sealefiog. “Let ihe Sine “ a up ratio in the pipeline : segment is 30 sec. Calculate theses vesormane Tse re Seni and softw b) What type of hardware and so in. multi-core computers? Explaites in multiprocessors. ection structttr ; Explain MES! protocol Res a) Explain different interconn problem? b) What is cache coherence solving cache coherence problem. Write short notes on: (Any Ovo} a) RISC vs. CISC b) Hardware Description language (HDL) ¢) Logic MicrooperationPOKHARA UNIVERSITY evel: Bachelor Semester: Spring Year: 2018 ramme: BE s ; piel Computer Architecture Pein a ‘Time + Shrs. Candidates are required to give their answers in their own words as far cs practicable. The figures in the margin indicate full marks. ‘Antempt all the questions. _ 3) What are the characteristics of computer system? Draw and explain the basic computer organization in detail. 4) What is RTL? Explain it when data transfer takes place between one and four bit register. 1 a) How a floating point number is represented in computer system? Verify the operation (9) x (-2) using signed magnitude data t) What is sequencer? Draw and explain the micro programmed control unit in detail. 3) What is instruction cycle? Write the necessary micro-operations for fetch, decode, indirect and interrupt cycles. b) What is mapping? What are the different cache memory mapping technique? a) What is DMA? Explain why DMA is used instead of interrupt driven and programmed /0? b) What is instruction pipeline? Explain 3-segment instruction pipelining, used in RISC computer. 3) How a computer system can be classified according to flyn’s? Design an arithmetic pipeline to speed up the computer to solve the expression Ay y+ Dj for i=0, 1,2,3,4. b) What are the function of ISR? Explain how interrupt are processed in computer system. ®) How floating point number can be added or subtracted using ipelining i » Bint sin seus wen oe maiCPUs? Write short notes on: (Any two) a) Alternative Chip Organization b) Types of registers | c) Control memory organization and mapping logicPOKHARA UNIVERSITy evel: Bachelor Semester: Fal amme: BE ! roe ver 22019 , Computer Architecture ‘ull Marks: 100 couse Pass Marks: 45 Time + Shrs. sundidates are required to give their ves co tate re Unswers in their own words as far the figures in the margin indicate full marks, Astempt all the questions. Tiptree NN ee each component. ») How data can be transferred between registers? Explain in detail 7 3} Describe the arithmetic and logic circuit with its appropriate block 7 diagram. b) Multiply (14)io and (3)\o using unsigned binary multiplication method = 8 with data flow diagram. 3) Perform (-5) *(-3) using the Booth multiplication algorithm, 4) Compare single and two address field addressing techniques used in 7 micro-programimed implementation of control unit, 3) Does hardwired implementation of Control Unit makes control unit & fast. or slow explain? Mention disadvantages of Hardwired implementation. 5) What is ive memory? How match logic works for associative 7 memory? 3) Define DMA. Explain DMA controller with different DMA transfer» 7 modes. : >) Explain the advantages of pipelining in the multiprocessor system. Deseribe the instruction pipeline with examples. ’) Why cache coherency occur in multiprocessor system? What are the 8B various ways to troubleshoot the problem? , Explain Flynn's classification of computer system a Write short notes on: (Any two) +) Optical disk °) RISC vs cise ‘) Multi Core OrganizationLevel: Bachelor % Programme: BE Mester: Sing Course: Computer Archite ture ts a2 \ Pass Marks: 45 Candidates are required io gig Te SS a roel * their answers ig their oy The figures in the margin indict "Words as far Attempt all the Questions, I marks, |. 3) Explain the different evohuti i computer system, tionary milestones in development of b) What are the different types of repi: i explain with examples, 7 OF tier use in computer system, a) Write the algorithm and perform multiplicati 5 : tip | algeathee plication of 9¢. b) Differentiate between micro Programmed contol and hardwired control unit? What are the techniques used tw microinstructions. -3 using booth sequence What is instruction ¢ycle? Explain various sub cycle of instruction cycle with micro-instructions involved in each sub cycle. | Define virtual memory. Explain address mapping using pages in virtual memory. | c 4) Explain how redundancy is obtained in ee reference to any Seal tevels yal 2 ie ae cme address is calculated in 5) Explain with an example, how effecti AS cae eden Direct, Register indirect, Relative and Index (Assume necessary data if you see) iabaefe *) What is mean by pipelining? Exp! > Explain me 5) What is cache coherence problem coherence problem. u don 2) What ae ihe various interconnected str System? Explain them. Briefly explain the different Pe ‘hort notes on: (Any ee) Register Transfer Late Future trends Sorapurss tnstruction pipelining out RISC pipelining? hads of solving cache 1 used for multiprocessor mance issues (HDL)POKHARA UNIVERSITY ; Level: Bachelor Semester : Spring Programme: BE Course: Computer Architecture Year 12023 Full Marks: 100 Pass Marks: 45 Time hrs. Candidates are required to give their answers in their own words as far as practicable, & The figures in the margin indicate full marks. ~~ Attempt all the questions, Si \. a) Differentiate between Computer Organization and Computer bs Architecture, Explain the functional view of the computer with reference to each component. b) Define RTL. Explain about Bus and Register transfers in RTL. 2, a) Explain different types of registers used in Computer System with examples. What is the use of registers in Computer System? b) Perform -15 *6 using Booth's algorithm. 3. a) Explain the restoring division algorithm with flowehart ») Explain the working principle of Micro-programmed implementation of control unit. Why is it slower than Hardwired Control Unit? 4, a) What is associative memory? How read /write operation takes place in associative memory? b) As we know cache memory size is smaller than main memory, how is it possible to map main memory data into cache memory? Explain in detail, a) How Interrupt driven V/O differ from programma VO? Explain with necessary diagram.” >) How instruction pipeli ing supports in parallelism? Explain, 6. a) Cache coherence problem arise in multiprocessor system and must be resolved. Justify this statement, b) What are the performance issues that arise in multicore computers? Write short notes on: (Any fo) a) Control unit. ) RISC VS CISC ©) Flynn's ClassificationPOKHARA UNIVERSITY Level: Bachelor ‘Semester: Fall Programme: BE Course: Computer Architecture Year Candidates are required to give their answers in their own words as as practicable. The figures in the margin indicate full marks. Attempt all the questions. 1. a) Discuss the term Computer Architecture. Explain IAS computer 8 architecture with detailed diagram. b) Define addressing mode. Explain different addressing modes with 7 appropriate figures and example of each. 2. a) Define RTL. How data can be transferred between registers. Explain. 8 b) Define Instruction cycle. What are the different states in an instruction 8 cycle? Also explain fetch cycle, decode cycle, execute cycle and indirect cycle. 3. a) Draw the flowchart for Booth’s Algorithm. Use the alg binary multiplication of (-12) and (-9). b) Explain single and two address field sequencing techniques in micro 7 programmed control unit. rithm for 8 4. a) Differentiate between Hardwired and Micro-programmed control unit 7 Explain the logic of Hardwired unit. b) What is memory hierarchy? Explain with reason why do we need 7 multilevel memory hierarchy? 5. a) Explain various communication techniques for V/O devices. 8 5) Differentiate between various mapping techniques when main memory 7 data is to be mapped into cache memory. What is power efficient processor? Ex; respect to quad core processor. 5) Describe in brief about Flynn's Taxonomy. Parallelism can be experienced in uniprocessor syst Write short notes on: (Any two) Ds a) RISC vs. Cisc ¥) Vector processors and Array processors 2) BED Asder 6. a) plain dual core processor with 8 Also explain how 7 ems.POKHARA UNIVERSITY Level: Bachelor Semester: Fall Year 22021 Programme: BE Full Marks: 100 Course: Computer Architecture Pass Marks: 45 Time =: 3hrs. Candidates are required to give their answers in their own words ee as far as practicable. Fe The figures in the margin indicate full marks. [ea Attempt all the questions. 2) Define Computer Architecture and Computer Organization. What is HDL and what are its advantages? b) What is addressing mode? Explain about different types of addressing 9 modes. 2. a) What is CPU organization? Explain register organization in details. 8 b) What is ALU? Design a 2-bit ALU that can perform AND, OR & 7 ADD operations. ‘What is Booths algorithm in computer Architecture? Exp! What is associative memory? How read write operation is performed 7 . in associative memory? 6 : Draw the block diagram of micro programmed control unit and explain it. What the drawbacks are of interrupt driven and programmed 0? 9 How DMA overcomes it? Explain. Explain DMA transfer in a Computer system with necessary 6 diagram. F ¢ Compare RISC and CISC Architecture, Describe Flynn's 9 ¢ classification. i { Show that the speedup factor for pipelined processor is equal t0 the number of stages in a pipeline. What is cache mapping? Explain cache rep! suitable example. Jacement algorithm with a §7. Write short notes on: (Any two) a) RAID b) Hardware performance issues in multicore systems c) Pipelining Conflicts