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COURSE PLAN
For
Fundamentals of Microprocessor and
Computer Architecture
(CBCA106)

Faculty Name : Ishan Budhiraja

Course Type : Core

Semester and Year : II Semester and I Year

L-T-P : 2-0-2

Credits :3

Department : Computer Science Engineering

Course Level : UG

Degree : BCA

SCHOOL OF COMPUTER SCIENCE ENGINEERING AND

TECHNOLOGY

Department of Computer Science Engineering

Bennett University
Greater Noida, Uttar Pradesh
COURSE CONTEXT
VERSION NO. OF
CURRICULUM/SYLLABUS
SCHOOL SCSET V1
THAT THIS COURSE IS A
PART OF
DATE THIS COURSE WILL BE
DEPARTMENT CSE Jul-Dec, 2020
EFFECTIVE FROM
VERSION NUMBER OF
DEGREE BCA 2
THIS COURSE

COURSE BRIEF
Fundamentals of
COURSE TITLE Microprocessor and Computer PRE-REQUISITES NA
Architecture
COURSE CODE CBCA106 TOTAL CREDITS 3
COURSE TYPE Core L-T-P FORMAT 2-0-2

COURSE SUMMARY
ALU, Instruction set, CPU design, Micro-operation and their RTL specification, CPU-
memory interaction, I/O processing, Programmed controlled I/O transfer, Interrupt controlled
I/O transfer, DMA controller, RISC and CISC paradigm, to pipelining and pipeline hazards,
design issues of pipeline architecture, interconnection networks, Multiprocessors and its
characteristics, models of memory consistency Architecture of Microprocessors, Overview of
microprocessor, Signals and pins of microprocessor, Assembly language and interfacing with
microprocessor.

COURSE-SPECIFIC LEARNING OUTCOMES (CO)

By the end of this program, students should have the following knowledge, skills and values:
CO1: Understand about modern architecture and microprocessors and the design techniques.
CO2: Evaluate various design alternative of computer architecture based on CPU
performance, memory, I/O.
CO3: Understand instruction sets and implement with assembly programme and design
application specific processor using HDL.

How are the above COs aligned with the Program-Specific Objectives (POs) of the degree?
The course outcomes are aligned to inculcating inquisitiveness in understanding cutting edge
areas of computer science engineering and allied disciplines with their potential impacts.

CO-PO MAPPING
COs PO1 PO2 PO3 PO4 PO5 PO6
POs
CO1
CO2
CO3
 CBCA106 – Fundamentals of Microprocessor and
Computer Architecture
Course Type - Core L-T-P Format 2-0-2 Credits – 3
DETAILED SYLLABUS
Module 1 (Contact hours: 14)

Why Microprocessor and Computer Architecture, Microprocessor Architecture, CPU

Registers, Segment Registers, General Purpose Registers, Bus Interface Unit, Address bus,
data bus and control bus, Control Unit, ALU, Memory unit, Architectural overview and
comparison between 32-bit and 64- bit processor, Microprocessor Pin Configuration, AI
Processor, Comparison of AI Processor with regular Microprocessor, ARM processor
Architecture, Instruction Set Architecture, Instruction interpretation and execution,
Addressing Modes, Immediate, Direct, Indirect, PC-relative, Indexed, Arithmetic and logic
unit, Register configuration of Signed Magnitude Addition-Subtraction Algorithm, Register
configuration of 2’s complement Addition Subtraction Algorithm, Signed Magnitude
Multiplication Algorithm, Booth’s multiplication algorithm.

Module 2 (Contact hours: 14)

CPU – Memory interconnections, Organization of memory modules, Principle of locality,

Cache Memory, Cache Memory Mapping Techniques, Associative, Direct, Set Associative,
Case Studies, Input/Output techniques, Programmed controlled I/O transfer, Interrupt
controlled I/O transfer, Different types of Interrupts, DMA controller, Secondary Storage –
solid-state drive (SSD), Comparison of SSD with HDD, Pipelining, pipeline hazards,
Instruction level parallelism and advanced issues, RISC and CISC paradigm, Design issues of
a RISC processor, Multiprocessor system and its characteristics.

STUDIO WORK / LABORATORY EXPERIMENTS:

Designing of various components (Adder, Subtractor, Comparator, Logical Operation, MUX,
DEMUX, Register) of 16-bit ALU, Integrate all the components designed in Lab1 and
prepare a functional ALU using FPGA, Introduction to Assembly Language programming
with MARS Simulator, Implementation of different Arithmetic operations in MARS
Simulator, Taking user input in Assembly code, MIPS Logical, Conditional and
Unconditional branch Instructions, String Handling in MIPS, taking user string input from
user at runtime, Subroutine handling, Assembly loop control structure, Array Declaration in
MIPS Simulator, Floating point number representations in MIPS, Application of Cache
Simulator in MIPS.

TEXTBOOKS/LEARNING RESOURCES:
1) J. L. Hennessy and D. A. Patterson, Computer Architecture: A Quantitative Approach
(6th ed.), Morgan Kaufmann, 2017. ISBN: 978-0128119051.
2) Douglas V. Hall, Microprocessors and Interfacing (3rd ed.), McGraw Hill
Education, 2017. ISBN 978- 1259006159.
 REFERENCE BOOKS/LEARNING RESOURCES:
1) William Stallings, Computer Organization and Architecture (11th Edition), Pearson,
2018. ISBN: 978-0134997193.

TEACHING-LEARNING STRATEGIES
The course will be taught using a combination of the best practices of teaching-learning.
Multiple environments will be used to enhance the outcomes such as seminar, self-learning,
MOOCs, group discussions and ICT based tools for class participation along with the
classroom sessions. The teaching pedagogy being followed includes more exposure to hands-
on experiment and practical implementations done in the lab sessions. To match with the
latest trend in academics, case study, advanced topics and research-oriented topics are
covered to lay down the foundation and develop the interest in the students leading to further
exploration of the related topics. To make the students aware of the industry trends, one
session of expert lecture will be organized to provide a platform to the students for
understanding the relevant industry needs.

EVALUATION POLICY
Components of Course Evaluation Percentage
Mid Term Examination 15
End Term Examination 35
Lab Continuous Evaluation 30
Surprise Class Quiz 20

LECTURE WISE PLAN

Lectur Content Planned Content Delivered
e No.
1 Course structure/handout Assessment mechanism (20)
Why Microprocessor and Computer Architecture (25)
2 Microprocessor Architecture (20)
CPU Registers, Segment Registers, General Purpose
Registers (25)
3 Bus Interface Unit (20)
Address bus, data bus and control bus (25)
4 Control Unit, ALU, Memory unit (30)
Architectural overview and comparison between 32-bit and
64-bit processor (20)
5 Microprocessor Pin Configuration (45)
6 Microcontroller (30)
Comparison with microprocessor (15)
7 AI Processor (20)
Comparison of AI Processor with regular Microprocessor
(30)
8 ARM processor Architecture (45)
9 Instruction Set Architecture (20)
Instruction interpretation and execution (30)
10 MIPS Instructions format (20)
ARM – Instruction Set Architecture (30)
11 Addressing Modes (10)
Immediate (10)
Direct (10)
Indirect (10)
PC-relative, Indexed (10)
12 Arithmetic and logic unit (10)
Register configuration of Signed Magnitude Addition-
Subtraction Algorithm (35)
13 Register configuration of 2’s complement Addition
Subtraction Algorithm (45)
14 Signed Magnitude Multiplication Algorithm (20)
Booth’s multiplication algorithm (30)
15 CPU – Memory interconnections (35)
Organization of memory modules (10)
16 Associative memory (45)
17 Principle of locality (15)
Cache Memory (30)
18 Cache Memory Mapping Techniques (10)
Associative (15)
Direct (15)
Set Associative (15)
19 Interfacing of memory chips (25)
Address allocation technique and decoding (25)
20 Interfacing of I/O devices (15)
LEDs toggle-switches as examples (10)
Memory mapped and isolated I/O structure (25)
21 Input/Output techniques (20)
Programmed controlled I/O transfer (30)
22 Interrupt controlled I/O transfer (20)
Different types of Interrupts (30)
23 DMA controller (45)
24 Secondary Storage – solid-state drive (SSD) (30)
Comparison of SSD with HDD (20)
25 Pipelining (30)
Pipeline hazards (20)
26 Design issues of pipeline architecture (45)
27 Instruction level parallelism and advanced issues (20)
RISC and CISC paradigm (30)
28 Design issues of a RISC processor (30)
Multiprocessor system and its characteristics (15)
29 Advance Research Topics in Microprocessor (50)
30 Assessment 2 /Expert Lecture/ Buffer Lecture*
 End-Term-Exam
* Assessment, expert lecture dates are tentative. Course coordinator may schedule it as per need.

LAB WISE PLAN

Lab No. Lab Assignment Lab Delivered
1 Designing of various components (Adder, Subtractor, Comparator,
Logical Operation, MUX, DEMUX, Register) of 16-bit ALU
2 Introduction to Assembly Language programming with MARS
Simulator
3 Implementation of different Arithmetic operations in MARS Simulator
4 Taking user input in Assembly code, MIPS Logical
5 Conditional and Unconditional branch Instructions
6 Mid-Term Lab Exam
7 String Handling in MIPS, taking user string input from user at runtime
8 Subroutine handling, Assembly loop control structure
9 Array Declaration in MIPS Simulator
10 Floating point number representations in MIPS
11. Application of Cache Simulator in MIPS
12 Buffer
13. End-Term Lab Exam
14. End-Term Lab Exam

MOOC COURSES
1) https://nptel.ac.in/courses/108107029
2) https://nptel.ac.in/courses/108103157
3) https://nptel.ac.in/courses/106105163

Expert talk plan

S. No Talk Title Resource Person Company
1 Talk-1 (After 1st Module) Mr. Deepak Samant ST Microelectronics
2 Talk-2 (After 2nd Module) Mr. Karim Khan Magneti Marelli

Suggest at least 3 innovations how this will enhance

learning outcome of the course.
1) Apart from the regular syllabus, some latest microprocessor chips, like Qualcomm
snapdragon, apple, Exynos, MediaTek will be taught thus students get familiarize
with the latest microprocessor chips which are used in widely used smartphones and
other electronic gadgets.
2) Three different tools will be introduced in Lab thus students gain idea on basic
assembly programming as well as the latest techniques in relevant area.
 3) One short project purely on microcontroller programming will be done by the
students as project competition which will increase their hands-on experience on
assembly programming.

Tentative Date for hackathon/Longathon.

Second Week of April.

Tentative date/speaker for industry talk.

First Week of March and April.

List tools (teaching and lab) that can be used in course.

Acadly, Mentimeter, Logisim, MARS, and Gem5.

Course Details and Lecture Videos

Make a 2-5 min video to introduce your course (overall what you will teach, why this
course is important, industrial application, how this course will be support students’
future plans, i.e., placement, business setup, others), make a YouTube playlist where
first video will be your introductory video of the course. Share the playlist link.
Record every lecture and upload in this playlist.

To be Filled each Semester

1) Relevant MOOC Courses being Referred: Yes
2) Probable Case Studies: Yes
3) Advanced Research Topics: NA
4) Start-ups to be discussed: Yes
5) Assessment Components Details: Yes
6) Software required: Logisim and MARS
7) Hardware required: A machine with good configuration having Windows 10.
8) Industry/certificate mapping: Yes