ECE1393F Sept. 18, 2004 ECE1393F Sept.

18, 2004

2.4 Short Channel Effects

X Short channel effects are more apparent when the
2. Small Geometry MOSFETs channel length L is comparable to the junction depth
XJ of the source and drain diffusion.
VDS
VGS IDS
Wai Tung Ng
VS = 0V XJ
Associate Professor
TOX
University of Toronto
Electrical & Computer Engineering
Toronto Ontario n+ n+
Canada M5S 3G4
LEFF ΔL
LD
Tel: (416) 978-6249 L W
p-Si
E-mail: ngwt@vrg.utoronto.ca

University of Toronto 2-1 University of Toronto 2-2

ECE1393F Sept. 18, 2004 ECE1393F Sept. 18, 2004

X One of the distinctive feature of the IV Channel Length Modulation

characteristics for short channel device is that the
X The depletion-layer under the n+ drain junction is
drain current increase with VDS — large gds.
a function of VDS. Assuming an abrupt junction,
2ε s ε 0 (φ + VDS )
xd =
qNSUB
X The depletion charge is

Qd = −qxd NSUB = − 2qε s ε 0NSUB (φ + VDS )

X The depletion-layer extends both vertically and
horizontally. The horizontal (or lateral) extension
reduces the channel length by a length of ΔL.

University of Toronto 2-3 University of Toronto 2-4

1
ECE1393F Sept. 18, 2004 ECE1393F Sept. 18, 2004

X Since the depletion layer depends on VDS, the X IDS,sat is the drain current at the onset of
effective channel length also varies with VDS. saturation, with VDS = VDS,sat .
X The output conductance (important in determining
2ε s ε 0
ΔL =
qNSUB
( φ + VDS,sat + ΔVDS − φ + VDS,sat ) the gain), gds is the slope of the IV curve.

X Where VDS,sat is the voltage at which the device first

IDS
enters the saturation region.
X As the effective channel length reduces and the
drain current increases
IDS,sat slope = gds
Leff = L − ΔL
IDS L L
= =
IDS,sat Leff L − ΔL
0 VDS
University of Toronto 2-5 University of Toronto 2-6

ECE1393F Sept. 18, 2004 ECE1393F Sept. 18, 2004

X Subthreshold conduction — substantial X As the channel length reduces, the parasitic bipolar
leakage current occurs for short L. The subthreshold transistor behavior starts to dominate.
current varies exponentially with VGS. X Subthreshold current is caused by carrier diffusion
from source to the drain.
Source Drain
Isub = Is (e −qVSB kT − e −qVDB kT ) Gate
X where
n + p o ly

μ WCoxγ ( kT q )2 q (ψ sw −2φf ) kT n+ n+
Is = n e
2 ψ sw L
p-substrate
⎡ 1 2 ⎤2
γ ⎛γ 2 ⎞
ψ sw = ⎢ − + ⎜ + VGB − VFB ⎟ ⎥ 2qε sε 0Nsub
⎢ 2 ⎝ 4 ⎠ ⎥ γ ≡
⎣ ⎦ Cox

University of Toronto 2-7 University of Toronto 2-8

2
ECE1393F Sept. 18, 2004 ECE1393F Sept. 18, 2004

Threshold Voltage Variations X Assuming that part of the depletion charge is shared
X The threshold voltage does not remain constant if by the source and drain depletion regions, the
the dimensions of L and W are reduced. geometry should be trapezoidal (not rectangular).
X The equations developed previously are based on LEFF + L '
'
Qbulk = QdW
the fact that all the depletion charge is due to the 2
gate bias. VGS
Q Q
VTH = Φ ms − i − d + 2φF VS = 0V VD = small
Cox Cox
n+ poly-Si
X The total charge contributing to the inversion under
the gate terminal is Qbulk = W × L × Qd. n+ xdm n+ XJ
X This is calculated based on a rectangular geometry,
L'
without taking account for the influence due to the
depletion region from the source and drain. LEFF p-Si

University of Toronto 2-9 University of Toronto 2-10

ECE1393F Sept. 18, 2004 ECE1393F Sept. 18, 2004

X Comparing to Qbulk, it is important to determine the X Similar analysis for narrow W devices can also lead
factor LEFF + L’/2LEFF, which can be proved to be to an expression for threshold voltage is a function of
W, XJ, and NSUB.
LEFF + L ' ⎛ 2x ⎞ X
= 1 − ⎜ 1 + dm − 1⎟ J X If VDS is large, the depletion region will no longer be a
2LEFF ⎝ XJ ⎠ LEFF trapezoid, but instead will become a polygon. In this
case, the threshold voltage will also be a function of
X The proper equation for the threshold voltage is now VDS.
a function of LEFF, XJ, and NSUB.

Qi Q ⎡ ⎛ 2 xdm ⎞ X ⎤
VTH = Φ ms − + 2φF − d ⎢1 − ⎜ 1 + − 1⎟ J ⎥
Cox Cox ⎣⎢ ⎝ XJ ⎠ LEFF ⎦⎥

University of Toronto 2-11 University of Toronto 2-12

3
ECE1393F Sept. 18, 2004 ECE1393F Sept. 18, 2004

X The threshold voltage VTH is as a function of the X As the channel length reduces, the threshold
channel length L. voltage VTH approaches 0V.
Threshold Voltage of NMOS Devices Threshold Voltage of PMOS Devices

University of Toronto 2-13 University of Toronto 2-14

ECE1393F Sept. 18, 2004 ECE1393F Sept. 18, 2004

X A Typical CMOS process flow

7. High Resistor Mask IM (Dark, Align to TO) 10. P+ implant Mask SP (Clear, Align to TO)
1. N-well Mask TB 4. P-Implant Mask NF (reverse of N-well, same as PT)

SiO2 SiO2 SiO2 SiO2 SiO2 SiO2

p+ p+ n+ p+ n+ n+
p-well p-well
p-well p-well p-well
n-well p-field implant p-well n-well n-well
n-well

p-substrate p-substrate p-substrate

p-substrate

8. Poly 2 Mask PC (Dark, Align to TO) 11. Contact Mask W1 (Clear, Align to GT,TO)
2. P-well Mask PT (reverse of N-well mask, Align to TB) 5. N+ Code Mask RO (for Depletion mode, Align to TO)

SiO2 SiO2 SiO2 SiO2 SiO2 SiO2

SiO2 SiO2 SiO2 p+ p+ n+ p+ n+ n+
p-well p-well
p-well p-well p-well p-well
p-well p-well n-well n-well
n-well n-well

p-substrate p-substrate
p-substrate p-substrate

9. N+ implant Mask SN (Clear, Align to TO) 12. Metal 1 Mask A1 (Dark, Align to W1)
3. Active Mask TO (Dark, Align to TB) 6. Poly 1 Mask GT (Dark, Align to TO)

Si3N4 Si3N4
SiO2 SiO2 SiO2 SiO2 SiO2 SiO2
SiO2 SiO2 SiO2 n+ n+ n+ p+ p+ n+ p+ n+ n+
p-well p-well
p-well p-well p-well p-well
p-well p-well n-well n-well
n-well n-well

p-substrate p-substrate
p-substrate p-substrate

University of Toronto 2-15 University of Toronto 2-16

4
ECE1393F Sept. 18, 2004

13. Via Mask W2 (Clear, Align to A1)

SiO2
p+ p+ n+
SiO2
p+ n+ n+
SiO2
Taking Silicon to the Limit
p-well
n-well
p-well
Challenges and Opportunities
p-substrate

14. Metal 2 Mask A2 (Dark, Align to W2)

Tsu-Jae King
SiO2 SiO2 SiO2
p-well
p+ p+ n+ p+ n+
p-well
n+
Department of Electrical Engineering and Computer Sciences
n-well

p-substrate
University of California, Berkeley, CA 94720 USA
15. Pad Mask CP (Clear, Align to A2)
Advanced Technology Group
Synopsys, Inc., Mountain View, CA USA
SiO2 SiO2 SiO2
p+ p+ n+ p+ n+ n+
p-well
p-well
n-well
October 19, 2004
p-substrate

University of Toronto 2-17 2004 ICSICT

Outline IC Technology Advancement

Rapid advances in IC technology have been achieved
z Introduction largely by scaling down transistor lateral dimensions
ƒ ITRS 2003 Technology Scaling
M. Bohr, Intel Developer
Forum, September 2004

ƒ Challenges for MOSFET scaling SMIC’s Fab 4 (Beijing, China)

Photo by L.R. Huang, DigiTimes
ITRS 2003 Projection
z Thin-body transistor structures Investment Better Performance/Cost 100

GATE LENGTH (nm)

z Advanced CMOS materials Market Growth
10

z Performance enhancement approaches

LOW POWER
HIGH PERFORMANCE
z Summary 1
2000 2005 2010 2015 2020
YEAR

T.-J. King, 10/19/04 19 T.-J. King, 10/19/04 20

5
 Intel’s 90 nm CMOS Technology CMOS Technology Evolution
Information Age UbiComp Age
internet portable & wireless
T. Ghani et al., ng
al c omputi 65nm
person
presented at the Int’l Electron Devices Mtg. 32nm?
(San Francisco, CA) Dec. ‘03 130nm
0.25μm
Used for volume manufacture of 0.5μm
tensile strain Æ 10% Idsat increase
Pentium® and Intel®CentrinoTM
processors on 300 mm wafers 1μm
ƒ Lg = 45 nm
ƒ Tox = 1.2 nm
ƒ Strained Si channel
compressive strain Æ 30% Idsat increase Year 2004 2005 2006 2007 2010 2013 2016
Technology 90 80 70 65 45 32 22
nm nm nm nm nm nm nm
Source: The Economist Node Acknowledgement: Jamil Kawa
Tox Solutions Being No Known
T.-J. King, 10/19/04 21 T.-J. King, 10/19/04 22
Idsat Pursued Solutions

Issues for Scaling Lg to <20nm Outline

Lg
Metal-Oxide-Semiconductor
Tox z Introduction
Field-Effect Transistor:
Gate
z Leakage z Thin-body transistor structures
ƒ drain current Source Xj Drain
ƒ Ultra-thin-body (UTB) MOSFET
Leff
ƒ gate current Substrate Nsub
ƒ Double-gate (DG) MOSFET
ƒ Back-gated UTB FET
z Incommensurate gains in Idsat with scaling
ƒ limited carrier mobilities z Advanced CMOS materials
ƒ parasitic resistance SiO2 Gate

z Performance enhancement approaches

z VT variation Source Drain
A. Brown et al., IEEE Trans. Nanotechnology, p. 195, 2002 z Summary
T.-J. King, 10/19/04 23 T.-J. King, 10/19/04 24

6
 Ultra-Thin-Body MOSFET 20 nm Lg UTB CMOSFETs
z UTB suppresses leakage ƒ Lg = 12 nm Krivokapic et al. (AMD),
z Thick S/D => low Rseries ƒ Tox = 2 nm presented at the Int’l Conference on
Solid-State Devices and Materials
Simulated Id -Vg (Tokyo, Japan) Sep. ’03.
1.E-02

Drain Current [A/um]

Vds=1V • TSi = 6 nm
Gate
1.E-04
Source SOI Drain • Tox = 1.3 nm (SiO2/Si3N4)
1.E-06 Subthreshold swing
SiO2 S (units: mV/dec) • Strained Si channel
1.E-08
Tsi=8nm
Silicon Substrate
1.E-10 Tsi=6nm
Tsi=4nm
M. Takamiya et al., Proc. 1997 ISDRS, p. 215 1.E-12
B. Yu et al., Proc. 1997 ISDRS, p. 623 0 0.2 0.4 0.6 0.8 1 ƒ High Idsat is achieved with thick S/D structure
Gate Voltage [V]
T.-J. King, 10/19/04 25 T.-J. King, 10/19/04 26

UTB MOSFET Scaling Double-Gate “FinFET”

z Issues for bulk-Si MOSFET scaling eliminated z Self-aligned gates straddle thin silicon fin
ƒ Body does not need to be heavily doped z Current flows parallel to wafer surface
ƒ Tox does not need to be scaled as aggressively Gate Length = Lg
Gate
z Body thickness must be less than ~1/3 x Lg

Source
ƒ Formation of uniformly thin body is primary challenge Gate 2
ƒ For TSi < 4 nm, quantum confinement & interface
roughness Æ VT variation and degraded gm Gate 1 Source Drain
K. Uchida et al., IEDM Technical Digest, pp. 805-808, 2002 “Silicon on Nothing” Process Current

Drain
ÆScaling limit may be Lg ≅ 12 nm, Flow
unless uniformly thin TSi and atomically Fin Height = Hfin = W
smooth interfaces are achieved,
e.g. by epitaxial growth of the Si channel Fin Width Wfin = TSi
M. Jurzcak et al., IEEE Trans. Electron Devices, pp. 2179-2187, 2000

T.-J. King, 10/19/04 27 T.-J. King, 10/19/04 28

7
 GATE 20 nm

Impact of FinFET Orientation 15 nm Lg FinFETs

DRAIN

10 nm

L. Chang et al., IEEE Trans. Electron Devices, Vol. 51, p. 1621, 2004 SOURCE

TSi = 10 nm; Tox = 2.1 nm

Sub-Threshold Characteristics Output Characteristics

Drain Current, Id[uA/um]

-2 -2

Drain Current, Id [A/um]

10 10 600 600
D (100) Vd=-1.0 V P+Si0.4Ge0.6 Vd=1.0 V
Hole D PMOS |Vg-Vt|=1.2V NMOS
S -4 Gate -4 500 500
Mobility 10 10
(110)
S Vd=-0.05 V Vd=0.05 V 400 400
(100) 10
-6
10
-6 Voltage step
NMOS 300 : 0.2V 300
(110) -8 N-body= -8
D 10 10
PMOS 18
2x10 cm
-3
200 200
-10 -10
S 10 10 100 100
Electron (110) D NMOS
S PMOS
Mobility (100) 10
-12
10
-12
0 0
-1.0 -0.5 0.0 0.5 1.0 1.5 2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5
(110) Gate Voltage, Vg [V] Drain Voltage, Vd [V]
(110) Y.-K. Choi et al., IEDM Technical Digest, pp. 421-424, 2001

T.-J. King, 10/19/04 29 T.-J. King, 10/19/04 30

10 nm Lg FinFETs Design for Manufacturability

Cumulative Distribution of CD
SiGe Spacer
Lithography

Gate Drain
z Spacer process can be SOI fins
used to achieve sub- E-Beam

lithographic & uniform TSi BOX Lithography

20 40 60 80
Source NiSi Feature Size [nm]
z Line-edge roughness is Y.-K. Choi et al., IEEE Trans.
Poly-Si
220Å not an issue for FinFET photoresist Electron Devices, 49, p. 436, 2002

SiO2 cap gate lithography

Lg=10nm z FinFETs can be made on

Si Fin bulk-Si wafers
ƒ lower cost
BOX
ƒ good recrystallization of S/D
regions after implantation
B. Yu et al., IEDM Technical Digest, pp. 251-254, 2002
ƒ improved thermal
C.-H. Lee et al., Symp. VLSI
conduction Technology Digest, p. 130, 2004

T.-J. King, 10/19/04 31 T.-J. King, 10/19/04 32

8
 Gate Leakage Reduction FinFET Reliability
Y.-K. Choi et al., IEDM Technical Digest, pp. 177-180, 2004

Stress Bias Condition: Vg=Vd=2.0V

30
z DG-MOSFET

ΔId / Id [%]
Lg=80nm
z Narrower fin (thinner TSi)
provides lower Ig 20
→ improved HC immunity
10
Î Tox can be more
z HC lifetime and oxide
aggressively scaled 0
QBD are also improved

ΔVT / VT [%]
for improved Idsat -10 by smoothening the Si
-20 W fin=18nm Wfin=26nm fin sidewall surfaces (by
W fin=34nm Wfin=42nm H2 annealing)
-30
0 1 2 3
10 10 10 10
Stress Time [sec]
L. Chang et al., IEDM 2001

T.-J. King, 10/19/04 33 T.-J. King, 10/19/04 34

FinFET SONOS Memory Thin-Body FET Design Optimization

z Thin-body structure is attractive for high-density memory S. Balasubramanian et al., 2004 Silicon Nanoelectronics Workshop

Measured Endurance Behavior Gate

3.5
2 bits per cell For a given Lg :
K. H. Yuen et al., IEEE
1 bit per cell
Threshold voltage (V)

3.0
Electron Device Letters,
Tox
2.5
pp. 518-520, 2003 1. Fix Ioff , Tox
P. Xuan et al., IEDM
2.0
TSi Source Drain
(100) device
Technical Digest,
1.5
(110) device 2. Maximize Idsat by
pp. 609-612, 2004 1.0 TBOX
0.5
co-optimizing TSi , Leff , TBOX
0.0
Gate
10 100 1k 10k 100k 1M Idsat optimal
Number of cycles
FinFET SONOS Device Cross-Section Simulated I-V Characteristics Simulated I-V Characteristics
1E+20 Leff

Doping (cm-3)
Poly-Si
1E+18
SCE Rs dominated
dominated
SiO2

30nm 1E+16
0
Si3N4

40nm
Si Leff 1E+14
SiO2

Distance along channel

z For sub-20nm gate lengths, Leff > Lg is optimal.
SiO2 0

Gate voltage (V) (Electrical channel length in OFF state is larger than in the ON state)
T.-J. King, 10/19/04 35 T.-J. King, 10/19/04 36

9
 Impact of S/D Contact Structure Dynamic Voltage Scaling
H. Kam and T.-J. King, 2004 Silicon Nanoelectronics Workshop End Contact

Lgate = 18 nm, Leff = 22 nm S

O
U
G
A D
R
Energy ∝ Dynamic power + Static power
T

E = α CEFF VDD2 + VDDI0 e-(VTH/S)TCYCLE

R A
Wrapped Contact, ρ c = 0 C E I
E N

Wrapped Contact 16% reduction

1200
34% reduction Dynamic supply-voltage (VDD) scaling:
End Contact Top Contact
800 ƒ Reduces dynamic power, but at performance cost
ρc=10-8 Ω-cm2
S
O G ƒ Only option for DG-FET operation
Top Contact U A D
R
400 R
C
T
E A
I
E N

Wrapped Contact Combined VDD & VTH scaling:

0
0 0.1 0.2 0.3 0.4 0.5 0.6 S
9 Lowest energy without performance loss
O G D
U A
R
C
E
T
E
R
A
I ƒ Requires back-gate biasing capability
• Parasitic resistance (& capacitance) will limit Idsat N

T.-J. King, 10/19/04 37 T.-J. King, 10/19/04 38

Back-Gated FETs for Dynamic VT Outline

S. Balasubramanian et al., 2004 SOI Conference

8
Logic depth
Gate area
375 CV/I
2.4 mm2
BG UTB z Introduction
Activity 10%
Energy (nJ)

6
% Core sleep 30% z Thin-body transistor structures
Gate VBG HP DG
Idrain

4
Source Drain z Advanced CMOS materials
Back 2
Gate Vgate ƒ Metal gate technology for thin-body FETs
LP DG
0 ƒ High-κ gate dielectric
0 2 4 6 8
Frequency (GHz)
z Performance enhancement approaches
Back-gated UTB FET spans larger Energy vs. Delay space
ƒ 100× lower leakage in sleep mode z Summary
Æ energy savings without delay penalty

T.-J. King, 10/19/04 39 T.-J. King, 10/19/04 40

10
 Impact of Gate Technology Tunable-ΦM Mo Gate Technology
L. Chang et al., IEDM 2000
P. Ranade et al., IEDM Technical Digest, pp. 363-366, 2002
z Channel doping must be eliminated to achieve high
Idsat and to avoid VT variation due to channel dopant z Effective Φ M can be
fluctuation effects selectively lowered
ÆVT must be adjusted by tuning the gate work function ΦM by N+ implantation
in the range from ~4.5eV to ~5.0eV + thermal annealing
Simulated circuit performance comparison required range
FO4 Inverter Delay [ps]

Lgate=35nm Poly Gate

Mid-gap Gate
10 Metal Gate

0
Anneal time = 15m except for 900oC (15s)
Bulk SG-UTB DG TMo = 15nm

T.-J. King, 10/19/04 41 T.-J. King, 10/19/04 42

N+ S
P
Po

Tunable-ΦM NiSi Gate Technology

olly
y-Si N+

Mo-gated HfO2 FinFETs D

Mo

D. Ha et al., to be presented at IEDM 2004

ΦM can be adjusted
W
Lg J. Kedzierski et al., IEDM 2002 z

-3
TSi by implanting Si
10 W/L=0.6/1.5μm |VDS|=0.05, 1.2V with dopants prior
Drain Current, |IDS| (A/μm)

10
-5 to Ni silicidation:
4.5 eV < ΦM < 4.9 eV
-7 Mo-gate Mo-gate w/ 14N (n+ Si) (p+ Si)
10
(1x1016cm-2)

-9
10 z Potential issues:
-11
- dopant penetration
10
VTH=-0.17V VTH=0.28V - thermal stability
S.Swing=62.9 mV/dec S.Swing=67.5 mV/dec
10
-13 - stress/adhesion
-1.2 -0.9 -0.6 -0.3 0.0 0.3 0.6 0.9 1.2 - gate-oxide reliability
Gate Voltage, VGS (V)

• FinFET gate current is reduced by >103, • ΦM is reduced by N implantation

J. Schaeffer et al., 2004 MRS Spring Meeting
as compared to poly-Si/SiO2 with same EOT Reduction is lower than on SiO2,
(NiSi gate annealed 60s at 700oC)
due to N diffusion into the HfO2

T.-J. King, 10/19/04 43 T.-J. King, 10/19/04 44

11
 Outline Field-Effect Mobility Bulk-Si PMOSFET Ion vs. Ioff
unstrained
z Increased carrier mobility
z Introduction Æ improved Ion / Ioff tradeoff

z Thin-body transistor structures z Mobilities are dependent on: strained

ƒ channel surface orientation
z Advanced CMOS materials & current flow direction
ƒ gate-stack materials & processes
z Performance enhancement approaches
ƒ channel strain P.R. Chidambaram et al., Symp.
ƒ Mobility enhancement VLSI Technology Digest, pp. 48-49, 2004

ƒ Metallic source/drain structure z Process-induced strain is dependent on:

ƒ Negative differential resistance devices ƒ process conditions (thermal exposure)
ƒ layer thicknesses and transistor lateral dimensions
z Summary • gate length, channel width, S/D length
T.-J. King, 10/19/04 45 T.-J. King, 10/19/04 46

Strained FinFET Approaches Minimizing Parasitic Resistance

z Need thin-body structure to control leakage

Stressed Capping Stressed Gate Stressed S/D z Use metallic source/drain to minimize Rseries
Layer Electrode
ƒ e.g. fully silicided source/drain regions
z y
x ƒ Ideally, Schottky barrier height Φb ≤ 0.1 eV

z Advantages:
Gate
ƒ improved circuit speed
SOI TSi ƒ simpler process flow
SiO2 TBOX ƒ reduced S/D variations
ƒ enhanced thermal
Silicon Substrate conductivity

T.-J. King, 10/19/04 47 T.-J. King, 10/19/04 48

12
 Thin-Body Metallic-S/D MOSFETs Off the Roadmap…
J. Kedzierski et al., IEDM Technical Digest, pp. 57-60, 2000
z Alternative approaches to
• TSi ≈ 10nm
1E-3 ƒ enhance performance and/or functionality
|Vds| from 0.2V to 1.4V
1E-4 in steps of 0.4V • PtSi (Φbop=0.24V) ƒ lower power consumption per function
for PMOS S/D
1E-5
will be needed to reduce cost per function
ErSi1.7 (Φbon=0.28V)
|Id| (A/μm)

1E-6
for NMOS S/D ¾ innovative circuit & system design
1E-7 PtSi ErSi1.7
PMOS ¾ 3D & heterogeneous integration

FUNCTION
NMOS

COST PER
1E-8 Tox = 4nm Tox = 4nm 9 Excellent Ioff SiGe comb-drive resonator on top of amplifier alternative
1E-9
Lg = 20nm Lg = 15nm approaches
9 High NMOS contact to scaling
1E-10
-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 resistance due to A. E. Franke et al.,
Vg (V)
oxidation of ErSi1.7 2000 Solid-State Sensor
and Actuator Workshop

¾ new devices TIME (yrs)

T.-J. King, 10/19/04 49 T.-J. King, 10/19/04 50

Negative Differential Resistance Outline

“peak” current
CURRENT

z NDR devices enable

Current decreases
more efficient design with increasing z Introduction
voltage
Ælower power & cost,
provided that the NDR devices
“valley” current z Thin-body transistor structures
ƒ are compact (as small as a FET),
VOLTAGE z Advanced CMOS materials
ƒ are easily integrated with CMOS, and
NDR voltage
ƒ have high “peak” to “valley” current ratio.
layout area z Performance enhancement approaches
comparison DEVICE COUNT COMPARISON
Circuit CMOS NDR + NFET z Summary
XOR 16 4
NOR+flip-flop 12 4 P. Mazumder et al.,
< 50% Proc. IEEE 86, 664
SRAM 6 3 (1998)

T.-J. King, 10/19/04 51 T.-J. King, 10/19/04 52

13
 MOSFET Scaling Scenario The End is Not the Limit !
Technology, Device & Circuit
z Innovations in process technology,
z Thin-body FET structures pave Innovations,
a pathway for scaling CMOS to high-κ dielectric materials, and device design will Heterogeneous Integration
metal S/D sustain the Si revolution
the end of the roadmap alternative Lower Power,
metal gate semiconductor?

SALES($)/YR
Investment Lower Cost
Mainframes (>1 persons per computer)
Lg (nm): 65 50 40 30 20 10 larger Eg, lower εr PCs (1 person/computer)
UbiComp (>1 computers per person)

G strained Si low channel doping Acknowledgement: Market Growth

Mark Weiser
S D classical z Information technology willfor better
be quality-of-life
Si G ƒ pervasive Environment
S SOI D TIME ƒ embedded
SiO2 today
ultra-thin body Si substrate ƒ human-centered
Sensatex ƒ solving societal- Energy Health Disaster response
G
scale problems care
multi-gate S SOI D
G
Philips Transportation
T.-J. King, 10/19/04 53 T.-J. King, 10/19/04 54

14