Introduction to
CMOS VLSI
Design
CMOS Transistor Theory:
Non-Ideal Effects
Capacitance
q Any two conductors separated by an insulator have
capacitance
q Gate to channel capacitor is very important
– Creates channel charge necessary for operation
q Source and drain have capacitance to body
– Across reverse-biased diodes
– Called diffusion capacitance because it is
associated with source/drain diffusion
MOS devices CMOS VLSI Design Slide 2
Channel Charge
q MOS structure looks like parallel plate capacitor
while operating in inversion
– Gate – oxide – channel
q Qchannel =
gate
Vg
polysilicon + +
gate source Vgs Cg Vgd drain
W
Vs - - Vd
channel
tox n+ - + n+
SiO2 gate oxide
Vds
L
n+ n+ (good insulator, ox = 3.9) p-type body
p-type body
MOS devices CMOS VLSI Design Slide 3
Gate Capacitance
q Approximate channel as connected to source
q Cgs = eoxWL/tox = CoxWL = CpermicronW
q Cpermicron is typically about 2 fF/µm
polysilicon
gate
W
tox
L SiO2 gate oxide
n+ n+ (good insulator, ox = 3.9 0)
p-type body
MOS devices CMOS VLSI Design Slide 7
Diffusion Capacitance
q Csb, Cdb
q Undesirable, called parasitic capacitance
q Capacitance depends on area and perimeter
– Use small diffusion nodes
– Comparable to Cg
for contacted diff
– ½ Cg for uncontacted
– Varies with process
MOS devices CMOS VLSI Design Slide 8
Short Channel Effects
Behavior of short channel device mainly due to
10
5 usat =105
Constant Velocity saturation –
velocity the velocity of the
carriers saturates due to
un (m/s)
scattering (collisions
Constant mobility suffered by the carriers)
(slope = µ)
0
0 1.5 3
xc= x(V/µm)
For an NMOS device with L of .25µm, only a couple of volts
difference between D and S are needed to reach velocity saturation
CMOS VLSI Design
Voltage-Current Relation:
Velocity Saturation
For large L or small VDS, K approaches 1.
For short channel devices For short channel devices, K is small than 1 which means that
the delivered current, even in the linear region, is smaller than
q Linear: When VDS £ VGS – VT
what would normally be expected!
VDSAT = k(VGT) VGT so further increasing VDS does not yield
ID = k(VDS) k’n W/L [(VGS – VT)VDS – VDS2/2]
more current
where
k(V) = 1/(1 + (V/xcL)) is a measure of the degree of
velocity saturation
q Saturation: When VDS = VDSAT ³ VGS – VT
IDSat = k(VDSAT) k’n W/L [(VGS – VT)VDSAT – VDSAT2/2]
CMOS VLSI Design
Velocity Saturation Effects
10
VGS = VDD Long For short channel devices
channel and large enough VGS – VT
devices
VDSAT < VGS – VT so
Short
channel the device enters
devices saturation before VDS
0
reaches VGS – VT and
operates more often in
VDSAT VGS-VT saturation
IDSAT has a linear dependence wrt VGS so a reduced amount
of current is delivered for a given control voltage
CMOS VLSI Design
Short Channel I-V Plot (NMOS)
X 10-4
2.5 Early Velocity
VGS = 2.5V
Saturation
2
1.5 VGS = 2.0V
ID (A)
Linear dependence
1
Linear Saturation VGS = 1.5V
0.5
0 VGS = 1.0V
0 0.5 1 1.5 2 2.5
VDS (V)
NMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = 0.43V
CMOS VLSI Design
MOS ID-VGS Characteristics
Linear (short-channel) versus
X 10-4 long-channel quadratic (long-channel)
6 dependence of ID on VGS in
quadratic
5 saturation
4 short-channel
ID (A)
3 linear
2 Velocity-saturation causes the
1 short-channel device to saturate
0 at substantially smaller values of
0 0.5 1 1.5 2 2.5 VDS resulting in a substantial
VGS (V) drop in current drive
(for VDS = 2.5V, W/L = 1.5)
CMOS VLSI Design
Short Channel I-V Plot (PMOS)
All polarities of all voltages and currents are reversed
-2 VDS (V)-1 0 PMOS
0
transistor,
VGS = -1.0V
0.25um,
-0.2
Ld = 0.25um,
VGS = -1.5V W/L = 1.5,
-0.4
VDD = 2.5V,
VT = -0.4V
ID (A)
-0.6
VGS = -2.0V
-0.8
X 10-4
VGS = -2.5V -1
CMOS VLSI Design
The MOS Current-Source Model
G
ID = 0 for VGS – VT £ 0
ID
S D ID = k’ W/L [(VGS – VT)Vmin–Vmin2/2](1+lVDS)
for VGS – VT ³ 0
B with Vmin = min(VGS – VT, VDS, VDSAT)
and VGT = VGS - VT
Determined by the voltages at the four terminals and a set of
five device parameters
VT0(V) g(V0.5) VDSAT(V) k’(A/V2) l(V-1)
NMOS 0.43 0.4 0.63 115 x 10-6 0.06
PMOS -0.4 -0.4 -1 -30 x 10-6 -0.1
CMOS VLSI Design
Other (Submicon) MOS Transistor
Concerns
q Velocity saturation
q Subthreshold conduction (aka weak inversion)
– Transistor is already partially conducting for voltages below VT
q Threshold variations
– In long-channel devices, the threshold is a function of the
length (for low VDS)
– In short-channel devices, there is a drain-induced threshold
barrier lowering (DIBL) at the upper end of the VDS range (for
small L) G
q Parasitic resistances
– resistances associated with the S D
source and drain contacts RS RD
q Latch-up
CMOS VLSI Design
The Threshold Voltage
VT = VT0 + g(Ö|-2fF + VSB| - Ö|-2fF|)
where
VT0 is the threshold voltage at VSB = 0 and is mostly a function of the
manufacturing process
Difference in work-function between gate and substrate material, oxide
thickness, Fermi voltage, charge of impurities trapped at the surface, dosage of
implanted ions, etc.
VSB is the source-bulk voltage
fF = -fTln(NA/ni) is the Fermi potential (fT = kT/q = 26mV at 300K is the thermal
voltage; NA is the acceptor ion concentration; ni » 1.5x1010 cm-3 at 300K is the
intrinsic carrier concentration in pure silicon)
g = Ö(2qesiNA)/Cox is the body-effect coefficient (impact of changes in VSB)
(esi=1.053x10-10F/m is the permittivity of silicon; Cox = eox/tox is the gate oxide
capacitance with eox=3.5x10-11F/m)
CMOS VLSI Design
Subthreshold Conductance
10-2
Transition from ON to OFF is
Linear region gradual (decays exponentially)
Current roll-off (slope factor) is
Quadratic region also affected by increase in
temperature
ID (A)
Subthreshold S = n (kT/q) ln (10)
(typical values 60 to 100 mV/decade)
exponential
region
Has repercussions in dynamic
0 0.5 1 1.5 2 2.5
circuits and for power
VT VGS (V)
10-12 consumption
ID ~ IS e (qVGS/nkT) where n ³ 1
CMOS VLSI Design
Subthreshold ID vs VGS
ID = IS e (qVGS/nkT) (1 - e –(qVDS/kT))(1 + lVDS)
VDS from 0 to 0.5V
CMOS VLSI Design
Subthreshold ID vs VDS
ID = IS e (qVGS/nkT) (1 - e –(qVDS/kT))(1 + lVDS)
VGS from 0 to 0.3V
CMOS VLSI Design
Threshold Variations
VT VT
Low VDS
Long channel threshold
threshold
L VDS
Threshold varies as a function For short channel devices, the
of the length of the transistor threshold varies as a function of VDS
(for low VDS) - drain-induced barrier lowering
(DIBL)
CMOS VLSI Design
Drain Induced Barrier Lowering
10-2 q Drain-induced barrier
lowering (DIBL) is a short-
channel effect in MOSFETs
referring originally to a reduction of
threshold voltage of the transistor
at higher drain voltages.
ID (A)
q For high VDS, the drain depletion
region interacts with the source
increasing VDS near the channel surface lowering
the source potential barrier. The
source then injects carriers into
0 0.5 1 1.5 2 2.5 the channel without the gate
10-12 playing a role.
VGS (V)
q DIBL is enhanced at higher VDS
and shorter L.
CMOS VLSI Design
