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System Verilog Que

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Purna satya srinivas Vempala
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13 views3 pages

System Verilog Que

Uploaded by

Purna satya srinivas Vempala
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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@shraddha_pawankar Date:05/03/2024

System Verilog

1) What is the HDL limitation for the verification?


 Doesn’t support Functional coverage
 No oops Feature.
 Static in nature.

2) Which methodology is supported by System verilog?


 Constraint Random Coverage driven Verification
 Assertion based verification
 RTL design

3) How do we generate random packtes in SV?


 Random packets generates in Transaction class.
 We define variable in Transaction class.

4) What is the difference between Static and virtual interface?


 Static interface creates permanent connection in RTL.
 Virtual interface makes dynamic connection in Testbench.

5) Can we use virtual interface for the design ? if yes? Why.


 Virtual interface is not synthesizable construct
 It meant for dynamic connection in SV TB.
 We cant replace/add anything dynamically in the real hardware.
 So we cant use virtual interface in the design

6) Why do we opt for virtual interface for the SV TB?


 To connect the TB components dynamically with different ports
and generate different kinds of verification scenarios.

7) Semaphore can be used for


 Management of proper resource sharing
 Synchronization purpose

8) Which of the following datatype cannot be randomized?

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@shraddha_pawankar Date:05/03/2024

 String datatype.

9) The extended class constraints can override base class constraint if


 The constraint names are same in both case base and extended
classes.

10) Inline constraints can be used for


 Inline constraints are not meant for overriding the constraints .
 They are meant for additional constraints.

11) Which method is used to switch on and off the constraints?


 Constraint_mode()

12) What are the different ways to avoid race around condition
between DUT and TB.
 Clocking block
 Program block
 Driving DUT inputs using Non-blocking assignments.

13) Which of the following is true about packages?


 Good for reusability
 Good for declaring global variables.
 Good for definition of global methods like printing error message.
 Package is good for reusability because it can global variables and
global methods.

14) Typedef keyword can be used for


 Defining user defined data type as aliases for the existing
datatype.
 Typedef is a keyword used to define user defined datatype.

15) Queues can be used to model


 LIFO
 FIFO
 By pushing and popping the elements in the same direction – LIFO
 By pushing and popping the elements in the opposite direction –
FIFO
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@shraddha_pawankar Date:05/03/2024

16) The constructor method(new) role??


 Allocated fresh memory for each and every call.
 The constructor will allocate memory every time it is called it
returns the reference of the object to handle.

17) Which of the following is suitable for asynchronous signals in


Interface?
 MODPORTS
 Asynchronous signals should not be included in clocking block.it
should be included in MODPORTS.

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