System Verilog Interview QAs

1) Explain fork_join, fork_join_any, fork_join_none?

 fork...join: Waits for all parallel processes to finish.
 fork...join_any: Continues once any one process finishes.
 fork...join_none: Does not wait for any process, continues immediately.

2) What is pre_randomization?
A callback function that is automatically called before randomization of an object to set
initial values or states.

3) Difference between array and queue

Array: Fixed or dynamic size, indexed.
Queue: Variable size, allows push/pop operations similar to FIFO.

4) What is coverage? Explain transaction coverage

Coverage: Measures which parts of the design/test have been exercised.
Transaction coverage: Tracks different transaction-level events, ensuring all scenarios are
tested.

5) Assertion to check 3-bit signal has one or more bits low

assert property (!(signal = = = 3'b111));

6) Difference between functions and tasks?

Function: Executes in 0 time, can't contain delays or timing control.
Task: Can contain delays, wait statements, and consume simulation time.

7) Constraint for random array (size 20–30, descending)

rand int arr[];
constraint size_c { arr.size() inside {[20:30]}; }
constraint order_c {
foreach (arr[i]) {
if (i > 0) arr[i] <= arr[i-1];
}
}

8) Deep and shallow copy

Shallow copy: Copies reference.
Deep copy: Copies the actual content, including referenced objects.

9) What is virtual class?

A class that cannot be instantiated directly. Used as a base class for polymorphism.
10) What is parameterized class?
A class that takes parameters like data type or value.

class my_class #(type T=int);

T data;
endclass

11) What is clocking block?

Defines timing relationship between design and testbench signals for synchronization.

12) Use of monitor and scoreboard

Monitor: Captures DUT outputs passively.
Scoreboard: Compares actual outputs with expected results.

13) Pass by value and pass by reference

Pass by value: Copies the value into the function/task.
Pass by reference: Passes the actual reference, so modifications affect the original.

14) Why task can’t return a value?

Tasks can have timing delays and multiple outputs, so returning a single value is not
practical. Use output arguments instead.

15) Constraint to check power of 2 values

constraint pow2_c { (value & (value - 1)) == 0; }

16) Assertion for D flip-flop

property dff_check;
@(posedge clk) q == $past(d);
endproperty
assert property (dff_check);

17) Constraint: pick 2 cars with color-wise consecutive

Assuming colors are encoded as integers:

rand int car1, car2;

constraint color_c {
car1 inside {[0:3]};
car2 == car1 + 1 || car2 == car1 - 1;
}

18) Purpose of scoreboard?

It verifies correctness by comparing DUT output with expected results. Helps catch
mismatches and bugs.
19) 100% code coverage and 90% functional coverage?
Design code is fully exercised, but some functional scenarios are missing or not tested
thoroughly.

20) 80% code coverage and 100% functional coverage?

All functionalities are tested, but some lines or branches of code were not executed.

21) How to sort elements in an array?

Using built-in sort() method:

my_array.sort(); // Ascending
my_array.rsort(); // Descending

22) Constraint: 3 inputs occur 20%, 30%, 50%

Use distribution:

rand bit [1:0] input_sel;

constraint dist_c {
input_sel dist {0 := 20, 1 := 30, 2 := 50};
}

23) What are constraints? Give example

Constraints restrict the range or relation of random variables.

rand int x;
constraint c { x > 5 && x < 10; }

24) Function to multiply inputs and return result

function int multiply(int a, int b);
return a * b;
endfunction

25) Difference between get and try_get

get(): Blocking; waits until data is available.
try_get(): Non-blocking; returns success/fail.

26) What is a scoreboard and how it works?

Scoreboard compares expected and actual outputs from the DUT to validate correctness.

27) Why not pass object from driver to monitor directly?

Monitor is passive; collecting data from the interface ensures accurate observation, even with
DUT timing changes.
28) Use of checker and monitor
Monitor: Captures signal activity.
Checker: Applies protocol rules and assertions to validate the design.

29) Ensuring all memory address ranges are covered?

Use functional coverage with bins over address ranges:

covergroup cg;
coverpoint addr { bins range[] = {[0:255]}; }
endgroup

30) Assertion for ACK/NAK communication

Rising edge triggered ACK:

property ack_p;
@(posedge clk) req |=> ack;
endproperty
assert property (ack_p);

Level-triggered:

property ack_level;
@(posedge clk) req && !ack |-> ack;
endproperty

31) Testbench for FIFO (components & scenarios)

Components:
Driver: Sends data to FIFO.
Monitor: Observes FIFO outputs.
Scoreboard: Compares outputs with expected values.
Generator: Produces input data.
Scenarios:
Full/empty FIFO.
Random writes and reads.
Overflows/underflows.

32) Why associative and dynamic arrays?

Associative: When index is non-sequential (e.g., memory model).
Dynamic: When size changes during runtime.

33) Types of arrays

Static
Dynamic
Associative
Queue
34) Types of coverage and code coverage
Functional coverage: Bins, coverpoints, cross coverage.
Code coverage: Line, condition, branch, toggle, FSM.

35) Constraining a variable inside function scope

Variables inside functions can't be constrained directly. Workaround: declare it in class
scope or pass as argument.

36) Probability of a single-weight random variable?

If all options have equal weight, probability is 1/N (where N = number of values).

37) Weighted & distributed constraints

Weighted (deprecated in some tools):
var dist { 1 := 70, 2 := 30 };

Distributed:
var dist { 1 := 2, 2 := 1 }; // 2:1 ratio

38) Soft constraint & syntax

A soft constraint can be overridden by other constraints.
constraint soft_c { soft x == 5; }

39) Constraint override in child class

Parent: constraint c {a > 50;} Child: constraint c {a < 10;}
Conflict: Constraints are contradictory - randomization fails unless parent constraint is
overridden or disabled.

40) Declare, initialize, and display all elements of a queue

int q[$]; // Declare a queue

initial begin
q = {1, 2, 3, 4}; // Initialize
foreach (q[i]) $display("q[%0d] = %0d", i, q[i]); // Display
End

41) Driver code for data payload (dynamic array) and enable signal
task send_data(input bit enable, input int data[]);
if (enable) begin
foreach (data[i]) begin
$display("Sending data: %0d", data[i]);
end
end
endtask
42) Difference between posedge and $rose
posedge: Trigger used in procedural blocks (@posedge clk).
$rose(signal): Function used in assertions to detect rising edge.

43) Find 2nd and 3rd largest elements in array

int arr[] = '{5, 2, 9, 1, 7};
arr.sort();
$display("2nd largest: %0d", arr[$-2]);
$display("3rd largest: %0d", arr[$-3]);

44) SV or C code to find angle between hour and minute hands

float angle(int hour, int minute) {
float hour_angle = 30 * hour + 0.5 * minute;
float minute_angle = 6 * minute;
float diff = abs(hour_angle - minute_angle);
return (diff > 180) ? 360 - diff : diff;
}

45) Concurrent vs Immediate Assertions

Concurrent: Evaluated over simulation time.
Immediate: Checked instantly, in simulation order.

46) Covergroup, Coverpoints, Bins

Covergroup: Encapsulates coverage logic.
Coverpoints: Variables being monitored.
Bins: Buckets to count occurrences.

Example:
covergroup cg;
coverpoint a {
bins b0 = {0};
bins b1 = {1};
}
endgroup

47) Override parameters in design

Use during instantiation:
design_name #(.WIDTH(16)) inst_name (...);

48) Scoreboard logic

Collects expected output.
Receives actual output from monitor.
Compares and logs mismatches.
49) Coverage bins types
Auto bins
Explicit bins
Ignore bins
Illegal bins

50) Automating debugging process

Use:
Logging mechanisms.
Error injection and tracing.
Assertions and monitors.
Scripted waveform dumping.

51) Bidirectional constraints

Constraints where variables affect each other mutually.

constraint bidir {
a + b == 10;
a inside {[2:8]};
}

52) Preferred arrays for scoreboard modeling

Associative arrays - flexible index types, dynamic size, fast look-up.

53) What is cross coverage?

Combines multiple coverpoints to track all combinations:
cross cp1, cp2;

54) Coverpoints used in DMA

Example:
Address range
Burst size
Transfer type
Channel ID
Read/Write type

55) Have you worked on functional coverage?

(Example answer) Yes, used covergroups and coverpoints to verify scenario-based
transactions and address ranges in DMA/UART protocol.

56) Can private class exist in SV? What is public?

Private class: Not allowed in SV.
Public: Default access level for class members if not specified.
57) What is local and protected keyword?
local: Cannot be accessed outside class or subclass.
protected: Accessible within class and subclasses

58) What is rand and randc?

rand: Generates random values (can repeat).
randc: Generates random values without repeating until all values are used (cyclic random).

59) What constraints have you worked on?

(Example answer) Worked on constraints for:
Packet sizes
Address alignment
Priority levels
Transaction ordering
Random data generation with interdependent fields

60) Code to generate ascending or descending numbers from random values

rand int arr[];
constraint c {
arr.size() == 10;
foreach (arr[i]) {
if (i > 0) arr[i] >= arr[i-1]; // ascending
// or use arr[i] <= arr[i-1]; for descending
}
}

61) Assertion code to generate 100 MHz signal (check posedge and negedge)
Assuming a 10 ns clock period:

property check_100MHz;
time t;
@(posedge clk)
t == $time % 10ns == 0;
endproperty

assert property (check_100MHz);

To check edges:

property clk_edges;
@(posedge clk) 1 |-> $rose(clk) or $fell(clk);
endproperty
62) If base class is encrypted, how to write constraint in extended class?
Define new constraints in the extended class using only inherited variables (no redefinition).
If access is restricted, override using public/protected members.

63) Generate unique random numbers without rand/randc

int unsigned unique_vals[10];
initial begin
for (int i = 0; i < 10; i++) unique_vals[i] = i;
unique_vals.shuffle(); // built-in shuffle
end

64) Difference between a = b; and a <= b; in initial blocks

initial begin
#10 a = b;
#20 b = c;
end

initial begin
#10 a <= b;
#20 a <= c;
end

a = b;: Immediate assignment (value at that simulation time).

a <= b;: Non-blocking; will schedule to update in the next time slot. Result: Non-blocking
may cause both a <= b and a <= c to evaluate to the same a.

65) Difference between logic and bit

bit: 2-state (0 or 1).
logic: 4-state (0, 1, x, z) — used in RTL.

66) Polymorphism and its application

Allows the same method name to operate differently depending on the class. Useful for
writing generic drivers, monitors, or sequences that call overridden methods in extended
classes.

67) Difference between int and integer

int: 4-bit signed (32 bits).
integer: SystemVerilog legacy type, signed 32 bits.

68) What is an abstract class? Have you used one?

Class that cannot be instantiated.
Contains pure virtual methods (pure virtual function). Example use: base sequence classes in
UVM.
69) Struct vs Union
Struct: All members have their own storage.
Union: All members share the same memory.

70) Program block and its uses

Encapsulates testbench logic, synchronizes with design using clocking blocks. Ensures
testbench executes after design logic.

71) Assertion syntax

assert property (@(posedge clk) req |=> ack);

72) Difference between |-> and |=>

|->: Non-overlapping implication.
|=>: Overlapping implication.

73) Difference between bit & logic

bit: 2-state, for testbench use.
logic: 4-state, suited for RTL and modeling unknowns.

74) Why virtual interface?

Allows interface access across classes without creating multiple copies. Useful for modular
and reusable TB architecture.

75) Why SV over UVM?

Clarification: SV is a language; UVM is a methodology built on SV.
Use UVM for large, scalable projects. For simple or quick testing, plain SV is easier.

76) Types of assertions

Immediate (executed in procedural code)
Concurrent (executed over simulation time)
Temporal assertions using property

77) 80% code coverage and 100% functional coverage?

All required functionality is tested, but some design branches/statements are not exercised.
Investigate unused paths.

78) What do you mean by code coverage and functional coverage?

Code coverage: Measures which lines/branches/conditions of the HDL code are exercised.
Functional coverage: Measures if functional scenarios (like transactions or protocol features)
are tested.

79) Where do we use polymorphism? Is virtual necessary in parent?

Used in UVM (e.g., virtual methods in base class overridden in derived).
Yes, parent method must be declared virtual for polymorphism to work.
80) What is inheritance and polymorphism?
Inheritance: One class acquires properties of another.
Polymorphism: Methods behave differently based on object type.

81) Why use associative arrays?

Efficient for modeling sparse or index-based structures like memory or scoreboard
comparisons.

82) Why use clocking block and program block?

Clocking block: Controls signal sampling/driving.
Program block: Synchronizes testbench logic with design.

83) What is an interface?

Bundle of related signals grouped together for modularity and clean connectivity between
design and testbench.

84) What is a callback?

Mechanism to alter behavior during simulation without modifying core code — allows
hooks for extensions (used in UVM).

85) Different sampling methods in coverage

Automatic (event-based): covergroup @(posedge clk);
Manual: Using .sample() method.

86) What are SystemVerilog threads?

Parallel processes spawned using:
fork...join
Always blocks
Initial blocks

87) What is virtual interface? Why use virtual keyword?

Allows interface to be passed as a class handle.
virtual keyword enables dynamic binding of interface during runtime (e.g., in UVM
components).

88) Can we use queue instead of mailbox?

Only if you don’t need synchronization.
Queue is simpler, but mailbox is blocking and better for thread communication.

89) Pre-randomize and post-randomize methods?

pre_randomize(): Called before randomization.
post_randomize(): Called after randomization to process results.
90) Different constraints in SystemVerilog
Soft constraint
Hard constraint
In-line constraint
Distribution (dist)
Implication (->)
Weighted
Inter-dependent constraints

91) Extend dynamic array from 10 to 20 elements without losing data?

int da[] = new[10];
// ...
da = da.resize(20); // Not a built-in, but custom logic:
int tmp[] = new[20];
for (int i = 0; i < da.size(); i++) tmp[i] = da[i];
da = tmp;

92) Delete a particular element from dynamic array?

manually:
int da[] = {1, 2, 3, 4, 5};
da.delete(index); // For associative arrays

// For dynamic array: recreate without element

int temp[$];
foreach (da[i]) if (i != 2) temp.push_back(da[i]);
da = temp;

93) What to do with 100% code coverage and 30% functional coverage?
Functional scenarios are lacking. Analyze:
Missing coverpoints
Incomplete stimulus
Improve testcases to cover real functionality