Int. J. Mach. Learn. & Cyber.

DOI 10.1007/s13042-014-0324-3

ORIGINAL ARTICLE

Optimal sizing of CMOS analog circuits using gravitational search

algorithm with particle swarm optimization
S. Mallick • R. Kar • D. Mandal • S. P. Ghoshal

Received: 5 September 2014 / Accepted: 24 December 2014

 Springer-Verlag Berlin Heidelberg 2015

Abstract In this paper, a hybrid population based meta- and PSO in terms of convergence speed, design specifica-
heuristic search algorithm named as gravitational search tions and performance parameters of the optimal design of
algorithm (GSA) combined with particle swarm optimiza- the analog CMOS amplifier circuits. It is shown that GSA–
tion (PSO) (GSA–PSO) is proposed for the optimal designs PSO based design technique for each amplifier circuit yields
of two commonly used analog circuits, namely, comple- the least MOS area, and each designed circuit is shown to
mentary metal oxide semiconductor (CMOS) differential have the best performance parameters like gain, power
amplifier circuit with current mirror load and CMOS two- dissipation etc., as compared with those of other recently
stage operational amplifier circuit. PSO and GSA are sim- reported literature. Still the difficulties and challenges faced
ple, population based robust evolutionary algorithms but in this work are proper tuning of control parameters of the
have the problem of suboptimality, individually. The pro- algorithms GSA and PSO, some conflicting design/perfor-
posed GSA–PSO based approach has overcome this dis- mance parameters and design specifications, which have
advantage faced by both the PSO and the GSA algorithms been partially overcome by repeated manual tuning. Multi-
and is employed in this paper for the optimal designs of two objective optimization may be the proper alternative way to
amplifier circuits. The transistors’ sizes are optimized using overcome the above difficulties.
GSA–PSO in order to minimize the areas occupied by the
circuits and to improve the design/performance parameters Keywords CMOS  Circuit sizing  Two-stage op-amp 
of the circuits. Various design specifications/performance Differential amplifier  GSA–PSO  Evolutionary
parameters are optimized to optimize the transistor’s sizes optimization techniques  Low power design
and some other design parameters using GSA–PSO. By
using the optimal transistor sizes, Simulation Program with
Integrated Circuit Emphasis simulation has been carried out 1 Introduction
in order to show the performance parameters. The simula-
tion results justify the superiority of GSA–PSO over dif- Analog circuits have a significant role almost in all inte-
ferential evolution, harmony search, artificial bee colony grated circuits (ICs). They are extensively used as the
interface between the real world and the digital world
signals. Therefore, the importance of the analog design in
S. Mallick  R. Kar (&)  D. Mandal
ICs cannot be underestimated. Compared to the digital
Department of Electronics and Communication Engineering,
NIT Durgapur, Durgapur, India design, the analog design has not been automated to a great
e-mail: rajibkarece@gmail.com extent due to its immense complexity [1]. The automation
D. Mandal of analog circuit design has attracted great attention of the
e-mail: durbadal.bittu@gmail.com researchers across the world [2]. Analog circuit sizing is a
very composite, iterative and monotonous and time con-
S. P. Ghoshal
suming process.
Department of Electrical Engineering, NIT Durgapur, Durgapur,
India The analog design procedure consists of three major
e-mail: spghoshalnitdgp@gmail.com steps: topology selection, component sizing and layout

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 Int. J. Mach. Learn. & Cyber.

extraction [3]. The expert designers can make the analog Most of the circuit design optimization problems are
sizing and design process by their perception and experi- formulated with different types of constraints, variables
ence [4]. However, when the circuit complexity increases, and objective functions. Therefore, the aforementioned
the search space increases accordingly and it becomes an optimization methods usually require much more time for
excessive time consuming method for the designers to the computation when the problems become more com-
obtain the optimal design parameters. In fact, the optimal plicated and involve a very large search space. In order to
design of analog components is a bottleneck in the design overcome the drawbacks associated with these optimiza-
procedure. Automatically optimizing the sizes of the ana- tion methods, a new set of nature-inspired meta-heuristic
log components used in the circuits is an important issue optimization algorithms based on swarm intelligence [21]
towards the ability to design the high performance circuits is proposed. The idea behind these algorithms is inspired
quickly [5, 6]. In CMOS analog IC design method, the from the collective behaviour of decentralized, self-orga-
relations among aspect ratios, channel lengths and widths nized systems. Swarm intelligence based systems typically
of MOS transistors ensure that the search space and opti- employ a population of particles interacting locally with
mization technique are smooth and reliable. For the auto- each other and globally with their environment. Although
mation of optimal sizing of CMOS analog IC, effective the particles follow the conventions but there is no cen-
optimization techniques are essential. tralized control over the behaviour of each particle. The
Several classical optimization techniques are employed complexity of global behaviour arises when the particles
for the optimal sizing of CMOS analog IC. Classical interact with each other. Some of the well accepted opti-
optimization methods are of two types: deterministic mization techniques are: ant colony optimization (ACO)
methods and statistical methods. Deterministic techniques [22], particle swarm optimization (PSO) [23–25] and arti-
like Simplex method [7], Automatic method [8], Goal ficial bee colony (ABC) [26]. PSO is very popular opti-
Programming [9], and Dynamic Programming [10] etc., are mization algorithm among researchers because it offers
applicable for small size optimization problems. Statistical good performance in several application domains [27].
methods usually start by finding a suitable Direct Current These optimization techniques are integrated into the
(DC) operating point which is provided by the proficient analog computer-aided design (CAD) tools for the topol-
analog designer. After that, a simulation-based method is ogy selection as well as for the optimal sizing of complex
employed. However, these statistical methods are also ICs and for the actual layout extraction of the circuits [28,
time-consuming and do not ensure the convergence 29]. Among the different CAD tools available, OPASYN
towards the global optimum solution [11]. Several draw- [30] and DELIGHT.SPICE [31] employ classical optimi-
backs of classical optimization methods are: zation techniques whereas, IDAC [32], OASYS [33] and
ASLIC [34] are heuristic based system design approaches.
(i) Highly sensitive to starting points when the
There are different types of methodologies reported for
number of solution variables and hence the size
analog circuit design automation. The first one equation
of the solution space increases.
based method. It is based on the reverse process of circuit
(ii) Frequent convergence to local optimum solution
analysis technique. Since circuit sizing is being done
or divergence or revisiting the same suboptimal
mathematically, due to the simplified device equations and
solution.
approximations [34, 35], automation is faster but the
(iii) Requirement of continuous and differentiable
accuracy is compromised. The second one is the simulation
objective cost function (gradient search methods).
based method, which optimizes a set of performance con-
(iv) Requirement of the piecewise linear cost approx-
straints characterized by complex trade-offs and makes a
imation (linear programming).
monotonous use of complete circuit simulator embedded in
(v) Problem of convergence and algorithm complex-
the optimization tool. This method usually requires several
ity (nonlinear programming).
iterations to adjust transistor sizes and an optimization tool
Hence, classical optimization methods are mostly not needs to evaluate the performance every time. The method
appropriate for optimal sizing of the total large size analog is more accurate but it takes a very long time to complete
IC design process, which is a complicated, highly con- the IC design process.
strained, nonlinear process. Sizing rules are proposed for CMOS and bipolar ana-
Heuristics based approaches are essential to solve the log IC synthesis in [36]. For topology selection and cir-
large size problems [12]. Some mathematical heuristic cuit sizing, a GA based CMOS operational amplifier
methods were previously used, e.g., local search (LS) [13], synthesizer called DARWIN is proposed [37]. An auto-
simulated annealing (SA) [14, 15], tabu search (TS) [16, mated circuit design system for the evolution and sub-
17], scatter search (SS) [18], genetic algorithms (GA) [19, sequent design of CMOS amplifiers using genetic
20] etc. programming and current flow analysis has been reported

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in [38]. Using geometric programming techniques CMOS adopted. The authors will also work on the abovemen-
op-amp design can be approximated as convex optimi- tioned CMOS analog circuits as forthcoming works.
zation (CO) problem [39]. An evolution-based approach The contribution made in this paper is the optimal sizing
called memetic algorithm is developed for automatic and design of different CMOS amplifier circuits with
sizing of high performance analog IC design in [40]. higher gain, lower power dissipation and lesser MOS area
Multi-objective evolutionary algorithm (EA) based on compared with those methods reported in the existing lit-
decomposition has been proposed for the optimization of erature. With particular technology parameters, GSA–PSO
second-generation current conveyors where HSPICE is algorithm is applied to the design problems. The problem
used as a circuit evaluator [41]. For optimal current considered in this work is the optimal CMOS transistors’
conveyors design without circuit evaluator, a multi- sizing, which yields the minimum area of the total design.
objective heuristic [42, 43] and PSO algorithm [44] are As a global optimization technique, GSA–PSO has smaller
used. PSO is employed for dynamic reconfiguration of number of primitive mathematical operators whereas, in
field-programmable analog circuits [45]. For this purpose, GA, mathematical operations are required for reproduction,
an op-amp with predefined design constraints has been mutation and crossover and hence, it leads to longer
designed using PSO, considering different external computation time. The simulation results justify the fact
parameters like high temperature and fabrication faults. that the proposed GSA–PSO based amplifier design yields
PSO is also employed for reconfigurable sensor elec- the least area, higher gain and dissipates the least power,
tronics in [46]. Low-power and low-voltage analog cir- satisfying the other performance parameters in the best
cuits have been designed using hierarchical particle manner, as compared with the results reported in recent
swarm optimization (HPSO) [47]. In [48], an automatic literature.
synthesis tool of a cascaded low noise amplifier (LNA) is The major difficulty and limitation of this work is the
developed based on simulated annealing (SA) algorithm proper tuning of the control parameters for GSA and PSO.
having adaptive tunnelling mechanism and post-optimi- Here, the hybridization has been done between GSA and
zation sensitivity analysis with respect to process, design PSO to get GSA–PSO technique. Actually the acceleration
and temperature, which has been presented in [49]. Most term (in 29) of GSA has been incorporated with the
of the aforementioned heuristic algorithms show the velocity of PSO (in 41).
problems of fixing algorithm’s control parameters, pre- For GSA–PSO the best weighting factors (determined
mature convergence, stagnation and revisiting the same by 30 trial runs) were found as: w = 0.01; c1 = c2 = 1.0;
solution over and again. In [50], detailed investigations through experimentation, the best results were obtained
about the application of EA for the synthesis and sizing of with a = 20; the other best parameters of GSA–PSO were:
analog ICs are discussed. G0 = 1,000; rNorm = 2; rPower = 1; e = 0.0001;
Some of the real-life applications of various soft com- velocity = zeros (np, D).
puting techniques in different engineering fields are men- After successful execution of the program in MATLAB,
tioned in [51–60]. minimum area is achieved in terms of design parameters.
The limitations of the conventional PSO are premature But when the W values and L values are put in Cadence,
convergence and stagnation problem [61, 62]. In order to some parameters are conflicting with each other. This is
overcome these problems, the authors propose an alterna- another limitation of this work. For example, when the gain
tive superior hybrid optimization technique called GSA– increases, the phase margin decreases and vice versa. Even
PSO, which is the combination of gravitational search when the value of CL increases, UGB decreases. Then
algorithm (GSA) [63–66] and PSO for the optimal designs some manual tuning is needed to get better result in terms
of CMOS differential amplifier circuit with current mirror of design specifications and design parameters. In this work
load and CMOS two-stage op-amp circuit. This type of single objective function is considered but the abovemen-
work is not done widely. So, this is the motivation of the tioned problem can be overcome by using multi-objective
work. function and multi-objective optimization.
Some real-life practical applications of evolutionary Similar to hybridization of GSA with PSO adopted in
optimization techniques are mentioned in [67–71]. this paper, there may be many other alternatives of
Some papers on PSO techniques are mentioned in [72– hybridizations like PSO with DE, GSA with DE, Firefly
74]. with DE, GSA with wavelet mutation, PSO with wavelet
The authors have adopted CMOS differential amplifier mutation, opposition based Bat algorithm etc. The authors
with current mirror load and CMOS two-stage operational of the paper have tried with all these alternatives for dif-
amplifier circuit. Besides these two circuits other analog ferent optimization problems and established the superi-
circuits like CMOS folded cascode operational transcon- ority of any such hybrid algorithm over the basic
ductance amplifier (FCOTA), CMOS comparator can be algorithms on case-to-case basis. In this paper GSA–PSO

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hybridization has been adopted to show its comparative

superiority over the basic GSA and PSO. To limit the
length of the paper, the authors have not included the
results of all abovementioned hybrid algorithms for the
present problem.
The rest of the paper is organized as follows: In Sect. 2,
design procedures of two different analog IC structures are
discussed and the objective functions are formulated. In
Sect. 3, GSA, PSO and the GSA–PSO algorithms are
briefly discussed and the steps involved in the CMOS
analog IC designs are elaborated. In Sect. 4, comprehen-
sive and demonstrative sets of results are reported and are
validated with SPICE simulator. Finally, Sect. 5 concludes
the paper. Fig. 2 CMOS two-stage operational amplifier

The design process is implemented with the help of the

2 Design specifications and objective function
relationships that define the specifications. From the rela-
formulation
tionships, an objective function or cost function (CF) is
developed to obtain the optimal (W/L) values of all the
The design process consists of two types of information:
MOS transistors used in the circuit and the DC bias cur-
the design criteria and the design parameters. In this paper,
rents in order to minimize the total area occupied by the
the optimal design of a CMOS differential amplifier with
MOS transistors as well as the total power dissipations in
current mirror load (Fig. 1) and the optimal design of a
the circuits.
CMOS two-stage operational amplifier (Fig. 2) circuit are
carried out.
For the aforementioned two structures, all the design 2.1 Design criteria for the CMOS differential amplifier
specifications considered which may be called as perfor- with current mirror load
mance parameters also are slew rate (SR), small-signal
differential voltage gain (Av), cut-off frequency (f-3dB), The performance specifications responsible for the design
maximum input common mode range (ICMR) (VIC (max)), of the CMOS differential amplifier with current mirror load
minimum ICMR (VIC (min)), unity gain bandwidth (UGB) are SR, Av, f-3dB, VIC (max), VIC (min) and Pdiss. The
and power dissipation (Pdiss), all having certain minimum detailed analysis and relations of different performance
and maximum ranges. In addition, the design parameters specifications can be found in [75]. The input variables
considered are as follows: aspect ratio (W/L) values of considered are given as follows:
different MOS transistors used in the circuits, load capac- VDD is the positive power supply (V); VSS is the neg-
itances (CL) and compensation capacitances (CC). CL and ative power supply (V); Vin is the threshold voltage of
CC are also performance parameter. NMOS (V); Vip is the threshold voltage of PMOS (V);
VDS is the drain to source voltage of MOSFET (V) and
VGS is the gate to source voltage of MOSFET (V);
Kn0 ¼ ln  Cox , where Kn0 is the transconductance parame-
ter for NMOS (lA/V2); Kp0 ¼ lp  Cox , where Kp0 is the
transconductance parameter for PMOS (lA/V2). ln and lp
are the electron mobility and hole mobility (cm2/Vs),
respectively. Cox is the gate oxide capacitance per unit
area (F/m2). kn and kp are the channel length modulation
parameters for NMOS and PMOS (V-1), respectively. ID
is the drain current of MOSFET. gm is the transconduc-
tance and gds is the output conductance, Rout is the output
resistance of the CMOS differential amplifier considered
in this paper.
The steps involved for the design of the CMOS differ-
ential amplifier circuit with current mirror load are as
Fig. 1 CMOS differential amplifier with current mirror load follows:

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• Determine the range of IDS to satisfy SR. • Determine the value of ID5 in order to satisfy SR and
ID5 Pdiss.
SR ¼ ð1Þ
CL ID5 ¼ SR  CC ð12Þ
1 • Determine the transconductance of the input transistors
f3dB ¼ ð2Þ
Rout CL (M1, M2) (refer to Fig. 2) from CC and UGB.
 
• Determine WL11 ¼ WL22 in order to satisfy Av, where gm1 ¼ 2p  UGB  CC ð13Þ
rffiffiffiffiffiffiffiffiffiffiffi
ffi    
W1 W2
gm1 2 Kn0 W1 • Determine the values of L1 and L2 from (14).
Av ¼ gm1 Rout ¼ ¼
gds2 þ gds4 ðkn þ kp Þ ID5 L1
W1 W2 gm1
ð3Þ ¼ ¼ 0 ð14Þ
L1 L2 Kn ID5
     
W3
• Determine L3 ¼ WL44 in order to satisfy the maximum • Estimate WL33 and WL44 from the maximum value of
value of ICMR. ICMR.
VIC ðmaxÞ ¼ VDD  VSG3 þ Vtn1 ð4Þ
W3 W4
W3 2ID5 ¼
¼  2 ð5Þ L3 L4
L3 Kp0 VSG3 þ Vtp ID5
¼
  Kp0 ½VDD  Vin ðmaxÞ  Vtp ðmaxÞ þ Vtn ðminÞ2
• Estimate WL55 ¼ WL66 in order to satisfy the minimum
ð15Þ
value of ICMR.    
W5 W8
VIC ðminÞ ¼ VSS þ VDS5 ðsatÞ þ VGS1 • Estimate L5 and L8 from the minimum value of
¼ VSS þ VDS5 ðsatÞ þ VGS2 ð6Þ ICMR.
W5 2ID5 W5 W8 2I D5
¼ ð7Þ ¼ ¼ ð16Þ
L5 Kn ½VDS5 ðsatÞ2
0
L5 L8 Kn ½VDS5 ðsatÞ2
0

• Determine ID5 to satisfy Pdiss, where where

Pdiss ¼ ID5 ðVDD þ jVSS jÞ ð8Þ s
ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
ffi
ID5 L1
VDS5 ðsatÞ ¼ Vin ðminÞ  VSS  Vtn ðmaxÞ 
Kn0 W1
2.2 Design specifications of CMOS two-stage ð17Þ
operational amplifier circuit  
W6
• Estimate L6 from (18).
The performance specifications for the design of CMOS  
two-stage op-amp are Slew rate (SR), DC voltage gain W6 W4 gm6
¼ ð18Þ
(Av), unity gain bandwidth (UGB), Maximum ICMR (VIC L6 L4 gm4
(max)), Minimum ICMR (VIC (min)) and Power dissipa-
where
tion (Pdiss). The design steps carried out for the optimal
design of CMOS two-stage op-amp are as follows [75]: gm6  10gm1 ð19Þ

• Choose the smallest value for CC and place the pole, p2 and
at 2.2 times higher than the unity gain bandwidth qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
gm4 ¼ Kp0 ðW4 =L4 ÞID5 ð20Þ
(UGB). For 60 phase margin it is assumed that right
half plane (RHP) zero, z1 is beyond ten times to that of
• Determine ID6 required for Pdiss.
the UGB.
CC [ 0:22CL ð9Þ ðgm6 Þ2
ID6 ¼ ð21Þ
gm6 2Kp ðW6 =L6 Þ
p2 ¼  ð10Þ
CL  
W7
gm6 • Estimate the value of L7 to achieve the current ratio
z1 ¼ ð11Þ
CC between ID6 and ID5.

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W7 W5 ID6 3 Evolutionary algorithm employed
¼ ð22Þ
L7 L5 ID5
Evolutionary algorithms are based on the meta-heuristics,
• Estimate the gain and power dissipation as per (23) and which are characterized as stochastic, adaptive and learn-
(24), respectively. ing in order to construct intelligent optimization methods
2gm2 gm6 are adopted in this work. Such methods have the potential
Av ¼ ð23Þ
ID5  ID6 ðkn þ kp Þ2 to become accustomed to their ever-changing dynamic
environment through the previously acquired knowledge.
Pdiss ¼ ðID5 þ ID6 ÞðVDD þ jVSS jÞ ð24Þ In this section, GSA, PSO and GSA–PSO optimization
techniques are briefly discussed for the optimal sizing of
Initial population matrix size for the GSA–PSO algo- the MOS transistors used in the CMOS amplifier circuits as
rithm has been considered as (P 9 Q), where P = 60 and well as for the minimization of total MOS transistors area
Q = 7. The row number (P) indicates the number of par- and the total power dissipation of the CMOS amplifier
ticles in the population and column number (Q) indicates circuits (Figs. 1, 2).
the dimension of each particle vector. The particle vectors
structured for the two CMOS analog circuit structures 3.1 Gravitational search algorithm
considered in this paper are expressed in (25) and (26),
respectively. In GSA [53–56] particles/solution vectors are considered as
Each particle vector is nothing but a row vector, con- objects and their performances are measured by their
sisting of design specifications/performance parameters as masses. All these objects attract each other by gravity
column elements. forces, and these forces produce global movements of all
XDiff Amp ¼ ½SR; CL ; Av ; f 3dB ; VIC ðminÞ; VIC ðmaxÞ; Pdiss  objects towards the objects with heavier masses. Hence,
ð25Þ masses cooperate using a direct form of communication
through gravitational forces. The heavier masses (which
XTwo stage Opamp ¼ ½SR; CL ; Av ; UGB; VIC ðminÞ; correspond to better solutions) move more slowly than
ð26Þ
VIC ðmaxÞ; Pdiss  lighter ones. This guarantees the exploitation step of the
algorithm.
where SR is the slew rate (V/ls); CL is the output capac- Three kinds of masses are defined in theoretical physics:
itance (pF); Av is the DC gain (dB); f-3dB is the cut-off
frequency (KHz); UGB is the unity gain bandwidth (MHz); (a) Active gravitational mass (Ma) is a measure of the
Pdiss is the power dissipation (lW); VIC(min) is the lower strength of the gravitational field due to a particular
value of ICMR (V) and VIC(max) is the upper value of object. Gravitational field of an object with small
ICMR (V). active gravitational mass is weaker than the object
For GSA–PSO, the parameters are taken as follows: with more active gravitational mass.
a = 20; G0 = 1,000; rNorm = 2; rPower = 1; e = (b) Passive gravitational mass (Mp) is a measure of the
0.0001; velocity = zeros (np, D). strength of an object’s interaction with the gravita-
The algorithm has been run for an upper limit of 200 tional field. Within the same gravitational field, an
iterations. The Cost Function (CF) is defined as the total object with a smaller passive gravitational mass
area occupied by the MOS transistors, i.e., sum of the experiences a smaller force than an object with a
width multiplied by the length of each MOS transistor for larger passive gravitational mass.
all the MOS transistors of the circuits considered in this (c) Inertial mass (Mt) is a measure of an object’s
paper. The CF used in this paper is given in (27). resistance to changing its state of motion when a
force is applied. An object with large inertial mass
X
N
CF ¼ ðWi  Li Þ ð27Þ changes its motion more slowly, and an object with
i¼1 small inertial mass changes it rapidly.
where N is the total number of MOS transistors used to In GSA, each mass has four specifications: position,
design the circuit. The desired value of CF is intended inertial mass, active gravitational mass and passive gravi-
to be smaller than 300 lm2 for both the optimally tational mass. The position of the mass corresponds to the
designed amplifier circuits. CF is to be minimized using solution of the problem and its gravitational and inertial
GSA–PSO algorithm to obtain the desired optimal masses are determined using a fitness function. In other
values. words, each mass presents a solution; the algorithm is

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navigated by properly adjusting gravitational and inertial where randj is a random number in the interval [0, 1].
masses. By lapse of generation cycles, it is expected that Hence, by the law of motion, the acceleration of the ith
masses be attracted by the heaviest mass. This particle/ particle at generation cycle t, and in dth dimension, adi ðtÞ is
vector with the heaviest active gravitational mass will given by (32).
present the optimum solution in the search space.
Fid ðtÞ
GSA considers an isolated system of particles/agents adi ðtÞ ¼ ð32Þ
Mii ðtÞ
with masses. It is like a small artificial world of masses
obeying the Newtonian laws of gravitation and motion. where Mii ðtÞ is the inertial mass of the ith particle vector.
More precisely, masses obey the following two laws: Furthermore, the next velocity of a particle is considered
i. as a fraction of its current velocity added to its acceleration.
Law of gravity: Each particle attracts every other particle Therefore, its velocity and its position could be calculated
and the gravitational force between two particles is by employing (33) and (34), respectively.
directly proportional to the product of their masses and vdi ðt þ 1Þ ¼ randi  vdi ðt þ 1Þ þ adi ðtÞ ð33Þ
inversely proportional to the square of the distance
xdi ðt þ 1Þ ¼ xdi ðtÞ þ vdi ðt þ 1Þ ð34Þ
(R) between them. R is used as RrPower (rPower = 1)
because R offers better results than R2 in all the In (33), is a uniform random variable in [0, 1]. This random
experimental cases with benchmark functions [63]. number is utilized to give a randomized characteristic to
ii. the search.
Law of motion: The current velocity of any particle/ The gravitational constant (G) is initialized at the
vector is equal to the sum of the fraction of its previous beginning and will be reduced with generation cycle to
velocity and the variation in the velocity. Variation in control the search accuracy. In other words, G as a function
the velocity or acceleration of any particle is equal to the of the initial value (G0) and generation cycle (t) is
force acted on the system divided by the mass of inertia. expressed as in (35).
  
Now, let us consider a system with N particles with t
G ¼ G0 exp a  ð35Þ
various masses. The position of the ith particle is defined maxGenCycles
by
Gravitational and inertia masses are simply calculated by the
Xi ¼ ðx1i ; . . .; xdi ; . . .; xni Þ for i ¼ 1; 2; . . .; N ð28Þ cost function (CF) evaluation. A heavier mass means a more
where xdi presents the position of ith particle in the dth efficient particle. This means that better particles have higher
dimension. attractions and walk more slowly. Assuming the equality of
At a specific generation cycle t, the force acting on ith the gravitational and the inertia mass, the values of masses
particle from jth particle is defined by the following are calculated using the map of fitness. Gravitational and
equation: inertial masses are updated by the following equations:
Mai ¼ Mpi ¼ Mii for i ¼ 1; 2; . . .; N ð36Þ
Mpi ðtÞ  Maj ðtÞ  d 
Fijd ðtÞ ¼ G ðtÞ Xj ðtÞ  Xid ðtÞ ð29Þ fiti ðtÞ  worstðtÞ
Rij ðtÞ þ e mi ðtÞ ¼ ð37Þ
bestðtÞ  worstðtÞ
where Maj ðtÞ is the active gravitational mass related to the
jth particle at generation cycle t, Mpi ðtÞ is the passive mi ðtÞ
Mi ðtÞ ¼ PN ð38Þ
gravitational mass related to the jth particle at generation 1 mi ðtÞ
cycle t, GðtÞ is gravitational constant at generation cycle t, where fiti ðtÞ represents the fitness value of the ith particle at
e is a small constant, and Rij ðtÞ is the Euclidian distance
generation cycle t, and worstðtÞ and bestðtÞ are defined in
between the two particles i and j given by (30). (39) and (40), respectively, for our minimization problem.
Rij ðtÞ ¼ Xi ðtÞ; Xj ðtÞ ; rNorm is usually 2 ð30Þ fitj ðtÞ
rNorm bestðtÞ ¼ min ð39Þ
j2f1;...;Ng
To give a stochastic characteristic to the algorithm, it is
fitj ðtÞ
expected that the total force that acts on ith particle in dth worstðtÞ ¼ max ð40Þ
j2f1;...;Ng
dimension be a randomly weighted sum of dth components
of the forces exerted from other particles given by (31). One way to perform a good compromise between explo-
ration and exploitation is to reduce the number of particles
X
N
Fid ðtÞ ¼ randj Fijd ðtÞ ð31Þ with lapse of generation cycles in (31). Hence, it is sup-
j¼1;j6¼i posed that a set of particles with bigger masses apply their

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forces to the other. However, this policy is to be adopted and C2 are the positive weighting factors; rand1 and rand2
carefully because it may reduce the exploration power and are the random numbers between 0 and 1; Xid ðkÞ is the
increase the exploitation capability. current position of ith particle vector in the dth dimension
In order to avoid trapping into a local optimum, the at kth iteration; pbestid ðkÞ is the personal best of ith particle
algorithm must use the exploration at the beginning. By lapse vector in the dth dimension at kth iteration; gbestd ðkÞ is the
of iterations, exploration must fade out and exploitation must group best of the group in the dth dimension at kth itera-
fade in. To improve the performance of GSA by controlling tion. The searching point in the solution space may be
exploration and exploitation, only the Kbest particles will modified by the following equation:
attract the others. Kbest is a function of generation cycle with
the initial value K0 and it decreases with generation cycle. In Xid ðk þ 1Þ ¼ Xid ðkÞ þ vdi ðk þ 1Þ ð43Þ
such a way, all particles apply forces at the beginning, and as The first term of (42) is the previous velocity of the particle
generation cycle progresses, Kbest is decreased linearly. At vector. The second and third terms are used to change the
the end, there will be just one particle applying force to the velocity of the particle. Without the second and third terms,
others. Therefore, (31) could be modified as (41). the particle will keep on ‘‘flying’’ in the same direction
X until it hits the boundary. Namely, it corresponds to a kind
Fid ðtÞ ¼ randj Fijd ðtÞ ð41Þ
of inertia represented by the inertia constant, w and tries to
j2Kbest;j6¼i
explore new areas.
In (41), Kbest is the set of first K particles with the best
fitness values and the biggest masses. 3.3 Gravitational search algorithm hybridized
with particle swarm optimization (GSA–PSO)
3.2 Particle swarm optimization (PSO)
In GSA–PSO, the next velocity of the particle vector is
considered as a fraction of its current velocity added to its
PSO is a flexible, robust population-based stochastic
weighted acceleration (provided by GSA) and weighted
search/optimization technique with implicit parallelism,
difference between the social/group best particle vector and
which can easily handle with non-differential objective
the present position (provided by PSO). It is to be noted
functions, unlike traditional optimization methods. PSO is
here that the first term and the third term are equivalent to
less susceptible to getting trapped on local optima unlike
the inertia term and the social/group best term, respec-
GA, Simulated Annealing, etc. Eberhart et al. [23, 24]
tively, of conventional PSO algorithm. Therefore, its
developed PSO concept similar to the behaviour of a
position and its velocity for the next cycle (t ? 1) are
swarm of birds. PSO is developed through simulation of
calculated by employing (44) and (45), respectively.
bird flocking in multidimensional space. Bird flocking
optimizes a certain objective function. Each particle (bird) vdi ðt þ 1Þ ¼ w  vdi ðtÞ þ c1  adi ðtÞ þ c2
 
knows its best value so far (pbest). This information cor-  gbestd ðtÞ  Xid ðtÞ ð44Þ
responds to personal experiences of each particle. More-
over, each particle knows the best value so far in the group where gbestd(t) is the dimension of the social or group best
(gbest) among pbests. Namely, each particle tries to modify particle vector corresponding to the best fitness best(t) in
its position using the following information: the whole population for the current cycle (t ? 1); The best
weighting factors (determined by 30 trial runs) are found
• The distance between the current position and the pbest as: w = 0.01; c1 = c2 = 1.0.
• The distance between the current position and the gbest
Xid ðt þ 1Þ ¼ Xid ðtÞ þ vdi ðt þ 1Þ ð45Þ
Similar to GA, in PSO techniques also, real-coded par-
ticle vectors of population np are assumed. Each particle The third factor of the velocity updating expression of
vector consists of components or sub-strings as required GSA–PSO represents the term involved with social best
number of design parameters need to be optimized. position of the particle vector. So, the updated position is
Mathematically, velocities of the particle vectors are not allowed to move in an apparently uncontrolled way as
modified according to the following equation: given by GSA, rather it is always restricted to follow the
social best position of the current iteration. This is the
Vid ðk þ 1Þ ¼ w  Vid ðkÞ þ C1  rand1
  reason that GSA–PSO has performed better than GSA and
 pbestid ðkÞ  Xid ðkÞ þ C2  rand2 PSO individually.
 
 gbestd ðkÞ  Xid ðkÞ ð42Þ The algorithmic steps of GSA–PSO are as follows:
where Vid ðkÞ is the velocity of ith particle in the dth Step 1. Initialization: Population (swarm size) of
dimension at kth iteration; w is the weighting function; C1 particle vectors, np(=60); dimension of

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optimization problem, D (=7); maximum xj ofi

iteration cycles (=200); maximum and mini- Sfxij  ð46Þ
fi oxj
mum bound for each design parameter. a is a
decrement factor for G. It is required for According to (46), there is one sensitivity for each objec-
reducing the acceleration continuously as tive function f and for each variable in X. Then, it is pos-
generation (iteration) cycle progresses from sible to define the multi-parameter sensitivity which sums
initial stage global search to final stage local the different single sensitivities regarding the different
search, since agents/particles are to be less variables for each objective as follows [77]:
perturbed during final stage local search than sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
Xn
f 2
fj
initial stage global search. Through experi- S ¼ Sxji r2xi ð47Þ
mentation by several trial runs, the best results i¼1
were obtained with a = 20; the other best f
where Sxji is calculated by (46); rxi is a variability param-
parameters of GSA–PSO are: G0 = 1,000;
eter of xi and the square root is used to preserve the same
rNorm = 2; rPower = 1; e = 0.0001; veloc-
units. In this way, the multi-parameter sensitivity for the
ity = zeros (np, D).
cost functions CFDiff Amp (for differential amplifier with
w = 0.01; c1 = c2 = 1.0. All these control
parameters as set have achieved good results current mirror load) and CFTwo stage Opamp (for two-stage
and good convergence. operational amplifier), respectively, can be calculated as:
vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
!
Step 2. Generate initial particle vectors of design u 6
u X CF 2 X 6 2
SCFDiff Amp ¼ t
parameters of number D randomly within CF
S Diff Amp r2 þ
Wi Wi S Diff Amp r2
Li Li
limits. i¼1 i¼1
Step 3. Computation of CF values of the total pop- ð48Þ
ulation, nP.
Step 4. Computation of the population based best SCFTwoStageOpamp
vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
!ffi
solution particle vector. u 8
u X CF 2 X 8 2
¼t
CF
Step 5. Update G(t), best(t), worst(t) and Mi(t) for S TwoStageOpamp r2 þ
Wi Wi S TwoStageOpamp r2
Li Li
i ¼ 1; 2; . . .; np ; t is current iteration cycle. i¼1 i¼1

Step 6. Calculation of the total forces in different ð49Þ

directions.
Step 7. Calculation of accelerations and velocities of where xi is replaced by variable transistor width parameter
particles. Wi or, variable transistor length parameter Li.
Step 8. Updating particles’ positions.
Step 9. Repeat Steps 3–8 until the stopping criterion 3.5 Various assumptions taken in algorithm portion
(maximum generation cycles) is met. and optimization problem
Step 10. Finally, gbest is the vector of optimal design
parameters (D). 3.5.1 Assumptions taken in the algorithmic portion (GSA)

Each particle attracts every other particle and the gravita-

3.4 Multi-parameter sensitivity analysis tional force between two particles is directly proportional
to the product of their masses and inversely proportional to
The relative or normalized sensitivity (s) can be defined the square of the distance (R) between them. Here R is used
as the cause and effect relationship between the circuit as RrPower where rPower = 1 because R1 offers better
elements’ variations, and the resulting changes in the results than R2 in all the experimental cases with bench-
performance responses [76, 77]. Furthermore, in the mark functions [63]. This is one deviation cum assumption
design of analog ICs, the lowest sensitivity is much from the exact Newton’s gravitation law.
desirable. Rij(t) is the Euclidian distance between the two particles
Let fi(x) be an objective function (performance i and j given by (30)/(50).
response), where X ¼ ½x1 ; . . .; xn T is the vector of the Rij ðtÞ ¼ Xi ðtÞ; Xj ðtÞ ; rNorm is assumed as 2:
rNorm
design variables. It is possible to relate small changes in the
 This is another assumption: ð50Þ
response of the performance ðofi ; i 2 ½1; mÞ to variations in
 
the design variables oxj ; j 2 ½1; n . It leads to the single The gravitational constant (G) is initialized at the
parameter sensitivity definition given by, beginning and will be reduced with generation cycle to

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control the search accuracy. In other words, G as a function involved with the social best position of the particle vector.
of the initial value (G) and generation cycle (t) is expressed So, the updated position is not allowed to move in an
as in (35)/(51). apparently uncontrolled way as given by GSA, rather it is
   always restricted to follow the social best position of the
t
G ¼ G0 exp a  ð51Þ current iteration. This is the reason that GSA–PSO has
maxGenCycles
performed better than GSA and PSO individually.
This is another deviation cum assumption from Newton’s
gravitation law, where G is assumed to be constant. 3.5.3 Assumptions taken for parameter selection
Gravitational and inertia masses are simply calculated for GSA–PSO
by the cost function (CF) evaluation. A heavier mass
means a much better particle. This means that better par- Through experimentation by several trial runs, the best
ticles have less attraction and move more slowly. results were obtained with a = 20; the other best param-
Another assumption taken in this algorithm is the eters of GSA–PSO are: G0 = 1,000; rNorm = 2; rPow-
equality of gravitational and internal masses. er = 1; e = 0.0001; velocity = zeros (np, D); w = 0.01;
fiti ðtÞ represents the fitness value of the ith particle at c1 = c2 = 1.0. The very small value of e (=0.0001) is
generation cycle t, worstðtÞ and bestðtÞ are defined in (39)/ chosen to avoid any divide-by-zero condition if two par-
(52) and (40)/(53), respectively, for our minimization ticles come very near to each other or, fall on each other.
problem.
bestðtÞ ¼ min fitj ðtÞ
ð52Þ 3.5.4 Assumptions taken for the actual design process
j2f1;...;Ng of the CMOS analog circuit
fitj ðtÞ
worstðtÞ ¼ max ð53Þ
j2f1;...;Ng The smallest value has been chosen for CC, which places
the pole, p2 at 2.2 times higher than the unity gain band-
This is another deviation from Newton’s gravitation law, width (UGB). For 60 phase margin it is assumed that right
where G is assumed to be constant. Gravitational and half plane (RHP) zero, z1 is beyond ten times of the UGB.
inertia masses are simply calculated by the cost function In order to minimize the channel length modulation
(CF) evaluation. A heavier mass means a much better effect, lengths of MOS transistors are chosen as L1 -
particle. This means that better particles have less attrac- = L2 = L3 = L4 = 3.5 lm and L5 = L6 = 1.4 lm for
tion and move more slowly. Another assumption taken in CMOS differential amplifier with current mirror load and
this algorithm is the equality of gravitational and internal 2 lm for CMOS two-stage operational amplifier circuit.
masses.
One way to perform a good compromise between
exploration and exploitation is to reduce the number of 4 Simulation results and discussions
particles with lapse of generation cycles in (31). Hence, it
is assumed that some particles with bigger masses apply Extensive MATLAB simulation has been performed for the
their forces to the others. However, this policy is to be optimal design of CMOS differential amplifier circuit with
adopted carefully because it may reduce the exploration current mirror load and CMOS two-stage op-amp circuit
power and increase the exploitation capability, which may (Figs. 1, 2) using the proposed GSA–PSO algorithm. The
yield sub-optimal solutions. results achieved by the GSA–PSO based designs are
compared with those results already reported in the existing
3.5.2 Assumptions taken in the algorithmic portion (GSA– literature like GA [37], CO [39], PSO [78–80], HS [79],
PSO) DE [79] and ABC [79]. The values of the input variables
used for this work are given in Table 1.
In GSA–PSO, the next velocity of the particle vector is All optimization programs were run in MATLAB
considered as a fraction of its current velocity added to its R2013a version on CPU Intel coreTM i5-2430M
weighted acceleration (provided by GSA) and weighted @3.00 GHz processor with 4 GB RAM. Circuit simula-
difference between the social/group best particle vector and tions were executed with Cadence version 5 (IC 5.1.41)
the present position (provided by PSO). It is to be noted with model parameters of Taiwan Semiconductor Manu-
here that the first term and the third term are equivalent to facturing Company (TSMC) 0.35 lm technology for vali-
the inertia term and the social/group best term, respec- dation purpose.
tively, of conventional PSO algorithm. The aim of this work is to minimize the total MOS
The third factor of the velocity updating expression of transistor area, power dissipation and maximizing the gains
GSA–PSO, inherited from PSO, represents the term of the amplifiers while satisfying performance parameters

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Table 1 Technology, inputs Inputs, technology, lengths Values considered

and lengths considered
Vdd (V) 2.5
Vss (V) -2.5
Vtp (V) -0.6513
Vtn (V) 0.4761
Kn (A/V2) 181.2
Kp (A/V2) 65.8
Technology 0.35 lm
Length (L)i in (lm) (Fig. 1) 3.5 for i = 1, …, 4 and 1.4 for i = 5, 6
Length (L)i in (lm) (Fig. 2) 2 for i = 1, 2, …, 8

as design specifications and design parameters. Specifying be drawn and then simulation has to be performed to val-
the design specifications and design parameters, the opti- idate the design specifications/performance parameters.
mal circuit sizing is aimed to be determined by the GSA– This section provides the simulation results obtained for
PSO algorithm for both the circuit design case studies. The the GSA–PSO based amplifier designs along with the
optimal design problem is formulated as minimization of comparative results reported in different recent literature.
Cost Function (CF) given by (24) by composing equations
consisting of design specifications and input variables as 4.1 Simulation results for CMOS differential amplifier
given by (22) or, (23). The task of GSA–PSO is to mini- with current mirror load
mize the CF. Initially the design optimization requires two
types of information. The first one is the technology and The proposed GSA–PSO is employed for the optimal
the power supply, which are set by the designer. The sec- design of a CMOS differential amplifier with current mir-
ond one is the design criteria. The range of design ror load having inputs, design specifications and design
parameters, design specifications, power supply values and parameters are shown in Tables 1 and 2. In order to min-
technology information are set as inputs to the GSA–PSO imize the channel length modulation effect, lengths of
optimization technique and the optimal solution set is MOS transistors are chosen as L1 = L2 = L3 = -
obtained, which comprises of the optimal values of design L4 = 3.5 lm and L5 = L6 = 1.4 lm as shown in Table 1.
parameters (Wi/Li) where (i = 1, 2, …, 6) for CMOS The desired value of CF is targeted to be smaller than
differential amplifier with current mirror load and (i = 1, 300 lm2. The simulation results show that by using GSA–
2, …, 8) for CMOS two-stage op-amp circuit. GSA–PSO PSO, the least total MOS transistor area of 238.28 lm2
algorithm was run for 100 times to get the best sets of with the exact values of design specifications and design
optimized device parameters and the best results have been parameters (Wn, Wp, Ibias and CL) are obtained in 1.0293 s.
reported in this paper. CMOS differential amplifier circuit with current mir-
During its development, PSPICE has evolved into an ror load is practically redesigned by using the optimal
analog mixed signal simulator. The software, now devel- design parameters (shown in the last column of Table 4)
oped towards more complex industry requirements, is obtained by employing GSA–PSO algorithm in SPICE
integrated in the complete systems design flow in ORCAD simulator to validate the fact that GSA–PSO based
and Cadence. It includes features such as analysis of a design is satisfying the desired specifications. The
circuit with automatic optimization, encryption, a model SPICE simulation results obtained from the optimally
editor, and support for parameterized models, auto-con- designed CMOS differential amplifier with current mir-
vergence and checkpoint restart. ror load are shown in Figs. 3, 4, 5, 6, 7, 8, 9, 10,
Circuit simulations were executed with Cadence version respectively. SPICE simulation results justify that the
5 (IC 5.1.41) with model parameters of Taiwan Semicon- proposed GSA–PSO based differential amplifier circuit
ductor Manufacturing Company (TSMC) 0.35 lm tech- design not only satisfies all design specifications and
nology for validation purpose. The authors have chosen design parameters but also minimizes the total area
Cadence for validation of the models but other than occupied by the MOS transistors in comparison with GA
Cadence, TSPICE or PSPICE can also be used for vali- [37], PSO [78], HS [79], DE [79] and ABC [79]. The
dation purpose. Compared to TSPICE or PSPICE, Cadence comparison summary is shown in Tables 3. The values
is much user-friendly and it does not require program for of the optimal design parameters achieved by using
simulation of the model circuit. Another high end analog GSA–PSO as well as those values reported in existing
circuit simulator is HSPICE. In Cadence, the circuit has to literature are given in Table 4.

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Table 2 Constraints of the Outputs Ranges considered

proposed GSA–PSO based
analog circuit design method CMOS differential amplifier CMOS two-stage
with current mirror load operational amplifier

SR (V/ls) C10 C10

Av (V/V) [100 [1,000
CL in (pF) C4 C7
CC in (pF) Not required C2.5
UGB in (MHz) Not required C3
f-3dB (cut-off) in (KHz) C100 Not required
Aspect ratio (Wi/Li) 100 C (Wi/Li) C 3 100 C (Wi/Li) C 2
ICMR in (V) -1.5 B ICMR B 2 -1.5 B ICMR B 2
Pdiss (lW) B2,000 B2,500

Fig. 3 Plots of gain and phase

of the proposed GSA–PSO
based CMOS differential
amplifier circuit with current
mirror load

Fig. 4 Plot of slew rate of the

proposed GSA–PSO based
CMOS differential amplifier
circuit with current mirror load

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Fig. 5 Plot of positive PSRR of

the proposed GSA–PSO based
CMOS differential amplifier
circuit with current mirror load

Fig. 6 Plot of negative PSRR

of the proposed GSA–PSO
based CMOS differential
amplifier circuit with current
mirror load

Fig. 7 Plot of CMRR of the

proposed GSA–PSO based
CMOS differential amplifier
circuit with current mirror load

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Fig. 8 Plots of ICMR along

with ID5 and (VGS - Vtn) of the
proposed GSA–PSO based
CMOS differential amplifier
circuit with current mirror load

Fig. 9 Plot of power

dissipation of the proposed
GSA–PSO based CMOS
differential amplifier circuit
with current mirror load

Fig. 10 Plot of propagation

delay of the proposed GSA–
PSO based CMOS differential
amplifier circuit with current
mirror load

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Figure 3 shows the plots of gain and phase, Fig. 4 shows amp is redesigned using the optimal transistor sizes
the plot of slew rate, Fig. 5 shows the plot positive Power achieved by using GSA–PSO in SPICE simulator in order
Supply Rejection Ratio (PSRR?), Fig. 6 shows the plot of to validate the fact that the GSA–PSO based design meets
negative Power Supply Rejection Ratio (PSRR-), Fig. 7 the design specifications.
shows the plot of Common Mode Rejection Ratio Figure 11 shows the plots of gain and phase, Fig. 12
(CMRR), Fig. 8 shows the plot of power dissipation, Fig. 9 shows the plot slew rate, Fig. 13 shows the plot of PSRR?,
shows the plots of minimum and maximum Input Common Fig. 14 shows the plot of PSRR-, Fig. 15 shows the plot of
Mode Range (ICMR) along with ID5, VDS1 and (VGS1 - CMRR, Fig. 16 shows the plots of maximum and the
Vin). Figure 10 shows the plot of propagation delay. minimum ICMR along with ID5, VDS1 and (VGS1 - Vin),
Vural et al. [78, 79] employed PSO, HS, DE and ABC Fig. 17 shows the plot of power dissipation, Fig. 18 shows
techniques to design the same circuit considered in this the plot of propagation delay.
paper. The results reported in [78] show that the small Vural et al. [78, 80] employed PSO algorithm for the
signal differential voltage gain Av of 42 dB, CMRR of optimal design of two-stage op-amp circuit and the said
84.2 dB, PSRR? of 40.1 dB, PSRR- of 68 dB, power design is reported to have unity gain bandwidth (UGB)
dissipation of 1,260 lW and total MOS area of 296 lm2 of 5.32 MHz, DC voltage gain Av of 63.8 dB, CMRR of
have been achieved using PSO algorithm. In this paper, the 83.74 dB, PSRR? of 78.27 dB PSRR- of 93.56 dB,
proposed GSA–PSO based design is shown to have all power dissipation of 2,370 lW and total MOS area of
higher Av, CMRR, PSRR?, PSRR- and the least total 265 lm2.
MOS area as 44.52, 93.23, 48, 110.4 dB and 238.28 lm2, In this paper, GSA–PSO based two-stage op-amp circuit
respectively. All the design specifications are shown in design approach results in much improved superior values
Figs. 3, 4, 5, 6, 7, 8, 9, 10 and Table 3. The optimal design of UGB, Av, CMRR, PSRR?, PSRR-, the least power
parameters achieved by using GSA–PSO algorithm for the dissipation and the least total MOS transistor area of
design of CMOS differential amplifier circuit with current 5.776 MHz, 75.43, 87, 83.2, 110.4 dB, 712.8 lW and
mirror load are shown in Table 4. Power dissipation across 109.6 lm2, respectively, as compared with the results of
the transistors present in the circuit under consideration is PSO based approach reported in [78, 80]. All the design
the grand least (=511.6 lW) as compared with those of specifications are shown in Figs. 11, 12, 13, 14, 15, 16, 17,
other recent works [78, 79], except [37]. and 18 and Table 5 The optimal design parameters which
So, from Figs. 3, 4, 5, 6, 7, 8, 9, and 10 and Tables 3 and have been achieved by using GSA–PSO algorithm for the
4, it can be noted that the proposed GSA–PSO based design of the CMOS two-stage operational amplifier circuit
CMOS differential amplifier design technique is shown to are as follows and are also given in Table 6.
have the least MOS area, much superior improved gain, The best values obtained for all the performance
power supply rejection ratio, common mode rejection ratio parameters and the objective function (least MOS area)
and total power dissipation as compared with those results prove GSA–PSO to be the best optimizer for this design.
reported in the recent literature [37, 78, 79]. So, GSA–PSO Extensive SPICE simulations have been carried out to
optimizes the best optimizer for this optimal design. validate the design of the CMOS two-stage op-amp circuit
using the optimal device sizes (shown in the last column of
4.2 Simulation results for two-stage operational Table 6) obtained by using GSA–PSO algorithm. SPICE
amplifier simulations (Figs. 11, 12, 13, 14, 15, 16, 17, 18) demon-
strate that the proposed GSA–PSO based design not only
GSA–PSO is also utilized for the optimal design of CMOS satisfies all the design specifications and design parameters
two-stage op-amp having inputs, design specifications and but also minimizes the total area occupied by the MOS
design parameters are all shown in Tables 1 and 2. In order transistors, and also the total power dissipation as com-
to minimize the effect of the channel length modulation, pared with CO based method [39] and PSO based method
the length of each MOS transistor is chosen as 2 lm [75]. [78, 80]. The different performance specifications of the
The target value of CF is set to be smaller than 300 lm2. designed two-stage op-amp circuit using GSA–PSO are
The proposed GSA–PSO based optimal design of two- shown in Table 5 along with those results reported in dif-
stage op-amp results in the least total MOS transistor area ferent literature. Table 6 shows the optimal design
of 109.6 lm2 along with the exact values of the design parameters achieved for CMOS two-stage operational
specifications and the optimizing design parameters (Wn, amplifier circuit based on GSA–PSO algorithm. Table 6
Wp, Ibias, CC and CL). The design steps are completed after also shows the different optimal design parameters repor-
a total execution time of 0.5966 s. CMOS two-stage op- ted in different literature.

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Table 3 Comparison of design criteria/specifications of CMOS differential amplifier with current mirror load
Design criteria Specifications GA [37] PSO [78] HS [79] DE [79] ABC [79] GSA–PSO

Output capacitance (pF) C4 2 5 5 5 5 4

SR (V/ls) C10 3.2 22.4 14.916 18.451 15.67 16.77
Power dissipation (lW) B2,000 31 1,260 886 990 830 511.6
Phase margin () [45 72 83.8 89.1 88.81 91.248 82.74
Cut-off frequency (kHz) C100 NR* 100 114 129.7 112.367 100
Gain (dB) [40 60 42 40.98 41.23 42.045 44.52
VIC (min) (V) C-1.5 -1.3 -0.8 -0.7 -0.92 -0.97 -0.365
VIC (max) (V) B2 1.9 1.4 1.2 1.15 1.2 1.717
CMRR (dB) [40 NR* 84.2 78.5 78.39 79.67 93.23
?
PSRR (dB) [40 NR* 40.1 42.93 43.14 43.857 48
PSRR- (dB) [40 NR* 68 67.64 68.175 68.423 110.4
Total MOS area (lm2) \300 6,500 296 NR* NR* NR* 238.28
NR*: not reported in the refereed literature

Table 4 Design parameters obtained for CMOS differential amplifier MOS area as compared with the previously reported recent
with current mirror load literature.
Design parameters GA [37] PSO [78] GSA–PSO
4.3 Plot of convergence profiles of the proposed GSA–
Ibias (lA) 2 125 119.03
PSO
W1/L1 (lm/lm) 240/13.2 29.4/3.5 25/3.5
W2/L2 (lm/lm) 240/13.2 29.4/3.5 25/3.5 The convergence profile plot of GSA–PSO algorithm for
W3/L3 (lm/lm) 7.3/7.7 11.3/3.5 7.5/3.5 the differential amplifier circuit has been shown in Fig. 19.
W4/L4 (lm/lm) 7.3/7.7 11.3/3.5 7.5/3.5 The total area occupied by the MOS transistor is of
W5/L5 (lm/lm) 4.6/2.4 4.2/1.4 2.9/1.4 238.28 lm2 and the total time taken for the execution is
W6/L6 (lm/lm) 2.4/2.4 4.2/1.4 4.8/1.4 1.0293 s for 200 number of fitness evaluations (which is
CL (pF) 2 5 4 computed as product of number of cost function evaluations
per generation cycle and number of generation cycles).
Figure 20 shows the plot of convergence profile of the
Thus, GSA–PSO based optimal CMOS analog amplifier proposed GSA–PSO for the two-stage operational amplifier
circuit design technique ensures to have a much improved circuit. The total area has been occupied by the MOS
voltage gain, power supply rejection ratio, common mode transistor is 109.6 lm2 and the total time taken for the
rejection ratio, power dissipation and as well as the total execution is 0.5966 s for 200 number of fitness evaluations

Fig. 11 Plots of gain and phase

of the proposed GSA–PSO
based CMOS two-stage
operational amplifier circuit

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Fig. 12 Plot of slew rate of the

proposed GSA–PSO based
CMOS two-stage operational
amplifier circuit

Fig. 13 Plot of positive PSRR

of the proposed GSA–PSO
based CMOS two-stage
operational amplifier circuit

Fig. 14 Plot of negative PSRR

of the proposed GSA–PSO
based CMOS two-stage
operational amplifier circuit

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Fig. 15 Plot of CMRR of the

proposed GSA–PSO based
CMOS two-stage operational
amplifier circuit

Fig. 16 Plots of ICMR along

with ID5 and (VGS - Vtn) of the
proposed GSA–PSO based
CMOS two-stage operational
amplifier circuit

(which is computed as product of number of cost function 5 Conclusions

evaluations per generation cycle and number of generation
cycles). In this paper, a hybrid evolutionary optimization technique
From the convergence plots, it is evident that GSA–PSO based on GSA–PSO algorithm is employed for the optimal
achieves the near-global optimal minimum values of total designs of CMOS differential amplifier with current mirror
MOS area in less than 100 number of fitness evaluations load and CMOS two-stage operational amplifier circuit.
for each circuit design. So, GSA–PSO algorithm optimizes The optimal designs are aimed to be met by optimizing the
the best for the present study. design specifications such as slew rate, gain, power dissi-
pation, etc. The design equations are utilized for the cost
4.4 Plot of multi-parameter sensitivity function considering those several conflicting design
specifications. The design parameters such as widths of
Figure 21 shows the plot of multi-parameter sensitivity of MOS transistors, DC bias current, etc., achieved by
CFDiff Amp evaluated by (45), with r ¼ 1 for the differen- employing GSA–PSO algorithm are utilized for the rede-
tial amplifier with current mirror load. Figure 22 shows the sign of the circuits in SPICE simulator in order to validate
plot of multi-parameter sensitivity of CFTwoStageOpamp the exact values of design specifications/performance
evaluated by (46), with r ¼ 1 for the two-stage operational parameters obtained. Simulation results prove that each
amplifier. So, the optimal designs of two CMOS analog GSA–PSO based analog circuit design not only meets all
circuits are guaranteed. design specifications but also minimizes the total MOS

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Fig. 17 Plot of power

dissipation of the proposed
GSA–PSO based CMOS two-
stage operational amplifier
circuit

Fig. 18 Plot of propagation

delay of the proposed GSA–
PSO based CMOS two-stage
operational amplifier circuit

area and the power dissipation with respect to the previ- multidimensional search space, where the other reported
ously reported methods. GSA–PSO is proved to have algorithms are entrapped to suboptimal solutions. Hence, it
superior performance for CMOS differential amplifier with can be inferred that the proposed GSA–PSO based CMOS
current mirror load with much improved gain, CMRR, amplifier designs are the best in comparison with those
PSRR?, and PSRR- and the total power dissipation, the resulted in by the other reported techniques.
least total MOS area with respect to other reported litera- Automation of CMOS analog circuit optimization is a
ture. GSA–PSO based approach is also found to have very difficult and time consuming task. The emphasis of
superior performance for the CMOS two-stage operational this work is optimal designing of CMOS differential
amplifier with improved UGB, gain, CMRR, PSRR?, amplifier with current mirror load and CMOS two-stage
PSRR-, total power dissipation and the least total area operational amplifier circuits. After successful execution of
occupied by the MOS transistors in comparison with those the program in MATLAB, minimum area is achieved in
of other reported methods. From the simulation study, it is terms of design parameters. But some difficulties have been
established that the proposed GSA–PSO based optimiza- faced during the design. When the W values and L values
tion technique adopted for the analog IC optimization is are put in Cadence, some parameters are conflicting with
efficient in finding the near-global optimal solution in each other. For example, when gain increases, the phase

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Table 5 Comparison of design Design criteria Specifications CO [39] PSO [78, 80] GSA–PSO
criteria/specifications of CMOS
two-stage operational amplifier Output capacitance (pF) C7 3 10 7.2
Slew rate (V/ls) C10 88 11.13 10.88
Power dissipation (lW) B2,500 5,000 2,370 712.8
Phase margin () [45 60 66.55 66.2
Unity gain bandwidth (MHz) C3 86 5.32 5.776
Gain (dB) [60 89.2 63.8 75.43
VIC (min) (V) C - 1.5 NR* -0.8 -0.886
VIC (max) (V) B2 NR* 1.75 1.9
CMRR (dB) [60 92.5 83.74 87
PSRR? (dB) [70 116 78.27 83.2
-
PSRR (dB) [70 98.4 93.56 110.4
NR*: not reported in the Total MOS area (lm2) \300 8,200 265 109.6
refereed literature

Table 6 Design parameters obtained for CMOS two-stage opera- -10

x 10
tional amplifier 1.106
Design parameters CO [39] PSO [78, 80] GSA–PSO 1.105

1.104
Ibias (lA) 10 40.39 28
Total MOS Area (mxm) 1.103
W1/L1 (lm/lm) 232.8/0.8 4.9/2 4/2
W2/L2 (lm/lm) 232.8/0.8 4.9/2 4/2 1.102
W3/L3 (lm/lm) 143.6/0.8 5.9/2 4/2 1.101
W4/L4 (lm/lm) 143.6/0.8 5.9/2 4/2 1.1
W5/L5 (lm/lm) 64.6/0.8 2.1/2 2.8/2
1.099
W6/L6 (lm/lm) 588.8/0.8 90.9/2 24/2
1.098
W7/L7 (lm/lm) 132.6/0.8 16.3/2 9.2/2
W8/L8 (lm/lm) 2/0.8 2.1/2 2.8/2 1.097

CL (pF) 3 10 7.2 1.096

0 20 40 60 80 100 120 140 160 180 200
Cc (pF) 3.5 3 2.8 Number of fitness evaluations

Fig. 20 Plot of Convergence profile of the proposed GSA–PSO for

two-stage operational amplifier

-10
x 10 0.7745
2.398
0.774
2.396
0.7735
Total MOS Area (mxm)

2.394
0.773
SCFDiff-Amp

2.392
0.7725

2.39 0.772

2.388 0.7715

2.386
0.771

0.7705
2.384
0.77
2.382 2.382 2.384 2.386 2.388 2.39 2.392 2.394 2.396 2.398 2.4
0 20 40 60 80 100 120 140 160 180 200 -10
CF Diff-Amp
x 10
Number of fitness evaluations

Fig. 19 Plot of Convergence profile of the Proposed GSA–PSO for Fig. 21 Plot of multi-parameter sensitivity of CFDiff Amp for differ-
differential amplifier with current mirror load ential amplifier with current mirror load

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