Journal of Telecommunication, Electronic and Computer Engineering

ISSN: 2180 – 1843 e-ISSN: 2289-8131 Vol. 16 No. 4 (2024) 37 – 46

jtec.utem.edu.my
DOI: https://doi.org/10.54554/jtec.2024.16.04.006

AI-Driven Automation for Analog and Mixed-Signal Circuit Design:

Schematic to GDSII Layout
Jiveya Sri Sockalingam1, Yan Chiew Wong1*, Ser Lee Loh1, Ranjit Singh Sarban Singh2, T. Joseph Sahaya Anand3
1Faculty of Electronics and Computer Technology and Engineering, Universiti Teknikal Malaysia Melaka (UTeM),
76100 Durian Tunggal Melaka, Malaysia.
2School of Engineering and Technology, Sunway University, Selangor, Malaysia.
3School of Computing, MIT Vishwaprayag University, Solapur, 413255, India .

Article Info Abstract

Article history: As technology propels forward and circuits evolve into intricate and complex designs, the traditional
Received Jul 1st, 2024 manual circuit design approach finds itself at a crossroads. With cutting-edge processes
Revised Nov 5th, 2024 introducing many challenges, the journey from concept to creation has become increasingly
Accepted Dec 17th, 2024 arduous, demanding significant time investments. To overcome these challenges, automation
Published Dec 20th, 2024 emerges as a key innovation, accelerating product development while ensuring precision. This
study explores analog circuit design by investigating the architecture of an analog and digital circuit
Index Terms: generator and pioneering an automated synthesis method called “correct-by-construction”. This
Reinforcement Learning innovative approach optimizes the design process while prioritizing accuracy from the outset.
Neural Network Additionally, this study evaluates the performance of analog generators, focusing on accuracy and
Automatic analog circuit circuit metrics using AutoCkt. Tools such as ALIGN for automated layout generation and
Automated layout OpenFASoC for digital design automation further enhance efficiency and accessibility in analog
Automated mixed signal circuit design. The integration of these tools, alongside their compatibility with open-source CAD
Op-amp platforms, demonstrates significant advancements in automation. Furthermore, the development
Ring Oscillator of a graphical user interface (GUI) provides a user-friendly platform for interacting with various
ADC functionalities related to circuit design and simulation, enhancing the overall design workflow.
This is an open access article under the CC BY-NC-ND 4.0 license.

*Corresponding Author: ycwong@utem.edu.my

particularly in the domains of analog circuit design,

I. INTRODUCTION validation, and integration [2]. Manual circuit design, due to
the myriad design criteria and specifications inherent in
For decades, analog integrated circuit (IC) layouts have been contemporary complex circuits and substantial process
considered as works of art due to their lack of standardized variability, is a challenging, time-consuming, and often
design styles, unlike their digital counterparts [1]. Crafting inefficient endeavor [3]. Given these challenges, automated
the correct analog layout is a complex and time-consuming analog circuit generation emerges as a necessity. While
task, demanding significant design effort despite the ongoing initiatives aim to achieve fully automated end-to-end
relatively small footprint of analog circuits. Traditionally, this design using machine learning and other automation
process has been carried out using computer-aided design techniques, these efforts remain a work in progress and
(CAD) tools, with designs either manually created by skilled require verification for accuracy and practicality [4, 5]. The
designers or generated by computational tools. As technology key processes in basic schematic circuit design involve
advances, the challenges associated with innovating circuits determining the circuit's topology and the values of its
within complex systems have increased. Detailed design rules elements, such as sizing to meet specific parameters. Model-
and layout parasitic in advanced processes require substantial based approaches stand out as prominent techniques in
design time for circuits to reach the tape-out stage. This automated circuit sizing, encompassing non-convex
process has traditionally been managed by human designers, polynomial optimization, deep neural networks (DNN), and
who iteratively adjust circuit parameters to meet design geometric programming [6], [7].
targets, relying heavily on their expertise to formulate In summary, previous work on automation presents
equations and find solutions. To reduce time-to-market, it has promising and successful approaches to diverse aspects of the
become crucial to automate these time-consuming procedures ASIC design process. Methodologies vary significantly based
in a simulation-efficient and accurate manner. on the specific sub-problems they address, with distinctions
To meet the evolving requirements of modern System-on- in the level of automation, generalizability, accuracy, and
Chip (SoC) design, automation is increasingly indispensable, interpretability of these approaches.

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Journal of Telecommunication, Electronic and Computer Engineering Vol. 16 No. 4 (2024)

Aligned with these considerations, the primary objective An Autonomous System-on-Chip (SoC) Design
of this paper is to develop an automatic circuit generator Framework introduced in 2021 promised faster design times
utilizing deep neural network (DNN) technology. This and reduced Non-Recurring Engineering (NRE) costs.
automatic circuit generator aims to create a comprehensive However, the framework was hindered by manual layout
System-on-Chip (SoC) synthesis tool, guiding the process requirements and process-specific constraints [23].
from user specifications to GDSII. This tool leverages In this work, we propose an automated analog circuit
innovative technology to automatically synthesize “correct- generator leveraging multiple open-source Electronic Design
by-construction” Verilog descriptions for analog circuits, Automation (EDA) tools such as AutoCkt, Xschem, ALIGN,
enabling a portable, single-pass implementation flow [4]. and OpenFASOC. These tools were selected for their
Additionally, the paper aims to evaluate and analyze the capabilities to incorporate deep neural networks, enabling the
performance of analog generators in terms of accuracy and system to learn from experience and adapt to various circuit
circuit performance. types. AutoCkt employs deep reinforcement learning to
optimize circuit designs efficiently, while Xschem provides a
II. LITERATURE REVIEW versatile schematic capture tool. ALIGN facilitates analog
layout automation, and OpenFASOC integrates machine
Automated analog circuit optimization has progressed learning techniques for circuit synthesis and optimization to
significantly, reducing the need for human expertise. automate analog mixed signals. Together, these tools enable
Methods include reinforcement learning (RL) for parallel a comprehensive and adaptive approach to analog circuit
circuit design predictions [8], machine learning (ML) design, aligning with diverse design objectives and
combining neural networks and RL for autonomous circuit improving design efficiency and accuracy.
sizing [9], and deep learning models for automated placement
in circuit layout design [10]. Techniques like Generalized III. METHODOLOGY
Differential Evolution 3 (GDE3) and Gaussian Processes
efficiently optimize complex circuits with conflicting This methodology integrates a system to automate and
objectives [11]. Key steps in transforming a netlist into a optimize the design of analog circuits, analog layouts, and
layout involve partitioning the netlist [12][13][14], automated mixed-signal ICs. By combining advanced machine learning
layout stitching [15], and customizable logic device layout techniques with traditional Electronic Design Automation
generation [16]. Designing analog and mixed-signal (AMS) (EDA) tools, the system enhances design efficiency and
IP blocks on advanced technologies like FinFET or GAAFET effectiveness. The integrated system includes four key
is challenging due to the schematic-post-layout simulation components: AutoCkt, Xschem, ALIGN, and OpenFASoC,
gap, complex design rules, and reliability requirements. each providing unique functionalities to the workflow.
Recent research has focused on layout synthesis using ML
advancements, with studies showing potential improvements A. Automated Analog Circuit Design
using Boolean satisfiability-based routing algorithms and AutoCkt is a machine learning framework designed to
verifiable constraint languages [17]. solve analog circuit design problems. By training on a sparse
Deep Reinforcement Learning (DRL) has been developed sub-sample of the design space, AutoCkt significantly
for designing analog-integrated circuits such as operational reduces convergence time and efficiently meets various new
amplifiers. This method uses trial and error to find optimal design specifications. It takes three inputs: a circuit netlist, a
designs, building circuits from basic components with custom simulation testbench, and target design specifications. Using
rules and improving efficiency through hash tables and this information, AutoCkt determines the circuit parameters
symbolic analysis, achieving effective designs in a few hours to ensure the design meets the specified requirements. The
[18]. Similarly, reinforcement learning was used in AutoCkt GUI for AutoCkt allows users to easily select between two-
to design two-stage operational amplifiers, showing stage op-amp and ring oscillator circuits and includes a reset
efficiency in sparse subsampling and converging 25 times button and a help button to assist novice users.
faster than standard methods, with a 40-fold speedup for
subsequent circuits [19]. Another approach proposed a DNN-
based framework for RL-inspired circuit optimization,
demonstrating improved performance and reduced design
time, although it relies on accurate DNN predictions and fine-
tuning of hyperparameters [20].
The transformation of a netlist into a physical layout using
electronic design automation (EDA) involves key steps such
as partitioning, floor planning, placement, and routing. These
processes are supported by advanced tools tailored for both
digital and analog designs, ensuring functional correctness
Figure 1: Automated Analog Circuit Design
and compliance with manufacturing standards. Resolution
enhancement techniques (RET) are also essential for refining
The graphical user interface of AutoCkt provides a
layout quality [21]. Additionally, an open-source framework
seamless navigation experience, allowing users to easily
developed for automating analog layout generation using
transition between different functions. When selecting the
machine learning and graph-based recognition aimed to
Two Stage Opamp option, users are directed to the Two Stage
minimize human intervention but faced limitations due to
Opamp Options Window, where they can access five options
proprietary Process Design Kits (PDKs) [22].
tailored to their needs, such as updating target specifications,
running scripts, and accessing external tools like IPython and
Tensorboard. This structured approach enhances productivity

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 Journal of Telecommunication, Electronic and Computer Engineering Vol. 16 No. 4 (2024)

and user satisfaction by making it easy to perform tasks relative specification, adjusting the handling for ‘ibias_max’
related to circuit design. The intuitive layout and clear by inverting its sign. For negative relative specifications, their
labeling help users quickly locate and utilize the desired values are added to the reward, and 0 is appended to
functionalities to optimize circuit parameters based on target ‘pos_val’; otherwise, 1 is appended. Finally, if the computed
design specifications. reward is less than -0.02, it returns the reward, otherwise, it
defaults to 10, ensuring no penalty for exceeding the
B. AutoCkt Framework specification in AutoCkt. This approach enhances the
In AutoCkt, the system comprises two main components: efficiency of the proximal policy optimization algorithm’s
the RL agent, responsible for decision-making, and the circuit training process.
simulation environment, where decisions are executed and
evaluated. Reinforcement Learning (RL) is a subset of
machine learning that involves an agent interacting with its
environment through trial and error, mimicking human
learning. This approach uses a simulation-in-the-loop
framework, requiring validation of outputs against a reliable
simulation source.
At each step, the RL agent, equipped with a neural
network, observes the state of the environment and selects an
action from a probabilistic distribution. This process balances
exploration and exploitation, enabling the agent to discover
new possibilities while leveraging its existing knowledge to
maximize rewards. After selecting an action, the environment
transitions to a new state, and the reward for that action is
calculated. This iterative process continues across a trajectory
of multiple steps, with rewards accumulating until the target
is achieved or a maximum step limit is reached.
In this scenario, N refers to the array of parameters that
need to be adjusted within a circuit, including transistor
lengths and widths. M refers to the various target design
specifications that the circuit aims to achieve post-training,
such as gain and bandwidth. Together, these variables Figure 2: Calculating Reward in AutoCkt
encompass a wide range of performance goals and
requirements. The parameter space, denoted as x ∈ ZN, and In AutoCkt, a three-layer neural network with 64 neurons
the target design specifications space, labeled as y ∈ RM, are per layer facilitates the mapping between states and actions
standardized to a predefined range, ensuring uniformity and in the reinforcement learning framework, as depicted in
comparability across different parameters and specifications. Figure 2. This architecture was chosen for its ability to
Initially spanning RN, the parameter space is discretized into manage the complexity of adjusting parameters to meet target
K grids: {x ∈ ZN: 0 ≤ xi ≤ K, i= 1,…,N}. The system generates specifications without fixating excessively on specific circuit
L trajectories, each with targets chosen from the set of M components. Within this reinforcement learning algorithm,
specifications. The reward for each trajectory is calculated by the network takes inputs including current performance (o),
summing the rewards for each action, which are determined target specifications (o*), and current parameters (p). It
by the differences between the actual circuit performance (o) outputs a probabilistic distribution from which samples are
and its target specification (o*), normalized and bounded, and drawn to determine whether to increase, decrease, or maintain
then multiplied by a scaling constant, β as shown below: each circuit parameter. This approach enables adaptive
parameter adjustments based on the circuit’s current state and
𝑜−𝑜∗ desired performance goals.
𝑟𝑜 = 𝑚𝑖𝑛 (𝛽 , 0) (1)
𝑜+𝑜∗ When the agent is deployed, it is trained to create paths
𝑟 = ∑ 𝑟𝑜 (2) using distinct target requirements derived from o* (‘target
𝑜∈𝑜 design specification’). This training setting may differ from
the simulation environment. After comparing the target
For metrics being maximized, β is set to 1, while for design specification (o*) with the final specification o
metrics being minimized, β is set to -1. For minimized metrics produced by the trajectory, the corresponding counter is
that are not strict constraints, such as power, β is assigned a incremented.
value within the range -1 < β < 0. More negative rewards are
given for greater deviations below the target metrics being C. Automated Analog Layout Generation
maximized or for exceeding the metrics being minimized. ALIGN automates the layout generation process with a
Over satisfying any one metric results in no reward for the user-friendly graphical interface (GUI), as shown in Figure 3.
agent, with 𝒓𝒐 being set to zero in such cases. This GUI integrates tools like Xschem for schematic capture,
Figure 2 presents a reward method that calculates a reward facilitating hierarchical circuit representation and netlist
based on the differences between current specifications creation in formats such as VHDL, spice netlist, Verilog, or
(‘spec’) and desired goal specifications (‘goal_spec’). It tEDAx. Users can select and run these tools via radio buttons
begins by computing these differences using a 'lookup' on the main window, which also features a welcome message,
method and initializes an empty list ‘pos_val’ along with a option display, and navigation buttons for user convenience.
reward variable set to 0.0. The method iterates through each This setup streamlines operations, reduces manual effort, and

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improves layout accuracy, ensuring a smooth and efficient on generating analog components from high-level
user experience. specifications using a combination of machine learning and
traditional EDA techniques. OpenFASOC includes a
graphical user interface (GUI), as shown in Figure 5, that
simplifies tasks such as file uploading, viewing Verilog files,
logs, results, and generated GDS files from ALIGN processes
with a single click. This interface enhances efficiency and
productivity in circuit design workflows, and is designed to
be user-friendly for individuals with minimal technical
expertise.

Figure 3: Automated Layout Generation based on Xschem and ALIGN.

D. ALIGN Framework
ALIGN is an open-source automatic layout generator for
analog circuits. Figure 4 shows the five key components that
make up the ALIGN flow:

Figure 5: Automated Mixed Signal Circuit based on OpenFASoC.

F. OpenFASoC Framework
Figure 6 provides a high-level overview of the
OpenFASoC framework. The initial setup involved creating
aux-cells and generator models for the process design kit
(PDK), a step performed once. The process began by
Figure 4: Key Modules of ALIGN [ 24]
translating high-level user intent into analog specifications
that adhered to user constraints. This included generating the
• Design Rule Capture translates the proprietary Process SoC layout by assembling the design components, executing
Design Kit (PDK) into guidelines for the layout generator. an automatic place and route flow, and utilizing block
Simplified versions for advanced process nodes (10 nm, 7 generators as needed. This comprehensive process
nm, 22 nm) enable layout tools to understand PDK transformed user requirements into a finalized SoC layout
features, including enforced grid stops, minimum length efficiently within the automated framework of OpenFASoC.
design rules, metal spacing, and width/spacing grids for
each layer.
• Netlist auto-annotation in ALIGN identifies geometric
constraints for each block and organizes passives and
transistors into building blocks. Representing the netlist
as a graph, it uses machine learning to recognize
conventional structures, mimicking the pattern
recognition abilities of experienced designers.
• Electrical Constraint Generation translates performance
limitations, such as maximum route lengths, into layout
constraints for sub-blocks. These guidelines define
parameters like route lengths and parasitic requirements,
ensuring compliant and optimized layouts at all
hierarchical levels.
• Parameterized Layout Generation at the lowest ALIGN
hierarchy level automatically generates layouts for
primitives based on variables like transistor size, MOM
capacitance, and serpentine resistance. Parameterized
templates, adhering to PDK grids, ensure design rule
compliance and correct PDK abstraction interfacing.
• Block Assembly organizes blocks according to the design
hierarchy, with primitives using fixed-shape placement
methods to generate multiple layout options. Higher Figure 6: FASoC Architecture
levels use flexible forms and placement algorithms to
create compact layouts, while adhering to geometric and OpenFASoC employed a synthesizable cell-based
electrical constraints. approach to create analog blocks, significantly reducing
manual layout and verification efforts, as depicted in Figure
E. Mixed Signal IC Design 7. These small analog circuits, called aux-cells, augmented
Open-Source Fully Autonomous SOC, also known as the standard cell library with essential analog capabilities
OpenFASOC, is an open-source initiative revolutionizing required by the generators. The process integrated PDK
semiconductor design by automating the entire flow for characterization scripts with design templates to streamline
digital and mixed-signal systems-on-chip (SoCs). It focuses aux-cell creation. The templates encapsulated the exact

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behavior of each aux-cell without PDK-specific data, while IV. RESULT AND DISCUSSION
characterization scripts extracted technology-specific
parameters to adjust template knobs. These knobs controlled Optimizing 2-stage Op-amp in Automated Analog
device type, transistor size, and other circuit variables within Circuit Design
the template. The resulting aux-cell generation included
essential files like timing libraries, netlists, and layouts, An automated analog circuit design was evaluated through
facilitating traditional synthesis and automatic place and the implementation and testing of a 2-stage operational
route (APR) seamlessly. amplifier using Xschem, as shown in Figure 9. The schematic
The analog generators in OpenFASoC used models to depicts the operational amplifier circuit that includes a
predict performance and determine design parameters for differential stage, which comprises a differential pair and a
optimized block designs that met user-defined requirements. current mirror. Additionally, it features an amplification stage
These models relied on parameterized templates containing to enhance the gain.
aux-cells as their foundation. Each generator utilized a
distinct model, crafted through a combination of design space
exploration, machine learning, and mathematical formulas.
This modeling process was executed once per PDK, and the
outcomes were stored in respective model files, as illustrated
in Figure 7.

Figure 9: Schematic of two stage Operational Amplifier created by using

Figure 7: Process Setup and Modelling in OpenFASoC Xschem.

Block designs and composite designs in OpenFASoC were When users selected Option 1 in the Two Stage Op-amp
stored in the IP-XACT format for comprehensive description. window, they encountered an “Update Target Specifications”
Additional analog data, simulation, and verification dialog box as shown in Figure 10. This feature allowed users
information were recorded in an expanded format [22]. The to input specific parameters aligned with their requirements.
SoC integrator began by assembling the composite design It provided the capability to customize and fine-tune target
and converting it into a structural Verilog format compatible specifications for their circuit designs directly. By enabling
with computer simulation programs. The final validated GDS direct user input, the interface supported real-time
file was generated by processing this structural Verilog adjustments, empowering users to refine their design criteria
through the embedded tool flow, incorporating all necessary precisely. This interactive capability enhanced the design
artifacts from the database. This standardized flow was process by providing flexibility for iterative refinement based
employed universally by all generators (aux-cell, model, and on evolving needs and preferences.
analog) across the framework.
In OpenFASoC, the initial stage involved feeding the
Process Design Kit (PDK), cells, models, and block
specifications into the Verilog generation module, as depicted
in Figure 8. This module generated a synthesizable Verilog
description of the block that met input specifications, utilizing
models for accuracy. It also produced guidance data in a
vendor-independent format. The macro generation phase Figure 10: Update Target Specification for two stage op-amp.
created macros suitable for integration into larger SoC
designs, forwarding the Verilog and guidance data to a digital Selecting Option 2 in the Two Stage Op-amp window
flow. Here, processes like synthesis, automatic place and triggered the automatic execution of the script
route (APR), design rule check (DRC), and layout versus correct_inputs.py, which specifically involved navigating to
schematic (LVS) verification were executed. Finally, macro the circuit netlist directory for training purposes. Moreover, if
validation ensured comprehensive verification and reporting Option 3 was chosen in the Two Stage Op-amp window, it
of the created block, including parasitic extraction, SPICE prompted the user to input the desired number of design
simulations, and requirement checks across the entire circuit. specifications. By confirming with a click on OK, the system
updated the specifications accordingly, as shown in Figure
11. Upon completion, a message indicated whether the
generation process was successful or not.

Figure 8: SoC Generator in OpenFASoC.

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Figure 13: RL agent’s performance monitoring in Tensorboard.

Figure 11: Generating Design Specifications for Two Stage Op-amp. For instance, Figure 14 (a) shows the mean reward over
total environment steps. At the beginning of the training
Option 4 in the Two Stage Op-amp window allowed users process, the agent required a significant number of steps to
to choose between two execution modes: “Faster Execution” complete circuit optimization. As training progressed, the
and “Complete Execution”, as depicted in Figure 12. Opting agent learned to optimize circuit parameters more efficiently,
for Faster Execution triggered a streamlined process with 50 requiring fewer steps. As a result, the average episode length
training iterations, providing a quick overview of AutoCKT’s decreased. This decreasing trend indicated that the agent was
functionality. This mode automatically ended after the improving in its decision-making capabilities for optimizing
specified iterations, offering a brief insight into the process. circuit parameters and was meeting the design specifications
In contrast, selecting “Complete Execution” initiated a faster than through the manual steps. Figure 14(b) shows the
comprehensive cycle that continued until the system achieved maximum reward obtained by the reinforcement learning
the desired specifications and parameters. This mode enabled agent during the training. Initially, the reward increased as the
a thorough exploration of AutoCKT’s capabilities, allowing agent learned how to optimize the circuit parameters to meet
users to monitor its performance until achieving the desired target design specifications. Subsequently, the reward
outcome. stabilized, indicating that the agent has become proficient in
the optimization process.

(a) Ray episode length mean (b) Ray episode reward maximum
Figure 14: Performance Analysis of AutoCkt

3-stage Ring Oscillator in Automated Layout Design

Figure 12: Design parameters, specs and ideal specs achieved during Selecting Xschem directed users to a new window with
training. additional sub-options such as browsing and selecting
schematics or SPICE files to review their contents and
Figure 12 also shows the sequence of parameters obtained analyze pre- and post-layout simulation results through
for a 2-stage op-amp after optimization. The optimized graphical representations. Each sub-option was tailored to
parameters revealed that the width of the PMOS transistor improve users’ ability to visualize and analyze various
“mp1” was 12, the width of the NMOS transistor “mn1” was aspects of their circuit designs.
17, and then the width of the PMOS transistor “mp3” was 75. When users selected the option to view the schematic in the
Furthermore, additional optimized parameters included Xschem window, the GUI displayed an image of the
widths of 22 for transistor “mn3”, 13 for transistor “mn4”), schematic, specifically a ring oscillator, as shown in Figure
45 for transistor “mn5”, and 50 for the compensation 15. From the schematic, users were able to view the generated
capacitor “cc” within the circuit. netlist for the ring oscillator. This visual representation
The GUI’s performance was evaluated based on the speed offered users a detailed overview of the circuit's design,
of integrated processes and the efficiency of design making it easier to understand and verify the components and
optimization workflows. Users found that the GUI facilitated connections. Direct visualization of the schematic enabled
rapid execution of essential tasks, such as updating target users to swiftly identify potential issues or areas for
specifications and running validation scripts. The option to improvement in their design, thereby improving the overall
choose between faster and complete IPython execution design and simulation workflow.
provided flexibility, with the faster option delivering quick
results within a limited number of iterations. Automated
processes, including generating design specifications and
running validation scripts, streamlined the circuit design
process. Integration of external tools like Tensorboard
enabled users to monitor the RL agent’s performance in
ongoing simulations and track optimization progress using
saved checkpoint files, as shown in Figure 13.

Figure 15: Viewing 3-stage Ring Oscillator’s schematic and generated

netlist in Xschem

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Following this, when users chose to view folders or files

in the Xschem window, the GUI presented a file browsing
interface, as depicted in Figure 16. This interface allowed
users to navigate their directory structure and select files.
Upon double-clicking a file, its contents were displayed in a
text widget, enabling users to review detailed information
such as circuit design specifics and simulation parameters.
This feature ensured users could verify that the correct files
were selected and that their content aligned with design
expectations. It enhanced file management and verification
efficiency, thereby improving the overall effectiveness of the Figure 18: ALIGN options
design and simulation process.
Similarly, choosing the ALIGN option opened a dedicated
window for layout generation and visualization tasks, as
depicted in Figure 18. This interface introduced ALIGN’s
capabilities, enabling users to execute the tool, select a
circuit, generate layout designs using Docker, and view the
resulting .gds and .lef files directly. These files were
accessible for detailed examination in KLayout without
Figure 16: File Browsing Interface requiring manual intervention. The interface also provided
options to reset file selections and close the window,
Figure 17 (a) demonstrated how selecting the option to enhancing workflow efficiency and user experience.
view pre-layout results in the Xschem window presented Upon clicking “Choose Circuit” in Figure 19, a directory
simulation outcomes before generating the physical layout. selection window opened, showing the contents of
Users were able to visualize waveform images and other ‘/home/jvya/mygui/ALIGN-public/ALIGN-pdk
graphical data illustrating the circuit’s behavior under test /sky130/examples’. Users could select a specific circuit
conditions, such as the transient response or frequency folder from this interface, which updated the path displayed
characteristics of a ring oscillator. These results validated the at the bottom of the window. This selected path was then
circuit’s functionality in its schematic form, ensuring it met dynamically integrated for running the ALIGN tool with the
specifications before proceeding to layout, thereby saving correct directory.
time. Subsequently, option 4 allowed users to view post-
layout results, as shown in Figure 17 (b), indicating
simulation outcomes after completing the physical layout.
Like pre-layout results, these visuals provided critical
insights into the circuit's performance in its final form,
verifying compliance with design specifications. They also
helped identify issues caused by layout parasitic or other
layout-related factors that may not have been evident during
pre-layout simulation. Moreover, the consistency in periodic
simulation output between pre-layout and post-layout
analyses further supported the robustness and reliability of Figure 19: Choosing Circuit in ALIGN
the oscillator design.
One of the significant enhancements in this GUI
application was its seamless integration with ALIGN. Users
were able to execute ALIGN processes with a single click,
facilitating the generation of GDS and LEF files, as shown in
Figure 20. This integration simplified the process of running
ALIGN and offered immediate access to the generated files,
which could be viewed and analyzed using KLayout. This
streamlined workflow supported efficient GDS layout
generation and inspection, essential for advanced circuit
design and analysis.

(a) Pre-layout simulation (b) Post-Layout simulation

Figure 17: Pre-and Post layout simulation results

Figure 20: Running ALIGN

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Users could select multiple generated GDS and LEF files

conveniently using checkboxes in the GUI, as illustrated in
Figure 21, and open them simultaneously in KLayout for
visualization by clicking the “Open with KLayout” button.
This streamlined process allowed users to efficiently inspect
and compare layout designs, ensuring accuracy and
consistency across different versions. With all selected files Figure 23: Upload GDS and LEF Files of both Ring Oscillator and
ADC
readily available in KLayout, users were able to perform
thorough analyses, verify connections, and validate their
designs with ease. By integrating file selection and Selecting the “View Verilog Files” option opened a new
visualization within the GUI, this feature enhanced usability, window where users could browse and view the contents of
accelerated the design validation process, and contributed to Verilog files, as illustrated in Figure 24. This window
improved productivity and design quality. featured a listbox that listed all Verilog files located in the
Overall, this GUI seamlessly integrated file browsing, specified directory. Upon selecting a file from the list, its
content display, and visualization features, simplifying the contents were displayed in a text widget within the same
management and validation of design and simulation window. This functionality enabled users to efficiently
processes. The capability to open generated files directly in inspect and review their Verilog code, facilitating debugging
KLayout, as depicted in Figure 22, enhanced usability by and validation processes.
providing a comprehensive environment for analog circuit
design and layout generation. This streamlined workflow
enabled a thorough review of design schematics and
simulation results, promoting efficiency and productivity
throughout the design process.

Figure 24: View Verilog Files Window

The View Logs option opened a window where users could

view the logs generated during the design and simulation
processes. By selecting a log file from the list box, users could
read its content in the text widget, as shown in Figure 25. This
feature was crucial for diagnosing issues and ensuring that the
design process proceeds smoothly.

Figure 21: View Generated Files

Figure 25: View logs Window

When users selected the “View Results” option, as

depicted in Figure 26, they accessed comprehensive results
generated by OpenFASOC, covering the synthesis to routing
Figure 22: Ring Oscillator’s GDS Layout and Lef View in KLayout stages. Similar to the “View Logs” feature, this window
enabled users to browse, select, and examine result files
Integrating 3-Stage Ring Oscillator and 1-Bit ADC using effortlessly. It offered valuable insights into the outcomes of
Automated Mixed Signal IC Design. design and simulation processes, aiding in the validation of
design effectiveness and correctness. This streamlined
When users select Option 1 Upload Files, a new window capability ensured a smooth and efficient user experience by
opened, providing functionalities to upload various types of facilitating a thorough review of all relevant files.
files essential for the OpenFASOC workflow. First,
uploading GDS and LEF files allowed users to select and
upload respective GDS and LEF files to the specified
directory, facilitating the design process as shown in Figure
23. These LEF files were essential for layout and design rules.
Additionally, the Upload Verilog Files feature provided a
straightforward method for uploading Verilog files, which are
critical for circuit design in OpenFASOC flow. This feature
simplified file management within the OpenFASOC Figure 26: View Results Window
environment, ensuring that all necessary files were readily
accessible for further processing.

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The Option 5: View Generated GDS File feature enabled Sockalingam, Ser Lee Loh, Yan Chiew Wong; draft
users to view the final GDS layout using KLayout, as manuscript preparation: Jiveya Sri Sockalingam, Ranjit
illustrated in Figure 27. Upon selection, the application Singh Sarban Singh, T. Joseph Sahaya Anand. All authors
automatically opened the specified GDS file in KLayout, had reviewed the findings and approved the final manuscript.
providing a detailed visualization of the circuit layout. This
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