Product Description

Sirenza Microdevices’ SHF-0589 is a high performance AlGaAs/

SHF-0589
GaAs Heterostructure FET (HFET) housed in a low-cost sur-
face-mount plastic package. The HFET technology improves
0.05-3 GHz, 2 Watt
breakdown voltage while minimizing Schottky leakage current GaAs HFET

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resulting in higher PAE and improved linearity.

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Output power at 1dB compression is +33.4 dBm when biased
for Class AB operation at 7V,345mA at 1.96 GHz. The +46.5 Product Features
dBm third order intercept makes it ideal for high dynamic range, • High Linearity Performance at 1.96 GHz

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high intercept point requirements. It is well suited for use in
+33.4 dBm P1dB

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both analog and digital wireless communication
infrastructure and subscriber equipment including 3G, cellular, +46.5 dBm OIP3

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PCS, fixed wireless, and pager systems. +26 dBm IS-95 Channel Power
+11.5 dB Gain
Typical Gain Performance (7V,345mA)
• +23.7 dBm W-CDMA Channel Power

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40
35 • High Drain Efficiency (>50% at P1dB)

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Gain, Gmax (dB)

30

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25 Applications
20 Gmax
15 • Analog and Digital Wireless Systems

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10 Gain FO • 3G, Cellular, PCS
5 • Fixed Wireless, Pager Systems
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0 1 2 3 4 5 6
Frequency (GHz)
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Test C onditions, 25C

Test
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Symbol D evice C haracteristics VDS=7V, IDQ=345mA U nits Min Typ Max

Frequency
(unless otherw ise noted)
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0.90 GHz dB - 22.9 -

Gmax Maxi mum Avai lable Gai n ZS=ZS*, ZL=ZL* 1.96 GHz dB - 17.4 -
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2.14 GHz dB - 16.6 -

S 21 Inserti on Gai n [1]

ZS=ZL= 50 Ohms 0.90 GHz dB 14.1 15.7 17.3
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Gai n Power Gai n [2]

Appli cati on C i rcui t 1.96 GHz dB m 10.3 11.5 12.7
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OIP3 Output Thi rd Order Intercept Poi nt [2]

Appli cati on C i rcui t 1.96 GHz dB m 44 46.5 -

P 1dB Output 1dB C ompressi on Poi nt [2]

Appli cati on C i rcui t 1.96 GHz dB m 31.9 33.4 -
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PCHAN IS-95 C hannel Power (-45dBc AC PR) Appli cati on C i rcui t 1.96 GHz dB m - 26.2 -

NF Noi se Fi gure [2]

Appli cati on C i rcui t 1.96 GHz dB - 3.7 -
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IDSS Saturated D rai n C urrent VDS= VDSP, VGS= 0V mA 816 1176 1536
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gm Tranconductance VDS= VDSP, VGS= -0.25V mS 576 792 1008

VP Pi nch-Off Voltage [1]

VDS= 2.0V, IDS= 2.4mA V -3.0 -1.9 -1.0
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BVGS Gate-Source Breakdown Voltage [1]

IGS= 4.8mA, drai n open V - -17 -15
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BVGD Gate-D rai n Breakdown Voltage [1]

IGD= 4.8mA, VGS= -5.0V V - -22 -17

Rth Thermal Resi stance juncti on-to-lead o

C /W - 23 -
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V DS Operati ng Voltage [3]

drai n-source V - - 8.0
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IDQ Operati ng C urrent [3]

drai n-source, qui escent mA - - 480

PDISS Power D i ssi pati on [3]

C - - 2.4
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[1] 100% tested - Insertion gain tested using a 50 ohm contact board (no matching circuitry) during final production test.
[2] Sample tested - Samples pulled from each wafer/package lot. Sample test specifications are based on statistical data from sample test measurements. The test fixture is
an engineering application circuit board. The application circuit was designed for the optimum combination of linearity, P1dB, and VSWR.
[3] Maximum recommended power dissipation is specified to maintain TJ<140C at TL=85C. VDS * IDQ< 2.4W is recommended for continuous reliable operation.
The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or omissions.
Sirenza Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the user’s own risk. Prices and specifications are
subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. Sirenza Microdevices does not
authorize or warrant any Sirenza Microdevices product for use in life-support devices and/or systems.
Copyright 2002 Sirenza Microdevices, Inc. All worldwide rights reserved.
522 Almanor Ave., Sunnyvale, CA 94085 Phone: (800) SMI-MMIC http://www.sirenza.com
1 EDS-101242 Rev F
 SHF-0589 2 Watt HFET
Absolute Maximum Ratings
Parameter Symbol Value Unit
MTTF is inversely proportional to the device junction
temperature. For junction temperature and MTTF

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Drain Current IDS 640 mA
considerations the bias condition should also Forward Gate Current IGSF 4.8 mA

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satisfy the following expression:
Reverse Gate Current IGSR 4.8 mA

PDC < (TJ - TL) / RTH Drain-to-Source Voltage VDS 9.0 V

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Gate-to-Source Voltage VGS <-5 or >0 V

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where:
RF Input Power PIN 800 mW
PDC = IDS * VDS (W)

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TJ = Junction Temperature (°C) Operating Lead Temperature TL See Graph °C
TL = Lead Temperature (pin 4) (°C) Storage Temperature Range Tstor -40 to +165 °C

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RTH = Thermal Resistance (°C/W) Power Dissipation PDISS See Graph W

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Channel Temperature TJ 165 °C

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Operation of this device beyond any one of these limits may cause
permanent damage. For reliable continuous operation, the device
voltage and current must not exceed the maximum operating values
specified in the table on page 1.

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Power Derating Curve
FO
Total Dissipated Power (W)

5.0
4.5
4.0
3.5
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3.0
2.5
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2.0
1.5
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Operational (Tj<140C)
1.0
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0.5 ABS MAX (Tj<165C)

0.0
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-40 -10 20 50 80 110 140 170

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Lead Temperature (C)

Design Considerations and Trade-offs
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1. The SHF-0x89 is a depletion mode FET and requires a negative gate voltage. Normal pinchoff variation from part-to-
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part precludes the use of a fixed gate voltage for all devices. Active bias circuitry or manual gate bias alignment is
recommended to maintain acceptable performance (RF and thermal).
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2. Active bias circuitry is strongly recommended for class A operation (backoff >6dB).
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3. For large signal operation (< 6dB backoff) class AB operation is required to maximize the FET’s performance.
Passive gate bias circuitry is generally required to achieve pure class AB performance. This is generally accomplished
using a voltage divider with temperature compensation. Per item 1 above the gate voltage should be aligned for each
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device to eliminate the effects of pinchoff process variation.

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4. Choose the operating voltage based on the amount of backoff. For large signal operation the drain-source voltage
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should be increased to 8V to maximize P1dB. For small signal operation OIP3 may be improved by reducing the voltage
and increasing the current. The recommended application circuit should be re-optimized if the recommended 7V bias
condition is not used. Make sure the quiescent bias condition does not exceed the recommended power dissipation
limit (shown on page 1).

522 Almanor Ave., Sunnyvale, CA 94085 Phone: (800) SMI-MMIC http://www.sirenza.com

2 EDS-101242 Rev F
 SHF-0589 2 Watt HFET
De-embedded S-Parameters (ZS=ZL=50 Ohms, VDS=7V, IDS=345mA, 25°C)
Gain & Isolation S11, S22 vs Frequency

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40 0 1.0

35 -5

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0.5 6 GHz 2.0
Gain, Gmax (dB)

30 -10 5 GHz

Isolation (dB)
4 GHz
25 -15 6 GHz

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Gmax 3 GHz 5 GHz
20 -20
0.2 5.0

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4 GHz

15 Isolation -25 2 GHz

3 GHz

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2 GHz
10 -30 0.0 0.2
1 GHz
0.5
50 MHz
1.0 2.0 5.0
inf

5 -35

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Gain S22
0 -40 1 GHz
50 MHz
0.2 5.0

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0 1 2 3 4 5 6

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Frequency (GHz)
S11
0.5 2.0

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1.0
FO
Note: S-parameters are de-embedded to the device leads with Z S=Z L=50Ω. The data represents typical performace of the device.
De-embedded s-parameters can be downloaded from our website (www.sirenza.com).

DC-IV Curves
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1.2
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1
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0.8
IDS (A)

VGS = -2.0 to 0V, 0.2V steps

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0.6
T=25° C
0.4
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0.2
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0
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0 2 4 6 8 10
VDS (V)
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Typical Performance - Engineering Application Circuits

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-45dBc -55dBc
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Freq VDS IDQ P 1d B C h an n el C h an n el OIP3[6] Gain S11 S 22 NF

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(MHz ) (V) (mA) (dBm) P o w er P o w er (dBm) (dB) (dB) (dB) (dB)

(dBm) (dBm)
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900 7 345 32.0 25.7 [4]

23.2 [4]
45.0 16.3 -20 -10 3.6
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1960 7 345 33.4 26.2 [4]

23.2 [4]
46.5 11.5 -15 -12 3.7
2140 7 345 32.7 23.7 [5]
20.5 [5]
46.4 11.1 -15 -12 4.4
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[4] IS-95 CDMA Channel Power (9 Fwd Channels, 885kHz offset, 30kHz Adj Chan BW)
[5] W-CDMA Channel Power (64 DPCH, 5MHz offset, 3.84MHz Adj Chan BW)
[6] POUT= +15dBm per tone, 1MHz tone spacing

522 Almanor Ave., Sunnyvale, CA 94085 Phone: (800) SMI-MMIC http://www.sirenza.com

3 EDS-101242 Rev F
 SHF-0589 2 Watt HFET
Caution: ESD sensitive
Appropriate precautions in handling, packaging and Part Number Ordering Information
testing devices must be observed.

Pin Description Part Number Reel Siz e Devices/Reel

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Pin # Function Description SHF-0589 7" 1000

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1 Gate RF Input

2 Source Connection to ground. Use via holes to reduce lead Part Symbolization
inductance. Place vias as close to ground leads as possible.
The part will be symbolized with the “H5”

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3 Drain RF Output

4 Source Same as Pin 2

designator and a dot signifying pin 1 on the top

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surface of the package.
Mounting and Thermal Considerations

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It is very important that adequate heat sinking be
Package Dimensions

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provided to minimize the device junction .161
temperature. The following items should be
implemented to maximize MTTF and RF

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3
performance. .016

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H5
.177 .068 .019 .118

2
1. Multiple solder-filled vias are required directly
below the ground tab (pin 4). [CRITICAL]

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2. Incorporate a large ground pad area with

1
multiple plated-through vias around pin 4 of the FO .096 .041
device. [CRITICAL]
3. Use two point board seating to lower the thermal
resistance between the PCB and mounting plate.
Place machine screws as close to the ground tab
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.059 .015
(pin 4) as possible. [CRITICAL]
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4. Use 2 ounce copper to improve the PCB’s heat

spreading capability. [CRITICAL]
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5. Thermal transfer paste should be used between DIMENSIONS ARE IN INCHES

the PCB and the mounting plate to improve heat
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spreading capability. [RECOMMENDED]

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Recommended Mounting Configuration for

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Optimum RF and Thermal Performance

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Ground Plane
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Plated Thru
C

Holes
(0.020" DIA)
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SHF-0x89
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T
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Machine
Screws
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522 Almanor Ave., Sunnyvale, CA 94085 Phone: (800) SMI-MMIC http://www.sirenza.com

4 EDS-101242 Rev F