SN54HC32, SN74HC32

QUADRUPLE 2-INPUT POSITIVE-OR GATES

SCLS200D – DECEMBER 1982 – REVISED AUGUST 2003

D Wide Operating Voltage Range of 2 V to 6 V D Typical tpd = 8 ns

D Outputs Can Drive Up To 10 LSTTL Loads D ±4-mA Output Drive at 5 V
D Low Power Consumption, 20-µA Max ICC D Low Input Current of 1 µA Max

SN54HC32 . . . J OR W PACKAGE SN54HC32 . . . FK PACKAGE

SN74HC32 . . . D, DB, N, NS, OR PW PACKAGE (TOP VIEW)
(TOP VIEW)

VCC
NC
1B
1A

4B
1A 1 14 VCC
3 2 1 20 19
1B 2 13 4B 1Y 4 18 4A
1Y 3 12 4A NC 5 17 NC
2A 4 11 4Y 2A 6 16 4Y
2B 5 10 3B NC 7 15 NC
2Y 6 9 3A 2B 8 14 3B
GND 7 8 3Y 9 10 11 12 13

2Y

3Y
3A
NC
GND
NC – No internal connection

description/ordering information
The ’HC32 devices contain four independent 2-input OR gates. They perform the Boolean function
Y +
A • B or Y + )
A B in positive logic.

ORDERING INFORMATION
ORDERABLE TOP-SIDE
TA PACKAGE†
PART NUMBER MARKING
PDIP – N Tube of 25 SN74HC32N SN74HC32N
Tube of 50 SN74HC32D
SOIC – D Reel of 2500 SN74HC32DR HC32
Reel of 250 SN74HC32DT
–40°C
–40 C to 85
85°C
C SOP – NS Reel of 2000 SN74HC32NSR HC32
SSOP – DB Reel of 2000 SN74HC32DBR HC32
Tube of 90 SN74HC32PW
TSSOP – PW Reel of 2000 SN74HC32PWR HC32
Reel of 250 SN74HC32PWT
CDIP – J Tube of 25 SNJ54HC32J SNJ54HC32J
–55°C 125°C
–55 C to 125 C CFP – W Tube of 150 SNJ54HC32W SNJ54HC32W
LCCC – FK Tube of 55 SNJ54HC32FK
SNJ54HC32FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Copyright  2003, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments On products compliant to MIL-PRF-38535, all parameters are tested
standard warranty. Production processing does not necessarily include unless otherwise noted. On all other products, production
testing of all parameters. processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

SN54HC32, SN74HC32
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SCLS200D – DECEMBER 1982 – REVISED AUGUST 2003

FUNCTION TABLE
(each gate)
INPUTS OUTPUT
A B Y
H X H
X H H
L L L

logic diagram (positive logic)

A
Y
B

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions (see Note 3)

SN54HC32 SN74HC32
UNIT
MIN NOM MAX MIN NOM MAX
VCC Supply voltage 2 5 6 2 5 6 V
VCC = 2 V 1.5 1.5
VIH High-level input voltage VCC = 4.5 V 3.15 3.15 V
VCC = 6 V 4.2 4.2
VCC = 2 V 0.5 0.5
VIL Low-level input voltage VCC = 4.5 V 1.35 1.35 V
VCC = 6 V 1.8 1.8
VI Input voltage 0 VCC 0 VCC V
VO Output voltage 0 VCC 0 VCC V
VCC = 2 V 1000 1000
∆t/∆v
t/ v Input transition rise/fall time VCC = 4.5 V 500 500 ns
VCC = 6 V 400 400
TA Operating free-air temperature –55 125 –40 85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 SN54HC32, SN74HC32
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SCLS200D – DECEMBER 1982 – REVISED AUGUST 2003

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
TA = 25°C SN54HC32 SN74HC32
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP MAX MIN MAX MIN MAX
2V 1.9 1.998 1.9 1.9
IOH = –20 µA
A 4.5 V 4.4 4.499 4.4 4.4
VOH VI = VIH or VIL 6V 5.9 5.999 5.9 5.9 V
IOH = –4 mA 4.5 V 3.98 4.3 3.7 3.84
IOH = –5.2 mA 6V 5.48 5.8 5.2 5.34
2V 0.002 0.1 0.1 0.1
IOL = 20 µA
A 4.5 V 0.001 0.1 0.1 0.1
VOL VI = VIH or VIL 6V 0.001 0.1 0.1 0.1 V
IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33
IOL = 5.2 mA 6V 0.15 0.26 0.4 0.33
II VI = VCC or 0 6V ±0.1 ±100 ±1000 ±1000 nA
ICC VI = VCC or 0, IO = 0 6V 2 40 20 µA
Ci 2 V to 6 V 3 10 10 10 pF

switching characteristics over recommended operating free-air temperature range, CL = 50 pF

(unless otherwise noted) (see Figure 1)
FROM TO TA = 25°C SN54HC32 SN74HC32
PARAMETER VCC UNIT
(INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX
2V 50 100 150 125
tpd A or B Y 4.5 V 10 20 30 25 ns
6V 8 17 25 21
2V 38 75 110 95
tt Y 4.5 V 8 15 22 19 ns
6V 6 13 19 16

operating characteristics, TA = 25°C

PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance per gate No load 20 pF

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

SN54HC32, SN74HC32
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SCLS200D – DECEMBER 1982 – REVISED AUGUST 2003

PARAMETER MEASUREMENT INFORMATION

From Output Test VCC

Under Test Point Input 50% 50%
0V
CL = 50 pF
(see Note A) tPLH tPHL

In-Phase VOH
90% 90%
Output 50% 50%
LOAD CIRCUIT 10% 10%
VOL
tr tf
tPHL tPLH
VCC
90% 90% VOH
Input 50% 50% Out-of-Phase 90% 90%
10% 10% 0 V 50% 50%
Output 10% 10%
VOL
tr tf tf tr

VOLTAGE WAVEFORM VOLTAGE WAVEFORMS

INPUT RISE AND FALL TIMES PROPAGATION DELAY AND OUTPUT TRANSITION TIMES

NOTES: A. CL includes probe and test-fixture capacitance.

B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. The outputs are measured one at a time with one input transition per measurement.
D. tPLH and tPHL are the same as tpd.

Figure 1. Load Circuit and Voltage Waveforms

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 PACKAGE OPTION ADDENDUM

www.ti.com 18-Oct-2013

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

5962-8404501VCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8404501VC
A
SNV54HC32J
5962-8404501VDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8404501VD
A
SNV54HC32W
84045012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 84045012A
SNJ54HC
32FK
8404501CA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 8404501CA
SNJ54HC32J
8404501DA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 8404501DA
SNJ54HC32W
JM38510/65201B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/
65201B2A
JM38510/65201BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
65201BCA
JM38510/65201BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
65201BDA
M38510/65201B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/
65201B2A
M38510/65201BCA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
65201BCA
M38510/65201BDA ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510/
65201BDA
SN54HC32J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 SN54HC32J

SN74HC32D ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC32

& no Sb/Br)
SN74HC32DBLE OBSOLETE SSOP DB 14 TBD Call TI Call TI -40 to 85
SN74HC32DBR ACTIVE SSOP DB 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC32
& no Sb/Br)
SN74HC32DBRE4 ACTIVE SSOP DB 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC32
& no Sb/Br)

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 18-Oct-2013

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

SN74HC32DBRG4 ACTIVE SSOP DB 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC32
& no Sb/Br)
SN74HC32DE4 ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC32
& no Sb/Br)
SN74HC32DG4 ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC32
& no Sb/Br)
SN74HC32DR ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 HC32
& no Sb/Br)
SN74HC32DRE4 ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC32
& no Sb/Br)
SN74HC32DRG4 ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC32
& no Sb/Br)
SN74HC32DT ACTIVE SOIC D 14 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC32
& no Sb/Br)
SN74HC32DTE4 ACTIVE SOIC D 14 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC32
& no Sb/Br)
SN74HC32DTG4 ACTIVE SOIC D 14 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC32
& no Sb/Br)
SN74HC32N ACTIVE PDIP N 14 25 Pb-Free CU NIPDAU N / A for Pkg Type -40 to 85 SN74HC32N
(RoHS)
SN74HC32N3 OBSOLETE PDIP N 14 TBD Call TI Call TI -40 to 85
SN74HC32NE4 ACTIVE PDIP N 14 25 Pb-Free CU NIPDAU N / A for Pkg Type -40 to 85 SN74HC32N
(RoHS)
SN74HC32NSR ACTIVE SO NS 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC32
& no Sb/Br)
SN74HC32NSRE4 ACTIVE SO NS 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC32
& no Sb/Br)
SN74HC32NSRG4 ACTIVE SO NS 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC32
& no Sb/Br)
SN74HC32PW ACTIVE TSSOP PW 14 90 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC32
& no Sb/Br)
SN74HC32PWE4 ACTIVE TSSOP PW 14 90 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC32
& no Sb/Br)
SN74HC32PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC32
& no Sb/Br)
SN74HC32PWLE OBSOLETE TSSOP PW 14 TBD Call TI Call TI -40 to 85

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

www.ti.com 18-Oct-2013

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

SN74HC32PWR ACTIVE TSSOP PW 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC32
& no Sb/Br)
SN74HC32PWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC32
& no Sb/Br)
SN74HC32PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC32
& no Sb/Br)
SN74HC32PWT ACTIVE TSSOP PW 14 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC32
& no Sb/Br)
SN74HC32PWTE4 ACTIVE TSSOP PW 14 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC32
& no Sb/Br)
SN74HC32PWTG4 ACTIVE TSSOP PW 14 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 HC32
& no Sb/Br)
SNJ54HC32FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 84045012A
SNJ54HC
32FK
SNJ54HC32J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 8404501CA
SNJ54HC32J
SNJ54HC32W ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type -55 to 125 8404501DA
SNJ54HC32W

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Addendum-Page 3
 PACKAGE OPTION ADDENDUM

www.ti.com 18-Oct-2013

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN54HC32, SN54HC32-SP, SN74HC32 :

• Catalog: SN74HC32, SN54HC32

• Military: SN54HC32
• Space: SN54HC32-SP

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Military - QML certified for Military and Defense Applications
• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application

Addendum-Page 4
 PACKAGE MATERIALS INFORMATION

www.ti.com 11-Oct-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74HC32DBR SSOP DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
SN74HC32DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC32DR SOIC D 14 2500 330.0 16.8 6.5 9.5 2.3 8.0 16.0 Q1
SN74HC32DRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC32DRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC32DT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC32PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74HC32PWT TSSOP PW 14 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 11-Oct-2013

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74HC32DBR SSOP DB 14 2000 367.0 367.0 38.0
SN74HC32DR SOIC D 14 2500 333.2 345.9 28.6
SN74HC32DR SOIC D 14 2500 364.0 364.0 27.0
SN74HC32DRG4 SOIC D 14 2500 333.2 345.9 28.6
SN74HC32DRG4 SOIC D 14 2500 367.0 367.0 38.0
SN74HC32DT SOIC D 14 250 367.0 367.0 38.0
SN74HC32PWR TSSOP PW 14 2000 367.0 367.0 35.0
SN74HC32PWT TSSOP PW 14 250 367.0 367.0 35.0

Pack Materials-Page 2
 MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38
0,65 0,15 M
0,22
28 15

0,25
0,09
5,60 8,20
5,00 7,40

Gage Plane

1 14 0,25

A 0°–ā8° 0,95
0,55

Seating Plane

2,00 MAX 0,05 MIN 0,10

PINS **
14 16 20 24 28 30 38
DIM

A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90

A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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