SN54HCT02, SN74HCT02

QUADRUPLE 2-INPUT POSITIVE-NOR GATES

SCLS065E – NOVEMBER 1988 – REVISED JULY 2003

D Operating Voltage Range of 4.5 V to 5.5 V D Typical tpd = 10 ns

D Outputs Can Drive Up To 10 LSTTL Loads D ±4-mA Output Drive at 5 V
D Low Power Consumption, 20-µA Max ICC D Low Input Current of 1 µA Max
D Inputs Are TTL-Voltage Compatible
SN54HCT02 . . . J OR W PACKAGE SN54HCT02 . . . FK PACKAGE
SN74HCT02 . . . D, DB, N, NS, OR PW PACKAGE (TOP VIEW)
(TOP VIEW)

VCC
NC
1A
1Y

4Y
1Y 1 14 VCC
3 2 1 20 19
1A 2 13 4Y 1B 4 18 4B
1B 3 12 4B NC 5 17 NC
2Y 4 11 4A 2Y 6 16 4A
2A 5 10 3Y NC 7 15 NC
2B 6 9 3B 2A 8 14 3Y
GND 7 8 3A 9 10 11 12 13

2B

3A
3B
NC
GND
NC – No internal connection

description/ordering information
These devices contain four independent 2-input NOR gates. They perform the Boolean function Y = A • B or
Y = A + B in positive logic.

ORDERING INFORMATION
ORDERABLE TOP-SIDE
TA PACKAGE†
PART NUMBER MARKING
PDIP – N Tube of 25 SN74HCT02N SN74HCT02N
Tube of 50 SN74HCT02D
SOIC – D Reel of 2500 SN74HCT02DR HCT02
Reel of 250 SN74HCT02DT
–40°C
–40 C to 85
85°C
C SOP – NS Reel of 2000 SN74HCT02NSR HCT02
SSOP – DB Reel of 2000 SN74HCT02DBR HT02
Tube of 90 SN74HCT02PW
TSSOP – PW Reel of 2000 SN74HCT02PWR HT02
Reel of 250 SN74HCT02PWT
CDIP – J Tube of 25 SNJ54HCT02J SNJ54HCT02J
–55°C 125°C
–55 C to 125 C CFP – W Tube of 150 SNJ54HCT02W SNJ54HCT02W
LCCC – FK Tube of 55 SNJ54HCT02FK
SNJ54HCT02FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

UNLESS OTHERWISE NOTED this document contains PRODUCTION Copyright  2003, Texas Instruments Incorporated
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

SN54HCT02, SN74HCT02
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SCLS065E – NOVEMBER 1988 – REVISED JULY 2003

FUNCTION TABLE
(each gate)
INPUTS OUTPUT
A B Y
H X L
X H L
L L H

logic diagram, each gate (positive logic)

A
Y
B

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions (see Note 3)

SN54HCT02 SN74HCT02
UNIT
MIN NOM MAX MIN NOM MAX
VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V
VIH High-level input voltage VCC = 4.5 V to 5.5 V 2 2 V
VIL Low-level input voltage VCC = 4.5 V to 5.5 V 0.8 0.8 V
VI Input voltage 0 VCC 0 VCC V
VO Output voltage 0 VCC 0 VCC V
∆t/∆v Input transition rise/fall time 500 500 ns
TA Operating free-air temperature –55 125 –40 85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 SN54HCT02, SN74HCT02
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SCLS065E – NOVEMBER 1988 – REVISED JULY 2003

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
TA = 25°C SN54HCT02 SN74HCT02
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP MAX MIN MAX MIN MAX
IOH = –20 µA 4.4 4.499 4.4 4.4
VOH VI = VIH or VIL 4.5 V V
IOH = –4 mA 3.98 4.3 3.7 3.84
IOL = 20 µA 0.001 0.1 0.1 0.1
VOL VI = VIH or VIL 4.5 V V
IOL = 4 mA 0.17 0.26 0.4 0.33
II VI = VCC or 0 5.5 V ±0.1 ±100 ±1000 ±1000 nA
ICC VI = VCC or 0, IO = 0 5.5 V 2 40 20 µA
One input at 0.5 V or 2.4 V,
∆ICC† 5.5 V 1.4 2.4 3 2.9 mA
Other inputs at 0 or VCC
4.5 V
Ci 3 10 10 10 pF
to 5.5 V
† This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.

switching characteristics over recommended operating free-air temperature range, CL = 50 pF

(unless otherwise noted) (see Figure 1)
FROM TO TA = 25°C SN54HCT02 SN74HCT02
PARAMETER VCC UNIT
(INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX
4.5 V 11 20 30 25
tpd A or B Y ns
5.5 V 10 18 27 22
4.5 V 9 15 22 19
tt Y ns
5.5 V 8 14 20 17

operating characteristics, TA = 25°C

PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance No load 20 pF

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

SN54HCT02, SN74HCT02
QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SCLS065E – NOVEMBER 1988 – REVISED JULY 2003

PARAMETER MEASUREMENT INFORMATION

From Output Test 3V

Input 1.3 V 1.3 V
Under Test Point
0V
CL = 50 pF
(see Note A) tPLH tPHL

In-Phase VOH
90% 90%
Output 1.3 V 1.3 V
LOAD CIRCUIT 10% 10% V
OL
tr tf
tPHL tPLH
3V VOH
Input 1.3 V 2.7 V 2.7 V 1.3 V 90% 90%
Out-of-Phase 1.3 V 1.3 V
0.3 V 0.3 V 0 V 10% 10%
Output VOL
tr tf tf tr

VOLTAGE WAVEFORM VOLTAGE WAVEFORMS

INPUT RISE AND FALL TIMES PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES

NOTES: A. CL includes probe and test-fixture capacitance.

B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. The outputs are measured one at a time with one input transition per measurement.
D. tPLH and tPHL are the same as tpd.

Figure 1. Load Circuit and Voltage Waveforms

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN74HCT02D ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HCT02

SN74HCT02DG4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HCT02

SN74HCT02DR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HCT02

SN74HCT02DRG4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HCT02

SN74HCT02DT ACTIVE SOIC D 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HCT02

SN74HCT02N ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74HCT02N

SN74HCT02NE4 ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74HCT02N

SN74HCT02NSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HCT02

SN74HCT02PW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HT02

SN74HCT02PWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HT02

SN74HCT02PWT ACTIVE TSSOP PW 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HT02

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 30-Dec-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74HCT02DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HCT02DT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HCT02NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN74HCT02PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74HCT02PWT TSSOP PW 14 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 30-Dec-2020

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74HCT02DR SOIC D 14 2500 853.0 449.0 35.0
SN74HCT02DT SOIC D 14 250 210.0 185.0 35.0
SN74HCT02NSR SO NS 14 2000 853.0 449.0 35.0
SN74HCT02PWR TSSOP PW 14 2000 853.0 449.0 35.0
SN74HCT02PWT TSSOP PW 14 250 853.0 449.0 35.0

Pack Materials-Page 2
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