The document discusses various techniques for sequential circuit design including C2MOS logic, pipelining, NORA-CMOS, doubled C2MOS latches, and true single phase clock (TSPC) logic. It describes how C2MOS logic avoids race conditions through independent pull-up and pull-down networks controlled by non-overlapping clock phases. Pipelining uses registers to separate combinational logic stages and can be implemented using C2MOS. NORA-CMOS combines dynamic logic and C2MOS registers to allow fast pipelined datapaths.
The document discusses various techniques for sequential circuit design including C2MOS logic, pipelining, NORA-CMOS, doubled C2MOS latches, and true single phase clock (TSPC) logic. It describes how C2MOS logic avoids race conditions through independent pull-up and pull-down networks controlled by non-overlapping clock phases. Pipelining uses registers to separate combinational logic stages and can be implemented using C2MOS. NORA-CMOS combines dynamic logic and C2MOS registers to allow fast pipelined datapaths.
The document discusses various techniques for sequential circuit design including C2MOS logic, pipelining, NORA-CMOS, doubled C2MOS latches, and true single phase clock (TSPC) logic. It describes how C2MOS logic avoids race conditions through independent pull-up and pull-down networks controlled by non-overlapping clock phases. Pipelining uses registers to separate combinational logic stages and can be implemented using C2MOS. NORA-CMOS combines dynamic logic and C2MOS registers to allow fast pipelined datapaths.
The document discusses various techniques for sequential circuit design including C2MOS logic, pipelining, NORA-CMOS, doubled C2MOS latches, and true single phase clock (TSPC) logic. It describes how C2MOS logic avoids race conditions through independent pull-up and pull-down networks controlled by non-overlapping clock phases. Pipelining uses registers to separate combinational logic stages and can be implemented using C2MOS. NORA-CMOS combines dynamic logic and C2MOS registers to allow fast pipelined datapaths.
C2MOS Logic Goal: Make circuit operation independent of phase overlap No need to worry about careful design of clock phases, clock inversions, etc Really ingenious design!
Flip-flop insensitive to clock overlap
Modes of operation: V DD M2 V DD M6
1) Evaluate ( = 1) -section acts as inverter -section is in high-impedance (hold) mode 2) Roles reversed for = 0 Q C L2
M4 C L1
M8
M3
M7
M1
M5
-section
-section C2 MOS master -slave negative edge-triggered D flip-flop
Insensitive to clock overlap as long as clock rise and fall times are small 3
C2MOS avoids Race Conditions
Signal propagation requires pull-up followed by pull-down, or vice versa VDD M2 VDD M6 V DD VD D
M2
M6
X D 1 M3 1 M7
M4
M8
M1
M5
M1
M5
(1 - 1 ) o ver la p
(0 - 0 ) o v e rlap
Only pull-down networks are enabled
Only pull-up networks are enabled
C2MOS avoids Race Conditions
Caution: If clock has low rise/fall times, then both pMOS and nMOS may conduct Typically need rise/fall time at most five times clock propagation delay
Pipelining Register Register
Common in high-speed designs Combinational logic (stages) separated by registers Alternating clock phases typically used Race may occur if clock phases overlap 6
Pipelined Logic using C2MOS
V DD V DD VDD
In
C2
C3
Ou t
C1
NORA CMOS (NO RAce CMOS)
W h at a re t h e c o n s t ra in ts o n F a n d G ? 7
Example
VDD
V DD
V DD
N u m b e r o f a s ta tic in v e rs io n s s h o u ld b e e v e n
NORA CMOS Targets implementation of fast, pipelined datapaths using dynamic logic Combines C2MOS pipeline registers and np-CMOS dynamic logic functional blocks Combinational logic can be a mixture of static and dynamic logic Latch and logic (feeding latch) are clocked in such a way that both are simultaneously in either evaluation or hold (precharge) Block in evaluation during =1 is a -module, inverse is a -module -modules and -modules alternate
NORA CMOS Modules
VDD V DD VDD
In 1 In 2 In 3 PD N
P UN
L at ch VDD VDD
Out
V DD
Co mbina tio nal lo g ic
V DD In 4
-module
In 1 In 2 In 3 P DN
In 4
O ut
-module
10
NORA Logic Modules
Operation M odes
-block Logic Latch Hold Evaluate
-block Logic Latch
= 0 = 1
Precharge Evaluate
Evaluate Evaluate Precharge Hold
11
Doubled C2MOS Latches
Single clock (no inverse clock is sufficient) Requires redesign of C2MOS latch
12
Doubled C2MOS Latches
V DD V DD V DD VDD
Q D
D o ub le d n -C 2 M O S la tc h
D o ub led p -C M O S la tc h
= 1, latch in transparent, evaluate mode = 0, latch in hold mode, only pull -up network active Dual-stage approach: no races 13
Doubled C2MOS Latches: Advantages
No even-inversion constraints between two latches, or between latch and a dynamic block Dynamic and static circuits can be mixed freely Logic functions can be included in the n-C2MOS or pC2MOS latches, or placed between them Disadvantage: More transistors per latch (six, instead of four)
14
TSPC - True Single Phase Clock Logic
V DD
VDD
VDD
VDD
PUN In
PD N
S ta tic L og ic
Out
Inc luding log ic into the la tc h
Ins e rt ing lo gic be twe e n la tc he s
15
Simplified TSPC Latch (SplitOutput)
V DD V DD V DD V DD
Q D
-latch
Reduced area Voltage degradation at A
-latch
16
Master-Slave Flip-flops VDD D X (a) Positive edge-triggered D flip-flop VDD D V DD VDD V DD Y V DD D D V DD D V DD V DD
(b) Negative edge-triggered D flip-flop
(c) Positive edge-triggered D flip-flop using split-output latches
17
Two-Phase Clock Generator
in 1
Considerations: Drive: added buffers Non-overlap: Two phases inverted with respect to each other Minimum skew Implement with NAND gates? 18
Registers with Load/Enable Inputs
Ld
1 C
2 C Q
Ld
Multiplexed input
19
Registers with Load/Enable Inputs
2 D C C Q
Enable
Ld
Gated clock
Clock enable circuit
Gnd
20
10
Comments on Transmission Gates
(Common Misconceptions) Enable Enabled
Transmission gate used here as an AND gate
Clock enable circuit
Gnd
21
Comments on Transmission Gates
(Common Misconceptions) b C F = ab Transmission gate is not an AND gate
b Transmission gate network does not a C b a C F = a+b serve as an OR gate
