Lec 11 Sequential Logic Circuits

CMOS Digital Integrated Circuits
Lec 11
Sequential CMOS Logic
Circuits
Sequential Logic
In
Combinational
Logic
circuit
Out
Memory
Sequential
The output is determined by
Current inputs
Previous inputs
Output = f(In, Previous In)
The regenerative behavior of sequential circuits is due to either a
direct or an indirect feedback connection between the output and
input
2
Critical Components of Sequential Circuits

Basic Regenerative Circuits
Categories of Basic Regenerative Circuits

1. Bistable Circuits: Two stable states or operation modes, each of
them can be attained under certain input and output conditions. The
most widely used and the most important class which is used for
the basic latch, flip-flop circuits, registers, and memory elements.
2. Monostable Circuits: One stable state or operation mode
3. Astable Circuits: No stable operating point or state which the
circuit can preserve for a certain time period. The output oscillates
without settling into a stable operating mode.
Sequential
Circuits
Bistable
3
Monostable
Astable
Behavior of Bistable Elements (1/7)

Two Identical Cross-Coupled Inverter Circuit
Voltage Transfer Curves

The output voltage of inverter (1) is equal to the input voltage of
inverter (2), and the output voltage of inverter (2) is equal to the
input voltage of inverter (1).
A and B are stable points: If the circuit is initially operating at one
of them, it will preserve this state. The gain is smaller than unity.
A
Vi2=Vo1
stable
unstable
C
stable
Vi1
Vo1
Vi1=Vo2
Energy
Vo2
Vi2
C is an unstable point: The voltage gains of both inverters are

larger than unity. A small voltage perturbation at this operating
point will be amplified the operating point will move to one
of the stable operating points, A or B.
Energy Levels:
The potential energy is at its minimum at A and B, since the
voltage gains of both inverters are equal to zero.
The potential energy is at its maximum at C, since the voltage
gains of both inverters are maximum. (all four transistors are in
saturation modes)
VDD
VDD
VOH
Vi2
Vo1
Vi1
Vo2
Vth
VOL
Vo1
Vo2
t

Analysis of the Output Voltages
Let the initially operating point is at vo1=vo2=Vth, and assume that
the gate capacitance (Cg) of each inverter is much larger than the
drain capacitance (Cd).
ig1
id1
The drain current of each inverter is
1
vg1
equal to the gate current of the other
inverter.
id2
ig2
2
ig1 = id2 = gmvg2
vg2
(Eq. A)
ig2 = id1 = gmvg1
gm is the small-signal transconductance of the inverter.
The gate voltages can be expressed by gate charges, q1 and q2
vg1 = q1 / Cg
(Eq. B)
vg2 = q2 / Cg
Also the small-signal gate currents can be expressed as
ig1 = Cg dvg1 /dt
(Eq. C)
ig2 = Cg dvg2 /dt
6

Combine Eq. A and C, we have
g mv g2 = C
g m v g1 = C
ig1
vg1
dv g1
dt
dv g2
dt
id1
1
id2
ig2
2
vg2
Replace the gate voltages by Eq. B, we obtain

gm
Cg
gm
Cg
q2 =
dq1
dt
q1 =
dq 2
dt
The above equations can be simplified to

2
gm
d q1 g m
1
C g d q1
Cg
=
=
;
=
q1 =
q
q
1
2
2
2 1 0
dt
dt
g
gm
0
Cg
m
Cg
2

Therefore,
q (0 ) 0 q 1 ( 0 )
q 1 (t ) = 1
2
'
q (0 ) + 0 q 1 ( 0 )
+ 1
2
'
t
0
where q1(0) = Cgvg1(0)

Replace the gate charge of both inverters with the corresponding
output voltages variables, we have
0 for t >> 0
'
'
v o 2 (0 ) 0 v o 2 ( 0 ) t
v o 2 (0 ) + 0 v o 2 ( 0 ) t
+
v o 2 (t ) =
e
e
2
2
'
'
v o 1 (0 ) 0 v o 1 ( 0 ) t
v o 1 (0 ) + 0 v o 1 ( 0 ) t
v o 1 (t ) =
e +
e
2
2
0 for t >> 0
For large values of t, the above equations can be approximated as
t
1
'
vo1 (t ) (vo1 (0 ) + 0 vo1 (0) )e 0
2
t
1
'
vo 2 (t ) (vo 2 (0 ) + 0 vo 2 (0) )e 0
2
0

Depending on the polarity of the initial small perturbations dvo1(0)
and dvo1(0), the vo1 and vo2 will diverge from their initial values of
Vth to either VOL and VOH.
The polarity of dvo1 must always be opposite to that of dvo2,
because of the charge-conservation principle. Therefore, vo1 and
vo2 always diverge into opposite directions.
vo2
VOH
unstable
Vth
VOL
vo1
VOL
Vth
VOH
Phase-plane Representation
vo1: Vth VOH or VOL
vo2: Vth VOL or VOH
9

As a bistable circuit settles from unstable operating point to its
stable point, a signal travels around 2 INV loop n times.
vo1
vo1(t)/vo1(0)et/0
Loop
vo2
If during interval t = T, the signal travels around the loop n times

AneT/0
VOH
loop 1
A1
loop 2
A2
loop n
vo1
Vth
An
et/0
vo2
VOL
10
Naming Conventions

A latch is level sensitive

A register is edge-triggered
There are many different naming conventions
For instance, many books call edge-triggered elements flip-flops
Digital Integrated Circuits2nd

11
Latch versus Register

Latch
Register
stores data when
clock rises
stores data when

clock is low
D Q
D Q
Clk
Clk
Clk
Clk
Q
12
Latches
Positive Latch
In
Negative Latch
Out
In
CLK
clk
clk
In
In
Out
Out
Out
follows In
Out
CLK
Out
stable
Out
stable
Out
follows In

13
SR Latch Circuit
The two cross-coupled inverters can perform a simple memory
function of holding its state. However, the two-inverter circuit
alone has no provision for allowing its state to be changed
externally from one stable operating point to other.
In order to allow such a change of state, we need to add simple
switches which can be used to force or trigger the circuit from one
operating point to the other.
Q
S
R
NOR-based
SR Latch
Q
Q
Q
Schematic Diagram of SR Latch
14
SR Latch Circuit (Cont.)

The below circuit shows the simple CMOS SR latch which
consists of two triggering inputs, S (set) and R (reset).
The SR Latch consists of two CMOS NOR2 gates. One of the
input terminals of each NOR gate is used to cross-couple to the
output of the other NOR gate. The second input enables triggering
of the circuit.
VDD
VDD
M6
M5
M8
M7
Q
S
15
M1
basic cross
coupled inverter
Q
M2
M3
M4
SR Latch Circuit
Truth Table
Set: S=1, R=0 Qn+1=1, Qn+1=0. The SR latch will be set

regardless of its previous state.
R
Reset: S=0, R=1 Qn+1=0, Qn+1=1. The SR latch will be reset
regardless of its previous state.
Hold: S=0, R=0 Qn+1=Qn, Qn+1=Qn. The previous states will be
held.
Not Allow: S=1, R=1 Qn+1=0, Qn+1=0
active high
S
0
1
0
1
R
0
0
1
1
Qn+1
Qn
1
0
0
Qn+1
Qn
0
1
0
Operation
Hold
Set
Reset
Not Allowed
Truth Table of NOR-based (active high inputs) SR latch

16
SR Latch Circuit
Operation Modes of the Transistors
S
Qn+1 Qn+1
Operation
NMOS
VOH VOL VOH
PMOS
1
M7, M8 on; M5, M6 off
2
2
3
1
VOL VOH VOL1 VOH
M1
1, M2 off; M3, M4 on
1
2 1
M3
7, M8 off; M5, M6 on
VOL VOL VOH
VOL M1, M4 off; M2, on
M6, M8 on; M7, on
VOL VOL VOL
VOH M1, M4 off; M3, on
M6, M8 on; M5, on
VDD
M6
M5
VDD
M8
M1
basic cross
coupled inverter
M7
17
VOL M1, M2 on; M3, M4 off
Q
M2
M3
M4
R
SR Latch Circuit
Transient Analysis
For transient analysis, we have to consider an event which results
in a state change, reset set, or set reset
In either case, we note that both of the output nodes undergo
simultaneous voltage transitions. One is from logic-low to logichigh, and the other is from logic-high to logic-low.
The exact transient analysis need to solve two coupled differential
equations.
For simplicity, we can assume that the two events take place in
sequence rather than simultaneously. (overestimation)
Switching Time Calculation

The total lumped capacitance at each output node can be
approximated as
CQ = Cgb,2+Cgb,5+Cdb,3+Cdb,4+Cdb,7+Csb,7+Cdb,8
CQ = Cgb,3+Cgb,7+Cdb,1+Cdb,2+Cdb,5+Csb,5+Cdb,6
18
SR Latch Circuit
Transient Analysis (Cont.)
Assuming that the latch is initially reset and that a set operation is
being performed, the rise time associated with node Q can be
estimated as
rise,Q(SR-latch) = fall,Q(NOR2) + riseQ(NOR2)
VDD
VDD
Q M2 on
Q
S
0 1
19
M1
Q
M2
CQ
CQ
M3
M4
rise,Q(NOR2)
R
1 0
SR Latch Circuit
NAND-based (active low signals)
VDD
VDD
basic cross
coupled inverter
active low
20
Qn+1
Qn+1
Operation
Not Allowed
Set
Reset
Qn
Qn
Hold
Clocked Latch and Flip-Flop Circuits

The previous SR latch circuits are asynchronous sequential
circuits.
The synchronization can be introduced through clock CK, which
the outputs will respond to the input levels only during the active
period of a clock pulse.
Clocked SR Latch
SR Latch
CK
Q
R
When CK=0, S, R have no influence of Q, Q Hold
Set State: CK=1, S=1, R=0 Qn+1=1, Qn+1=0
Reset State: CK=1, S=0, R=1 Qn+1=0, Qn+1=1
Not Allowed: CK=1, S=1, R=1
21
Active High
AOI-based Implementation of
Clocked NOR-based SR Latch
The AOI-based implementation need a very small transistor count,
compared with the circuit consisting of two AND2 and two NOR2 gates
NOR-based: 20 transistors
NOR SR
AOI-based: 12 transistors
VDD
CK
VDD
Q
S
M1
CK
22
M1
Latch
Q
M2
M3
M4
R
CK
Operation of Clocked SR Latch

Operation
CK
CK
Qn+1
Qn+1
Hold
Qn
Qn
Set
Reset
Not Allow
Glitch
S
R
Q
Glitch Free Q
When Glitch ON S (or R) occurs during CK = 1, Q is set (or reset).
Level Sensitive: When CK = 1, any changes in S, R will effect Q.
23
Clocked NAND-based SR Latch

S
CK
Q
R
When CK = 1, S and R have no influence of Q and Q Hold
Operation
24
CK
Qn+1
Qn+1
Hold
Qn
Qn
Set
Reset
Not Allow
0
OAI-based Implementation of Clocked NAND-based SR Latch

The OAI-based implementation need a very small transistor count,
compared with the circuit consisting of two OR2 and two NAND2 gates
VDD
Q
M2
M1
CK
NAND
SR Latch
VDD
Q
M4
M3
CK
Synchronous operation
Level sensitive (any changes in S and R as CK=1 will be reflected onto outputs)
Not allowed input sequence
25
Clocked JK Latch
NAND SR
J
CK = 0 hold
CK = 1 active
CK
26
K
No not-allowed
input combination
CK = 1
Qn
Qn
Qn+1 Qn+1 Operation
0
0
0
0
0
1
1
0
1
1
1
1
0
1
1
0
Hold
Hold
0
0
1
1
0
1
1
0
1
1
1
0
0
0
1
1
Reset
Reset
1
1
0
0
0
1
1
0
0
1
1
1
1
1
0
0
Set
Set
1
1
1
1
0
1
1
0
0
1
1
0
1
0
0
1
Toggle
Toggle
OSC
NOR-based Clocked JK Latch (1/2)
NAND SR
S
J
CK
K
Q
R
Q
NOR SR
S
J
CK
K
S
J
Q
R
CK
K
27
NOR-based Clocked JK Latch (2/2)
The AOI-based implementation has a very small transistor count,
and a more compact circuit compared to all-NAND realization.
VDD
VDD
CK
J
CK
28
CK
JK Toggle Switch
J =K=1
J=1
CK
K=1
CK
JK
Latch
Q
Q
T1
Q
Iff JKP > T1 (awkward to implement)
Output Q changes only once per clock period
No not allowed input
Timing issues
Level sensitive
29
Master-Slave Flip-Flop
J
CK
K
S NAND
R
SR
Qm
Qm
S NAND
R
SR
Qs
Qs
CK
Two cascaded latches operating on opposite clock phases insures
that the flip-flop is never transparent; i.e., a change occurring in
the primary inputs is never reflected directly to the outputs.
Eliminates oscillations when J = K =1.
Still level sensitive.
Number of transistors:
NAND-based: 36
AOI-based: 28
30
D-Latch
D-latch is obtained by modifying the clocked NOR-based SR latch
circuit. The circuit has a single input D which is connected to S
input, and D is also inverted and connected to R input.
The applications of D-latch are primarily for temporary storage of
data or as a delay element.
SR Latch
D
Q
CK
Q
If CK=1 Qn+1 = D
If CK=0 Qn+1 = Qn
31
D-Latch (Cont.)
D-latch is a mux-based latch which can be represented as
1
D
0
CK
Q=CKQ+CKIn
Negative latch
(transparent when CK= 0)
32
Q
D
1
CK
Q=CKQ+CKIn
Positive latch
(transparent when CK= 1)
D-Latch
Implementation with Transmission Gates
Transmission gate D-latch: Use switch-like properties of
transmission gates
CK
CK
D
CK
Operation: For CK = 1, Qn+1=D and Qn+1=D. A bit is loaded. For

CK = 0, Qn+1=Qn and Qn+1=Qn. Thus, a bit is stored.
What about changes in D relative to changes in CK?
Setup time and Hold time relative to CK: 10
Device counts for TG-based reduced from AOI/OAI
AOI-based: 14
TG-based: 8 (plus 2 to invert clock)
33
D-Latch
Implementation with Three-State
Q
CK = 1
Q
CK = 0
Similar to the TG-based implementation, except as if connection

between n and pFETs in a driving inverter and input side of a driven
transmission gate is served. Require addition of inverter at input first.
VDD
VDD
VDD
CK
CK
D
CK
34
CK
D-Latch
Implementation with Three-State (Cont.)
The first three-state inverter acts as the input switch. Accept the input
signal when CK is high, the second three-state inverter is at its high
impedance state, and Q = D.
The first three-state inverter is inactive when the CK goes low, and the
second three-state inverter completes the two-inverter loop, which
preserves its state (Qn+1 = Qn)
VDD
VDD
VDD
CK
CK
D
CK
35
CK
D-Latch
Setup Time and Hold Time
CK
tsetup
thold
Q
tclock-to-Q
Tsetup: time before the negative-CK edge the D-input has to be stable
The setup time is the delay between the data input of the register and the
storage element. As the data takes a finite time to travel to the storage
point, the clock cannot be changed until the correct data value appears.
Thold: time after the negative-CK edge D-input has to remain stable
The hold time relates to the delay between the clock input to the register
and the storage element. That is, the data has to be held for this period
while the clock travels to the point of storage.
Tclock-to-Q: Delay from the negative-CK edge to new value of Q output
36
Edge Triggered Master-Slave Operation

Negative D-Latch
Q
CK
Q
CK=0
D
CK
Q
CK=1
D
D
CK
Positive D-Latch
CK
Q
Q
CK=1
D
CK
D
CK
37
Q
CK=0
D
Positive Edge Triggered Master-Slave Flip-Flop

negative level-sensitive
Master
positive level-sensitive
Slave
CK
CK
Qm
CK
Qm
Qs
Qs
CK
D
CK
CK
For CK=0
Qm
For CK=1
D
38
Qm
1. CK=0: Master Qm tracks current D;

Slave Qs=previous D sample
Qs
2. CK=01: Master stores Qm = D(new D
sample).
3. CK=1:Master passes Qm = D to Slave
output Qs
Qs 4. CK=10: Slave locks in new D, and
Master Qm begins tracking D.
DFF Transient Response
39
DFF Transient Response with Setup Time Violation
40
D Flip-Flop
Clock Skew Issues
In a TG or three-state implemented flip-flop, if CK and CK changes
are skewed (misaligned) enough, then a change in Master can
immediately propagate into Slave violating the master-slave (edgetriggered) concept.
If global or shared drivers used, can use the following to reduce skew:
CK
CK IN
0
CK
1
Adjust devices sizes to match

inverter delay
For the global case, skew can also arise due to interconnect delay.
41
Non-Bistable Sequential
Schmitt Trigger
The Schmitt trigger has an inverter-like voltage transfer
characteristic, but with two different threshold voltages for
increasing and decreasing input signals.
In
Out
VTC with hysteresis

Restores signal slopes
(positive feedback)
42
VOH
Vout
VOL
VM
VM+
Vin
Schmitt Trigger Application

Noise Suppression
Vin
Vout
VM+
VM
t0
Vout
VOH
t0 + tp
VOL
VM
43
VM+
Vin

Schmitt Trigger
The Circuit(1)
VDD
M2
Vin
M4
Vout
M1
M3
Moves switching threshold

of the first inverter
44
Schmitt Trigger Simulated VTC

kM1/(kM2+kM4)
2.5
2.5
2.0
2.0
VM1
Vout
1.5
Vout
1.5
1.0
1.0
VM2
k= 1
k=3
0.5
0.0
0.0
0.5
0.5
1.0
1.5
Vin (V)
2.0
2.5
Voltage-transfer characteristics with hysteresis.
(kM1+kM3)/kM2
45
k= 2
k=4
0.0
0.0
0.5
1.0
1.5
Vin (V)
2.0
2.5
The effect of varying the ratio of the

PMOS deviceM4. The width is k* 0.5 m m.

Schmitt Trigger
The Circuit(2)
VDD
M4
M6
M3
In
Out
M2
M5
VDD
M1

46
Multivibrator Circuits
R
S
Bistable Multivibrator
flip-flop, Schmitt Trigger
T
Monostable Multivibrator
one-shot
Astable Multivibrator
oscillator
47
Transition-Triggered Monostable
In
DELAY
td
Out
td

48
Astable Multivibrators (Oscillators)
N-1
Ring Oscillator
3.0
2.5
V1 V3 V5
Volts
2.0
1.5
1.0
0.5
0.0
20.5
0.0
0.5
1.0
1.5
time (ns)
simulated response of 5-stage oscillator

49

Lec 11 Sequential Logic Circuits

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CMOS Digital Integrated Circuits

CMOS Digital Integrated Circuits

CMOS Digital Integrated Circuits

Critical Components of Sequential Circuits

Categories of Basic Regenerative Circuits

Behavior of Bistable Elements (1/7)

Voltage Transfer Curves

CMOS Digital Integrated Circuits

Behavior of Bistable Elements (2/7)

C is an unstable point: The voltage gains of both inverters are

Behavior of Bistable Elements (3/7)

CMOS Digital Integrated Circuits

Behavior of Bistable Elements (4/7)

Replace the gate voltages by Eq. B, we obtain

The above equations can be simplified to

CMOS Digital Integrated Circuits

Behavior of Bistable Elements (5/7)

where q1(0) = Cgvg1(0)

CMOS Digital Integrated Circuits

Behavior of Bistable Elements (6/7)

CMOS Digital Integrated Circuits

Behavior of Bistable Elements (7/7)

If during interval t = T, the signal travels around the loop n times

CMOS Digital Integrated Circuits

A latch is level sensitive

Digital Integrated Circuits2nd

CMOS Digital Integrated Circuits

Latch versus Register

stores data when

CMOS Digital Integrated Circuits

Digital Integrated Circuits2nd

CMOS Digital Integrated Circuits

CMOS Digital Integrated Circuits

SR Latch Circuit (Cont.)

CMOS Digital Integrated Circuits

Set: S=1, R=0 Qn+1=1, Qn+1=0. The SR latch will be set

Truth Table of NOR-based (active high inputs) SR latch

CMOS Digital Integrated Circuits

VOH VOL VOH

M7, M8 on; M5, M6 off

VOL VOL VOH

VOL M1, M4 off; M2, on

M6, M8 on; M7, on

VOL VOL VOL

VOH M1, M4 off; M3, on

M6, M8 on; M5, on

VOL M1, M2 on; M3, M4 off

Switching Time Calculation

CMOS Digital Integrated Circuits

CMOS Digital Integrated Circuits

Clocked Latch and Flip-Flop Circuits

CMOS Digital Integrated Circuits

CMOS Digital Integrated Circuits

Operation of Clocked SR Latch

CMOS Digital Integrated Circuits

Clocked NAND-based SR Latch

OAI-based Implementation of Clocked NAND-based SR Latch