This document introduces CMOS VLSI design concepts including gate design, pass transistors, latches and flip-flops, standard cell layouts, and stick diagrams. It discusses complementary CMOS logic gates, series and parallel configurations, compound gates, multiplexers, latches, flip-flops, and race conditions. It also covers standard cell layout methodology and provides examples of an inverter and NAND gate layout as well as estimating the area of an O3AI gate using a stick diagram.
This document introduces CMOS VLSI design concepts including gate design, pass transistors, latches and flip-flops, standard cell layouts, and stick diagrams. It discusses complementary CMOS logic gates, series and parallel configurations, compound gates, multiplexers, latches, flip-flops, and race conditions. It also covers standard cell layout methodology and provides examples of an inverter and NAND gate layout as well as estimating the area of an O3AI gate using a stick diagram.
This document introduces CMOS VLSI design concepts including gate design, pass transistors, latches and flip-flops, standard cell layouts, and stick diagrams. It discusses complementary CMOS logic gates, series and parallel configurations, compound gates, multiplexers, latches, flip-flops, and race conditions. It also covers standard cell layout methodology and provides examples of an inverter and NAND gate layout as well as estimating the area of an O3AI gate using a stick diagram.
This document introduces CMOS VLSI design concepts including gate design, pass transistors, latches and flip-flops, standard cell layouts, and stick diagrams. It discusses complementary CMOS logic gates, series and parallel configurations, compound gates, multiplexers, latches, flip-flops, and race conditions. It also covers standard cell layout methodology and provides examples of an inverter and NAND gate layout as well as estimating the area of an O3AI gate using a stick diagram.
nMOS: 1 = ON pMOS: 0 = ON Series: both must be ON Parallel: either can be ON
a 0
g1 g2
(a)
(b)
a g1
g2
(c)
a g1
g2 b
CMOS VLSI Design
1 b
OFF
OFF
OFF
ON
ON
OFF
OFF
OFF
0 b
g2
a g1
0 b
(d)
OFF
ON
ON
ON
ON
ON
ON
OFF
Circuits and Layout
Slide 6
Conduction Complement Complementary CMOS gates always produce 0 or 1 Ex: NAND gate Series nMOS: Y=0 when both inputs are 1 Thus Y=1 when either input is 0 Y Requires parallel pMOS A
Rule of Conduction Complements
Pull-up network is complement of pull-down Parallel -> series, series -> parallel
CMOS VLSI Design
Circuits and Layout
Slide 7
Compound Gates Compound gates can do any inverting function Ex: Y = (A.B + C.D) A
(a)
(b)
B C
(c)
(d)
A B C D
(f)
(e)
CMOS VLSI Design
Circuits and Layout
Slide 8
Example: O3AI Y = ((A+B+C).D)
CMOS VLSI Design
Circuits and Layout
Slide 9
Example: O3AI Y = ((A+B+C).D)
A B C
D Y D
CMOS VLSI Design
Circuits andSlide Layout 10
Signal Strength Strength of signal How close it approximates ideal voltage source VDD and GND rails are strongest 1 and 0 nMOS pass strong 0 But degraded or weak 1 pMOS pass strong 1 But degraded or weak 0 Thus nMOS are best for pull-down network
CMOS VLSI Design
Circuits andSlide Layout 11
Pass Transistors Transistors can be used as switches g s
g s
CMOS VLSI Design
Circuits andSlide Layout 12
Pass Transistors Transistors can be used as switches g=0
g s
d g=1
d g=0
g s
Input g = 1 Output 0 strong 0
Input d
g=1 s
CMOS VLSI Design
g=1
g=0 g=0
degraded 1 Output degraded 0 strong 1
Circuits andSlide Layout 13
Transmission Gates Pass transistors produce degraded outputs Transmission gates pass both 0 and 1 well
CMOS VLSI Design
Circuits andSlide Layout 14
Transmission Gates Pass transistors produce degraded outputs Transmission gates pass both 0 and 1 well Input g a
b gb
b gb
g = 0, gb = 1 a b
g = 1, gb = 0 0 strong 0
g = 1, gb = 0 a b
g = 1, gb = 0 strong 1 1
g a
g b
gb
Output
b gb
CMOS VLSI Design
Circuits andSlide Layout 15
Tristates Tristate buffer produces Z when not enabled EN
EN
A EN
A EN
CMOS VLSI Design
Circuits andSlide Layout 16
Tristates Tristate buffer produces Z when not enabled EN
EN Y
A EN
A EN
CMOS VLSI Design
Circuits andSlide Layout 17
Nonrestoring Tristate Transmission gate acts as tristate buffer Only two transistors But nonrestoring Noise on A is passed on to Y
EN A
Y EN CMOS VLSI Design
Circuits andSlide Layout 18
Tristate Inverter Tristate inverter produces restored output Violates conduction complement rule Because we want a Z output A EN
EN
CMOS VLSI Design
Circuits andSlide Layout 19
Tristate Inverter Tristate inverter produces restored output Violates conduction complement rule Because we want a Z output A
A EN
EN = 0 Y = 'Z'
EN = 1 Y=A
EN
CMOS VLSI Design
Circuits andSlide Layout 20
Multiplexers 2:1 multiplexer chooses between two inputs
D1
D0
CMOS VLSI Design
D0
D1
Circuits andSlide Layout 21
Multiplexers 2:1 multiplexer chooses between two inputs
D1
D0
CMOS VLSI Design
S D0
D1
Circuits andSlide Layout 22
Gate-Level Mux Design
Y SD1 SD0 (too many transistors) How many transistors are needed?
CMOS VLSI Design
Circuits andSlide Layout 23
Gate-Level Mux Design
Y SD1 SD0 (too many transistors) How many transistors are needed? 20
D1 S D0
D1 S D0
2 4
CMOS VLSI Design
Circuits andSlide Layout 24
Transmission Gate Mux
Nonrestoring mux uses two transmission gates
CMOS VLSI Design
Circuits andSlide Layout 25
Transmission Gate Mux
Nonrestoring mux uses two transmission gates Only 4 transistors
S D0 Y
S D1 S
CMOS VLSI Design
Circuits andSlide Layout 26
Inverting Mux Inverting multiplexer Use compound AOI22 Or pair of tristate inverters Essentially the same thing Noninverting multiplexer adds an inverter D0 S
S D1
D0
D1
Y S
S Y
CMOS VLSI Design
D0
D1
Circuits andSlide Layout 27
4:1 Multiplexer 4:1 mux chooses one of 4 inputs using two selects
CMOS VLSI Design
Circuits andSlide Layout 28
4:1 Multiplexer 4:1 mux chooses one of 4 inputs using two selects Two levels of 2:1 muxes S1S0 S1S0 S1S0 S1S0 Or four tristates D0 S0 D0
D1
D2
D3
S1 D1 0 1
Y D2
D3
CMOS VLSI Design
Circuits andSlide Layout 29
D Latch When CLK = 1, latch is transparent D flows through to Q like a buffer When CLK = 0, the latch is opaque Q holds its old value independent of D a.k.a. transparent latch or level-sensitive latch
Latch
CLK
CLK D
Q Q
CMOS VLSI Design
Circuits andSlide Layout 30
D Latch Design Multiplexer chooses D or old Q CLK D
1 0
CLK
Q Q
Q CLK
CLK
CLK
CMOS VLSI Design
Circuits andSlide Layout 31
D Latch Operation Q D CLK = 1
Q D
CLK = 0
CLK D Q CMOS VLSI Design
Circuits andSlide Layout 32
D Flip-flop When CLK rises, D is copied to Q At all other times, Q holds its value a.k.a. positive edge-triggered flip-flop, master-slave flip-flop CLK
CLK D
Flop
Q Q
CMOS VLSI Design
Circuits andSlide Layout 33
D Flip-flop Design Built from master and slave D latches CLK
CLK CLK
CLK QM
Latch
Latch
CLK D
QM
D CLK
Q CLK
CLK
Q CLK
CMOS VLSI Design
CLK
Circuits andSlide Layout 34
D Flip-flop Operation D
QM
CLK = 0
QM
CLK = 1
CLK D Q
CMOS VLSI Design
Circuits andSlide Layout 35
Race Condition Back-to-back flops can malfunction from clock skew Second flip-flop fires late Sees first flip-flop change and captures its result Called hold-time failure or race condition CLK1 CLK2 Q1
Flop
Flop
CLK1
CLK2 Q2
Q1 Q2
CMOS VLSI Design
Circuits andSlide Layout 36
Nonoverlapping Clocks Nonoverlapping clocks can prevent races As long as nonoverlap exceeds clock skew We will use them in this class for safe design Industry manages skew more carefully instead 2
1 QM
D 2
Q 1
1 2
CMOS VLSI Design
Circuits andSlide Layout 37
Gate Layout Layout can be very time consuming Design gates to fit together nicely Build a library of standard cells Standard cell design methodology VDD and GND should abut (standard height) Adjacent gates should satisfy design rules nMOS at bottom and pMOS at top All gates include well and substrate contacts
CMOS VLSI Design
Circuits andSlide Layout 38
Example: Inverter
CMOS VLSI Design
Circuits andSlide Layout 39
Example: NAND3
Horizontal N-diffusion and p-diffusion strips
Vertical polysilicon gates Metal1 VDD rail at top Metal1 GND rail at bottom 32 by 40
CMOS VLSI Design
Circuits andSlide Layout 40
Stick Diagrams Stick diagrams help plan layout quickly Need not be to scale Draw with color pencils or dry-erase markers
CMOS VLSI Design
Circuits andSlide Layout 41
Wiring Tracks A wiring track is the space required for a wire 4 width, 4 spacing from neighbor = 8 pitch Transistors also consume one wiring track
CMOS VLSI Design
Circuits andSlide Layout 42
Well spacing Wells must surround transistors by 6 Implies 12 between opposite transistor flavors Leaves room for one wire track
CMOS VLSI Design
Circuits andSlide Layout 43
Area Estimation Estimate area by counting wiring tracks Multiply by 8 to express in
CMOS VLSI Design
Circuits andSlide Layout 44
Example: O3AI Sketch a stick diagram for O3AI and estimate area Y = ((A+B+C).D)
CMOS VLSI Design
Circuits andSlide Layout 45
Example: O3AI Sketch a stick diagram for O3AI and estimate area Y = ((A+B+C).D)
CMOS VLSI Design
Circuits andSlide Layout 46
Example: O3AI Sketch a stick diagram for O3AI and estimate area Y = ((A+B+C).D)
Seeking A Position in An Organization That I Can Utilize My Educational Skills and Logical Thinking For The Organization's Growth and As Well As Myself
Seeking A Position in An Organization That I Can Utilize My Educational Skills and Logical Thinking For The Organization's Growth and As Well As Myself
