The document summarizes the digital VLSI design flow from high level abstraction to physical implementation. It discusses hierarchical design partitioning, hardware description languages, logic design, circuit design, and physical design. Specifically, it provides examples to illustrate each step, from a behavioral Verilog description of a full adder, to its gate-level and transistor-level netlists, and finally a SPICE simulation. It also outlines the standard cell design methodology and design rules for layout.
The document summarizes the digital VLSI design flow from high level abstraction to physical implementation. It discusses hierarchical design partitioning, hardware description languages, logic design, circuit design, and physical design. Specifically, it provides examples to illustrate each step, from a behavioral Verilog description of a full adder, to its gate-level and transistor-level netlists, and finally a SPICE simulation. It also outlines the standard cell design methodology and design rules for layout.
The document summarizes the digital VLSI design flow from high level abstraction to physical implementation. It discusses hierarchical design partitioning, hardware description languages, logic design, circuit design, and physical design. Specifically, it provides examples to illustrate each step, from a behavioral Verilog description of a full adder, to its gate-level and transistor-level netlists, and finally a SPICE simulation. It also outlines the standard cell design methodology and design rules for layout.
The document summarizes the digital VLSI design flow from high level abstraction to physical implementation. It discusses hierarchical design partitioning, hardware description languages, logic design, circuit design, and physical design. Specifically, it provides examples to illustrate each step, from a behavioral Verilog description of a full adder, to its gate-level and transistor-level netlists, and finally a SPICE simulation. It also outlines the standard cell design methodology and design rules for layout.
Copyright:
Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online from Scribd
Download as pdf or txt
You are on page 1/ 37
Lecture 6: Design Flow
CSCE 5730 Digital CMOS VLSI Design
Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides are borrowed from various books websites authors pages and other books, websites, pages, sources for academic purpose only. The instructor does not claim any originality. y g y CSCE 5730: Digital CMOS VLSI Design
How to design modern System-on-Chip (SOC)? Many millions (soon billions!) of transistors Tens to hundreds of engineers
Approaches for larger system design:
Structured Design: Uses principles of Hierarchy, Regularity, Modularity, and Locality Design Partitioning: Design is partitioned to five interrelated tasks, such as architecture design, microarchitecture design logic design circuit design design, design, and physical design.
CSCE 5730: Digital CMOS VLSI Design
Design Partitioning : Structured Design
Hierarchy: Divide and Conquer Recursively system into modules
Regularity Reuse modules wherever possible Ex: Standard cell library
Modularity: well-formed interfaces
Allows modules to be treated as black boxes
Locality Physical and temporal
CSCE 5730: Digital CMOS VLSI Design
Hierarchical Design: Flow
mips controller standard cell library alu fulladder or2 and2 mux4 mux2 tri CSCE 5730: Digital CMOS VLSI Design
alucontrol
datapath bitslice zipper
inv4x flop ramslice
nor2 inv nand2
Design Partitioning : Y-Chart
Architecture: Users perspective, what does it do? Instruction set registers set, MIPS, x86, Alpha, PIC, ARM,
Microarchitecture: Single cycle, multicycle, pipelined, superscalar?
Datapaths, memories, random logic CSCE 5730: Digital CMOS VLSI Design
Design Partitioning : Y-Chart
Explains each domain and transformation among domains. Design process proceeds from higher to lower levels of abstractions i.e. from outer to inner rings. CSCE 5730: Digital CMOS VLSI Design
Hardware Description Language (HDL)
Hardware Description Languages Widely used in logic design Verilog Very High Speed Integrated Circuit HDL (VHDL) Very-High-Speed-Integrated-Circuit
Describe hardware using code
Document logic functions Simulate logic before building Synthesize code into gates and layout Requires a library of standard cells
CSCE 5730: Digital CMOS VLSI Design
HDLs: Verilog Example
module fulladder (input a, b, c, output s, cout); ( , , , ); sum s1(a, b, c, s); carry c1(a, b, c, cout); endmodule module carry (input a, b, c, output cout) t t t) assign cout = (a&b) | (a&c) | (b&c); endmodule
a b c a cout s fulladder cout s b c carry sum
CSCE 5730: Digital CMOS VLSI Design
Circuit Design How should logic be implemented? NANDs and NORs vs ANDs and ORs? vs. Fan-in and fan-out? How wide should transistors be?
These choices affect speed, area, power Logic synthesis makes these choices for you Good enough for many applications Hand-crafted circuits are still better
CSCE 5730: Digital CMOS VLSI Design
10
Carry Logic Example: Logic Level
assign cout = (a&b) | (a&c) | (b&c); g1 a b g2 a c g3 b c z Transistors? Gate Delays? CSCE 5730: Digital CMOS VLSI Design
x g4 y cout
11
Carry Logic Example: Transistor Level
assign cout = (a&b) | (a&c) | (b&c);
p p1 c c
p p2 p3 i3
b a a b
p p4 i4 p5 n5 i2 n4
cn
p6 cout n6
n3 i1 n1 b n2
Transistors? Gate Delays?
CSCE 5730: Digital CMOS VLSI Design
12
Carry Logic Example: Gate-level Netlist
module carry (input a, b, c, output cout) g1
wire x, y, z; and g1(x a b); g1(x, a, and g2(y, a, c); and g3(z b, c); g3(z, b or g4(cout, x, y, z); endmodule
1 2 4 a p1 b p2 b p4 i4 c p3 i3 a p5 cn c n3 i1 a n5 i2 a n1 b n2 b n4
p6 cout n6
CSCE 5730: Digital CMOS VLSI Design
14
Carry Logic Example: SPICE Netlist
.SUBCKT CARRY A B C COUT VDD GND MN1 I1 A GND GND NMOS W=1U L=0.18U AD=0.3P AS=0.5P MN2 I1 B GND GND NMOS W=1U L=0.18U AD=0.3P AS=0.5P W 1U L 0.18U AD 0.3P AS 0.5P MN3 CN C I1 GND NMOS W=1U L=0.18U AD=0.5P AS=0.5P MN4 I2 B GND GND NMOS W=1U L=0.18U AD=0.15P AS=0.5P MN5 CN A I2 GND NMOS W=1U L=0.18U AD=0.5P AS=0.15P MP1 I3 A VDD VDD PMOS W 2U L 0 18U AD 0 6P AS 1 P W=2U L=0.18U AD=0.6P AS=1 MP2 I3 B VDD VDD PMOS W=2U L=0.18U AD=0.6P AS=1P MP3 CN C I3 VDD PMOS W=2U L=0.18U AD=1P AS=1P MP4 I4 B VDD VDD PMOS W=2U L=0 18U AD=0 3P AS=1P W 2U L 0.18U AD 0.3P AS 1P MP5 CN A I4 VDD PMOS W=2U L=0.18U AD=1P AS=0.3P MN6 COUT CN GND GND NMOS W=2U L=0.18U AD=1P AS=1P MP6 COUT CN VDD VDD PMOS W=4U L=0.18U AD=2P AS=2P CI1 I1 GND 2FF CI3 I3 GND 3FF CA A GND 4FF CB B GND 4FF CC C GND 2FF CCN CN GND 4FF CCOUT COUT GND 2FF .ENDS CSCE 5730: Digital CMOS VLSI Design
15
Physical Design Floorplan : First step. Determines if design will fit in are budget budget. Standard cells : Layout is often generated using automatic place and route. Slice planning : Divide to slices. Slice plan makes S ce p a g de s ces S ce p a a es it is easy to calculate wire length, estimate area, a d e a ua e and evaluate wire congestion. e co ges o
CSCE 5730: Digital CMOS VLSI Design
16
Layout Design Rules
Interface between designer and process engineer G id li Guidelines f constructing process masks for t ti k Unit dimension: Minimum line width scalable d i rules: l bd parameter l bl design l lambda t absolute dimensions (micron rules)
CSCE 5730: Digital CMOS VLSI Design
17
Layout Design Rules
Chips are specified with set of masks Minimum dimensions of masks determine transistor size (and hence speed, cost, and power) Feature size f = distance between source and drain Set by minimum width of polysilicon
Normalize for feature size when describing design rules Express rules in terms of = f/2 e.g. = 60 nm in 120 nm process CSCE 5730: Digital CMOS VLSI Design 18
Layout Design Rules : Simplified Form
Metal and diffusion have minimum width and spacing of 4. Contacts are 2 x 2 and surrounded by 1 layer. Polysilicon width is 2 2. Polysilicon overlaps diffusion by 2 or 1 depending on situation situation. Polysilicon and contacts have spacing 3. n well surrounds PMOS transistors by 6 and n-well NMOS transistors 6. NOTE: Do not have to remember, CAD softwares handle it automatically once DRC are set depending on the foundry chosen. CSCE 5730: Digital CMOS VLSI Design
19
Layout Design Rules : Simplified Form
Conservative rules to get you started
CSCE 5730: Digital CMOS VLSI Design
20
Logic Gate Layout : Inverter
V DD 1 1 2
2 3 4
G ND
CSCE 5730: Digital CMOS VLSI Design
21
CMOS Process Layers
Layer L Well (p,n) Active Area (n+,p+) Select (p+,n+) Polysilicon Metal1 Metal2 Contact To Poly Contact To Diffusion Via Color C l Yellow Green Green Red Blue Magenta Black Black Black Representation R t ti
CSCE 5730: Digital CMOS VLSI Design
22
Layers in 0.25 m CMOS process
CSCE 5730: Digital CMOS VLSI Design
23
Intra-Layer Design Rules
Same Potential 0 or 6 10 3 Active 3 2 Select Contact or Via Hole 2 Metal2 3 CSCE 5730: Digital CMOS VLSI Design
Different Potential 9 Polysilicon 2 Metal1 M l1 2 3
4
Well
24
Transistor Layout y Tr Transistor
Polysilicon Well (n or p) Active Area (n+ or p+)
5
CSCE 5730: Digital CMOS VLSI Design
25
Vias and Contacts
2 Via 1 1 5 Metal to 1 Active Contact A i C Metal to Poly Contact 3 2 4
2 2
CSCE 5730: Digital CMOS VLSI Design
26
Select Layer y 2 3 2 1 3 3 Select
Substrate
Well
CSCE 5730: Digital CMOS VLSI Design
27
CMOS Inverter Layout
GND In VD D
Out (a) Layout
A p-substrate n+ (b) Cross-Section along A A Cross Section A-A
CSCE 5730: Digital CMOS VLSI Design
A n p+ Field Oxide
28
Layout Editor
CSCE 5730: Digital CMOS VLSI Design
29
Design Rule Checker
p y_ poly not_fet to all_diff minimum spacing = 0.14 um. p g
CSCE 5730: Digital CMOS VLSI Design
30
Sticks Diagram V DD In
3 Out Dimensionless layout entities Only topology is important Final layout generated by compaction p og a co pact o program
1 GND Stick diagram of inverter g
CSCE 5730: Digital CMOS VLSI Design
31
Logic Gate Layout
Layout can be very time consuming Design gates to fit together nicely Build a library of standard cells
St d d cell d i methodology Standard ll design th d l
VDD and GND should abut (standard height) Adjacent gates should satisfy design rules nMOS at bottom and pMOS at top All gates include well and substrate contacts
CSCE 5730: Digital CMOS VLSI Design
32
MIPS: Block Diagram
PCWriteCond PCEn PCSource MemRead MemWrite MemtoReg IRWrite[3:0] Op [5 : 0] PCWrite Outputs ALUOp IorD ALUSrcB Control ALUSrcA RegWrite RegDst 0 M x 2
Instruction [5 : 0] Instruction [31:26] Address Add Memory MemData Write data Instruction [25 : 21] Instruction [20 : 16] Instruction [15 : 0] Instruction register Instruction [7 : 0] Memory data register 0 M Instruction u x [15 : 11] 1 0 M u x 1 Read register 1 Read Read register 2 data 1 Registers Write Read register data 2 Write data A 0 M u x 1 0 1 M u 2 x 3
wiring channel: 30 tracks = 240 3500 0 1690 0 zipper 2700 x 250 datapath 2700 x 1050 (2.8 M2)
alucontrol 200 x 100 (20 k2) 10 I/O pads
10 I/O pads
5000 0
bitslice 2700 x 100 2700
3500
10 I/O pads
5000 000
CSCE 5730: Digital CMOS VLSI Design
34
MIPS : Layout
CSCE 5730: Digital CMOS VLSI Design
35
Area Estimation Need area estimates to make floorplan Compare t another bl k you already d i C to th block l d designed d Or estimate from transistor counts Budget room f l B d for large wiring tracks ii k Your mileage may vary!
CSCE 5730: Digital CMOS VLSI Design
36
Design Verification Fabrication is slow & expensive MOSIS 0 6m: $1000 3 months 0.6m: $1000, State of art: $1M, 1 month Specification = Architecture Design = Logic g Design = Circuit Design = Physical Design Function Timing Power Function Function Function
Debugging chips is very hard
Limited visibility into operation
Prove the design before building!
Logic simulation Ckt. simulation / formal verification Layout vs. schematic comparison Design & electrical rule checks g
