tps65261 1

TPS65261, TPS65261-1
SLVSCD3C – DECEMBER 2013 – REVISED MAY 2023
TPS6526x 4.5-V to 18-V Input Voltage, 3-A/2-A/2-A Output Current

Triple Synchronous Step-Down Converter
1 Features 3 Description
• Operating input supply voltage range The TPS65261, TPS65261-1 is a monolithic triple
(4.5 V to 18 V) synchronous step-down (buck) converter with 3-
• Feedback reference voltage 0.6 V±1% A/2-A/2-A output currents. A wide 4.5-V to 18-
• Maximum continuous output current 3 A/2 A/2 A V input supply voltage range encompasses the
• Adjustable clock frequency from 250 kHz to 2 MHz most intermediate bus voltages operating off 5-
• dedicated enable and soft start pins for each buck V, 9-V, 12-V or 15-V power bus. The converter,
• Automatic power-up, power-down sequence with constant frequency peak current mode, is
• Pulse Skipping Mode (PSM) at Light Load designed to simplify its application while giving
(TPS65261 only) designers options to optimize the system according
• Output voltage power-good indicator to targeted applications. The switching frequency of
• Input voltage power failure indicator the converters can be adjusted from 250 kHz to 2
• Thermal overloading protection MHz with an external resistor. The 180° out-of-phase
operation between Buck1 and Buck2, 3 (Buck2 and 3
2 Applications run in phase) minimizes the input filter requirements.
• DTV
The TPS65261, TPS65261-1 features an automatic
• Set top boxes
power sequence with connecting MODE pin to
• Home gateway and access point networks
V7V and configuring EN1/2/3 pins. The device also
• Wireless routers
features an open drain RESET signal to monitor
• Surveillance
power down.
• POS machine
At light load, the TPS65261 automatically operates
in pulse skipping mode (PSM) and the TPS65261-1
operates in force continuous current mode (FCC).
PSM mode provides high efficiency by reducing
switching losses at light loads and FCC mode reduces
noise susceptibility and RF interference.
The device features overvoltage protection,
overcurrent and short-circuit protection and over-
temperature protection. A power-good pin asserts
when any output voltages are out of regulation.
Device Information(1)
PART NUMBER MODE PACKAGE
TPS65261 PSM
RHB (VQFN, 32)
TPS65261-1 FCCM
(1) For all available packages, see the orderable addendum at

the end of the data sheet.
Vin Vout1
PVINx LX1
VIN
TPS65261
TPS65261-1
FB1
VDIV
RESET Vout2
LX2
PGOOD
ENx
FB2
MODE
SSx Vout3
ROSC LX3
AGND FB3
PGND
Typical Application
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS65261, TPS65261-1
SLVSCD3C – DECEMBER 2013 – REVISED MAY 2023 www.ti.com
Table of Contents
1 Features............................................................................1 7.4 Device Functional Modes..........................................23
2 Applications..................................................................... 1 8 Application and Implementation.................................. 25
3 Description.......................................................................1 8.1 Application Information............................................. 25
4 Revision History.............................................................. 2 8.2 Typical Application.................................................... 25
5 Pin Configuration and Functions...................................3 8.3 Power Supply Recommendations.............................35
6 Specifications.................................................................. 5 8.4 Layout....................................................................... 35
6.1 Absolute Maximum Ratings........................................ 5 9 Device and Documentation Support............................38
6.2 ESD Ratings............................................................... 5 9.1 Documentation Support............................................ 38
6.3 Recommended Operating Conditions.........................5 9.2 Receiving Notification of Documentation Updates....38
6.4 Thermal Information....................................................5 9.3 Support Resources................................................... 38
6.5 Electrical Characteristics.............................................6 9.4 Trademarks............................................................... 38
6.6 Typical Characteristics................................................ 8 9.5 Electrostatic Discharge Caution................................38
7 Detailed Description......................................................12 9.6 Glossary....................................................................38
7.1 Overview................................................................... 12 10 Mechanical, Packaging, and Orderable
7.2 Functional Block Diagram......................................... 13 Information.................................................................... 38
7.3 Feature Description...................................................13
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (May 2014) to Revision C (May 2023) Page
• Updated the numbering format for tables, figures, and cross-references throughout the document................. 1
• Removed color from images throughout the document......................................................................................1
• Changed the description of V7V pin in Table 5-1................................................................................................3
• Moved the storage temperature row in the ESD Ratings table to the Absolute Maximum Ratings table........... 5
• Renamed Handling Ratings to ESD Ratings ..................................................................................................... 5
• Changed the recommended value of capacitor from V7V pin to power ground in V7V Low Dropout Regulator
and Bootstrap................................................................................................................................................... 20
• Changed the recommended value of C5 in Figure 8-1 ....................................................................................25
Changes from Revision A (December 2013) to Revision B (May 2014) Page

• Changed all text, tables and graphics to match the new data sheet template. ................................................. 1
• Changed Figure 8-37 .......................................................................................................................................37
2 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated
Product Folder Links: TPS65261 TPS65261-1

TPS65261, TPS65261-1
www.ti.com SLVSCD3C – DECEMBER 2013 – REVISED MAY 2023
5 Pin Configuration and Functions
PGND1
PVIN1
BST1
VDIV
EN1
EN2
LX1
VIN
32 31 30 29 28 27 26 25
EN3 1 24 SS1
PGOOD 2 23 COMP1
RESET 3 22 FB1
MODE 4 21 AGND
Thermal Pad
V7V 5 20 ROSC
FB2 6 19 FB3
COMP2 7 18 COMP3
SS2 8 17 SS3
9 10 11 12 13 14 15 16
PGND2
PVIN2
PVIN3
BST3
PGND3
BST2
LX2
LX3
(There is no electric signal down bonded to thermal pad inside IC. Exposed thermal pad must be soldered to PCB for optimal thermal
performance.)
Figure 5-1. RHB Package 8-Pin VQFN (Top View)
Table 5-1. Pin Functions

PIN
DESCRIPTION
NO. NAME
Enable for buck3. Float to enable. Can use this pin to adjust the input undervoltage lockout of buck3 with a resistor
1 EN3
divider.
An open drain output, asserts low if output voltage of any buck beyond regulation range due to thermal shutdown,
2 PGOOD
overcurrent, undervoltage or ENx shut down.
3 RESET Open drain power failure output signal.
When high, an automatic power-up/power-down sequence is provided according to states of EN1, EN2 and EN3
4 MODE
pins.
5 V7V Internal LDO for gate driver and internal controller. Connect a 10-µF capacitor from the pin to power ground
6 FB2 Feedback Kelvin sensing pin for buck2 output voltage. Connect this pin to buck2 resistor divider.
Error amplifier output and Loop compensation pin for buck2. Connect a series resistor and capacitor to compensate
7 COMP2
the control loop of buck2 with peak current PWM mode.
Soft-start and tracking input for buck2. An internal 5-µA pullup current source is connected to this pin. The soft-start
8 SS2
time can be programmed by connecting a capacitor between this pin and ground.
Boot strapped supply to the high side floating gate driver in buck2. Connect a capacitor (recommend 47nF) from
9 BST2
BST2 pin to LX2 pin.
Switching node connection to the inductor and bootstrap capacitor for buck2. The voltage swing at this pin is from a
10 LX2
diode voltage below the ground up to PVIN2 voltage.
Power ground connection of buck2. Connect PGND2 pin as close as practical to the (–) terminal of VIN2 input
11 PGND2
ceramic capacitor.
Input power supply for buck2. Connect PVIN2 pin as close as practical to the (+) terminal of an input ceramic
12 PVIN2
capacitor (suggest 10µF).
13 PVIN3
Power ground connection of buck3. Connect PGND3 pin as close as practical to the (–) terminal of VIN3 input
14 PGND3
ceramic capacitor.
15 LX3
Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3

TPS65261, TPS65261-1
Table 5-1. Pin Functions (continued)

PIN
DESCRIPTION
NO. NAME
16 BST3
17 SS3
18 COMP3
20 ROSC Oscillator frequency programmable pin. Connect an external resistor to set the switching frequency.
Analog ground common to buck controllers and other analog circuits. It must be routed separately from high current
21 AGND
power grounds to the (–) terminal of bypass capacitor of input voltage VIN.
23 COMP1
24 SS1
25 BST1
26 LX1
Power ground connection of Buck1. Connect PGND1 pin as close as practical to the (–) terminal of VIN1 input
27 PGND1
ceramic capacitor.
28 PVIN1
29 VIN Buck controller power supply.
30 VDIV Input voltage threshold for power failure detection of input voltage.
31 EN1
divider.
32 EN2
divider.
There is no electric signal down bonded to thermal pad inside IC. Exposed thermal pad must be soldered to PCB for
PAD
optimal thermal performance.

TPS65261, TPS65261-1
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
PVIN1, PVIN2, PVIN3,VIN –0.3 20 V
LX1, LX2, LX3 (Maximum withstand voltage transient < 20 ns) –1.0 20 V
BST1, BST2, BST3 referenced to LX1, LX2, LX3 pins respectively –0.3 7 V
EN1, EN2, EN3, PGOOD, V7V, MODE, RESET, VDIV –0.3 7 V
FB1, FB2, FB3, COMP1 , COMP2, COMP3, SS1, SS2, SS3, ROSC –0.3 3.6 V
AGND, PGND1, PGND2, PGND3 –0.3 0.3 V
Operating junction temperature, TJ –40 125 °C
Storage temperature range, Tstg –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings

MIN MAX UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
–2000 2000
pins(1)
V(ESD) Electrostatic discharge V
Charged device model (CDM), per JEDEC specification
–500 500
JESD22-C101, all pins(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
PVIN1, PVIN2, PVIN3,VIN 4.5 18 V
LX1, LX2, LX3 (Maximum withstand voltage transient < 20 ns) –0.8 18 V
BST1, BST2, BST3 referenced to LX1, LX2, LX3 pins respectively –0.1 6.8 V
EN1, EN2, EN3, PGOOD, V7V, MODE, RESET, VDIV –0.1 6.3 V
FB1, FB2, FB3, COMP1 , COMP2, COMP3, SS1, SS2, SS3, ROSC –0.1 3 V
TA Operating junction temperature –40 85 °C
TJ Operating junction temperature –40 125 °C
6.4 Thermal Information

TPS65261
THERMAL METRIC(1) UNIT
RHB (32 PINS)
RθJA Junction-to-ambient thermal resistance 31.6
RθJC(top) Junction-to-case (top) thermal resistance 23.4
RθJB Junction-to-board thermal resistance 6.1
°C/W
ψJT Junction-to-top characterization parameter 0.2
ψJB Junction-to-board characterization parameter 6.1
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.9
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

TPS65261, TPS65261-1
6.5 Electrical Characteristics

TA = 25°C, VIN = 12 V, fSW = 600 kHz (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT SUPPLY VOLTAGE
VIN Input voltage range 4.5 18 V
VIN rising 4 4.25 4.5
V
UVLO VIN undervoltage lockout VIN falling 3.5 3.75 4
Hysteresis 500 mV
IDDSDN Shutdown supply current EN1=EN2=EN3=MODE=0 V 9.2 µA
EN1=EN2=EN3=5 V,
IDDQ_NSW 605 µA
FB1=FB2=FB3=0.8 V
IDDQ_NSW1 Input quiescent current without EN1=5V, EN2=EN3=0 V, FB1=0.8V 330 µA
buck1/2/3 switching
IDDQ_NSW2 EN2=5 V, EN1=EN3=0V, FB2=0.8 V 330 µA
IDDQ_NSW3 EN3=5V, EN1=EN2=0V, FB3=0.8V 330 µA
V7V V7V LDO output voltage V7V load current = 0 A 6 6.3 6.6 V
IOCP_V7V V7V LDO current limit 175 mA
FEEDBACK VOLTAGE REFERENCE
VCOMP = 1.2 V, TJ = 25°C 0.596 0.6 0.605 V
VFB Feedback voltage
VCOMP = 1.2 V, TJ = -40°C to 125°C 0.594 0.6 0.606 V
IOUT1 = 1.5 A, IOUT2 = 1 A, IOUT3 = 1 A
VLINEREG_BUCK Line regulation-DC 0.002 %/V
5 V < PVINx < 18 V
VLOADREG_BUCK Load regulation-DC IOUTx = (10–100%) × IOUTx_max 0.02 %/A
Buck1, Buck2, Buck3
VENXH EN1/2/3 high level input voltage 1.2 1.26 V
VENXL EN1/2/3 low level input voltage 1.1 1.15 V
IENX1 EN1/2/3 pullup current ENx = 1 V 3.6 µA
IENX2 EN1/2/3 pullup current ENx = 1.5 V 6.6 µA
IENhys Hysteresis current 3 µA
ISSX Soft start charging current 4.3 5 6 µA
TON_MIN Minimum on time 80 100 ns
Gm_EA Error amplifier trans-conductance –2 µA < ICOMPX < 2 µA 300 µS
COMP1/2/3 voltage to inductor current
Gm_PS1/2/3 ILX = 0.5 A 7.4 A/V
Gm
ILIMIT1 Buck1 peak inductor current limit 4.33 5.1 6.02 A
ILIMITSOURCE1 Buck1 low side source current limit 4.3 A
ILIMITSINK1 Buck1 low side sink current limit 1.3 A
ILIMIT2/3 Buck2/3 peak inductor current limit 2.6 3.1 3.73 A
ILIMITSOURCE2/3 Buck2/3 low side source current limit 2.7 A
ILIMITSINK2/3 Buck2/3 low side sink current limit 1 A
THiccup_wait Overcurrent wait time 256 cycles
THiccup_re Hiccup time before re-start 8192 cycles
Rdson_HS1 Buck1 High-side switch resistance VIN = 12 V 100 mΩ
Rdson_LS1 Buck1 low-side switch resistance VIN = 12 V 65 mΩ

TPS65261, TPS65261-1
6.5 Electrical Characteristics (continued)

TA = 25°C, VIN = 12 V, fSW = 600 kHz (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER GOOD, MODE, POWER SEQUENCE
FBx undervoltage Falling 92.5 %VREF
FBx undervoltage Rising 95 %VREF
Vth_PG Feedback voltage threshold
FBx overvoltage Rising 107.5 %VREF
FBx overvoltage Falling 105 %VREF
TDEGLITCH(PG)_F PGOOD falling edge deglitch time 128 cycles
TRDEGLITCH(PG)_R PGOOD rising edge deglitch time 512 cycles
IPG PGOOD pin leakage 0.05 µA
VLOW_PG PGOOD pin low voltage ISINK = 1 mA 0.4 V
VMODEH MODE high level input voltage 1.2 1.26 V
VMODEL MODE low level input voltage 1.1 1.15 V
IMODE1 MODE pullup current MODE = 1 V 3.6 µA
IMODE2 MODE pullup current MODE = 1.5 V 6.6 µA
Delay time between bucks at automatic
Tpsdelay MODE = 1.5 V 1024 cycles
power sequencing mode
POWER FAILURE DETECTOR
VDIVth VDIV threshold 1.18 1.23 1.26 V
VDIV = 1 V 1 µA
IVDIV VDIV pullup current
VDIV = 1.5 V 2 µA
IVDIVhys VDIV hysteresis current 1 µA
Tdeglitch_R RESET deglitch on the rising edge 534 cycles
Tdeglitch_F RESET deglitch on the falling edge 12 14 16 cycles
OSCILLATOR
FSW ROSC = 73.2 kΩ 560 600 640 kHz
Switching frequency
FSW_range 250 2000 kHz
THERMAL PROTECTION
TTRIP_OTP Temperature rising 160 °C
Thermal protection trip point
THYST_OTP Hysteresis 20 °C

TPS65261, TPS65261-1
6.6 Typical Characteristics

TA = 25°C, VIN = 12 V, VOUT1 = 1.2 V, VOUT2 = 3.3 V, VOUT3 = 1.8 V, fSW = 600 kHz (unless otherwise noted)
100 100
90 90
80 80
70 70
Efficiency (%)
Efficiency (%)
60 60
PSM
PSM Mode,
Mode, Vout
VO = =1.2
1.2V
V PSM
PSM Mode,
Mode, Vout
VO = =1.8
1.8V
V
50 50
PSM
PSM Mode,
Mode, VO
VO == 3.3
3.3VV PSM
PSM Mode,
Mode, Vout
VO = =3.3
3.3V
V
40 40
PSM
PSM Mode,
Mode, VO
VO == 5.0
5.0VV PSM
PSM Mode,
Mode, Vout
VO = =5.0
5.0V
V
30 30
FCC
FCC Mode,
Mode, VO
VO == 1.2
1.2VV FCC
FCC Mode,
Mode, Vout
VO = =1.8
1.8V
V
20 20
FCC
FCC Mode,
Mode, VO
VO == 3.3
3.3VV FCC
FCC Mode,
Mode, Vout
VO = =3.3
3.3V
V
10 10
FCC
FCC Mode,
Mode, VO
VO == 5.0
5.0VV FCC
FCC Mode,
Mode, Vout
VO = =5.0
5.0V
V
0 0
0.01 0.1 1 0.01 0.1 1
Output Load (A) C002 Output Load (A) C003
Figure 6-1. BUCK 1 Efficiency Figure 6-2. BUCK 2 Efficiency

1.220 3.33
1.215
3.32
1.210
Output Voltage (V)
Output Voltage (V) 3.31

1.205
1.200 3.30
1.195
3.29
1.190
VIN=5V
VIN = 5 V 3.28 VIN=5V
VIN = 5 V
1.185
VIN=12V
VIN = 12 V VIN=12V
VIN = 12 V
1.180 3.27
0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Output Load (A) C004 Output Load (A) C005
VOUT = 1.2 V VOUT = 3.3 V

Figure 6-3. BUCK1, PSM Mode, Load Regulation Figure 6-4. BUCK2, PSM Mode, Load Regulation
1.820 1.210
1.815
1.206
1.810
Output Voltage (V)
Output Voltage (V)
1.805 1.202
1.800
1.795 1.198
1.790 IOUT=0.1A
IOUT = 0.1 A
1.194
VIN=5V
VIN = 5 V IOUT=1.5A
IOUT = 1.5 A
1.785
VIN=12V
VIN = 12 V IOUT = 3.0 A
IOUT=3.0A
1.780 1.190
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 4 6 8 10 12 14 16 18
Output Load (A) C006 Input Voltage (V) C007

Figure 6-5. BUCK3, PSM Mode, Load Regulation Figure 6-6. BUCK1, PSM Mode, Line Regulation

TPS65261, TPS65261-1
6.6 Typical Characteristics (continued)

3.300 1.810
3.298 1.806
Output Voltage (V)
Output Voltage (V)

3.296 1.802
3.294 1.798
IOUT=0.1A
IOUT = 0.1 A IOUT=0.1A
IOUT = 0.1 A
3.292 1.794
IOUT=1A
IOUT = 1.0 A IOUT=1A
IOUT = 1.0 A
IOUT = 2.0 A
IOUT=2A IOUT = 2.0 A
IOUT=2A
3.290 1.790
4 6 8 10 12 14 16 18 4 6 8 10 12 14 16 18
Input Voltage (V) C008 Input Voltage (V) C009

Figure 6-7. BUCK2, PSM MODE, LINE REGULATION Figure 6-8. BUCK3, PSM Mode, Line Regulation
0.606 640
0.604 Oscillator Frequency (kHz)

Voltage Reference (V)
620
0.602
0.600 600
0.598
580
0.596
0.594
560
±50 ±25 0 25 50 75 100 125
-50 -25 0 25 50 75 100 125
Junction Temperature (ƒC) C011
Junction Temperature (°C) C012
Figure 6-9. Voltage Reference vs Temperature
ROSC = 73.2 kΩ
Figure 6-10. Oscillator Frequency vs Temperature
15 4.4
Shutdown Quiescent Current ( A)
4.2
13
En Pin On Pullup ( A)
4.0
11
3.8
3.6
9
3.4
7
3.2
5 3.0
±50 ±25 0 25 50 75 100 125 ±50 ±25 0 25 50 75 100 125
Junction Temperature (ƒC) C013 Junction Temperature (ƒC) C014
VIN = 12 V VIN = 12 V EN = 1 V
Figure 6-11. Shutdown Quiescent vs Temperature Figure 6-12. EN Pin Pull-Up Current vs Temperature, EN=1.0V

TPS65261, TPS65261-1

7.4 1.28
7.2
EN Pin Threshold Raising (V)

1.24
En Pin On Pullup ( A)
7.0
6.8
1.20
6.6
6.4
1.16
6.2
6.0 1.12
±50 ±25 0 25 50 75 100 125 ±50 ±25 0 25 50 75 100 125
VIN = 12 V EN = 1.5 V VIN = 12 V

Figure 6-13. EN Pin Pullup Current vs Temperature, EN = 1.5 V Figure 6-14. EN Pin Threshold Raising vs Temperature
1.23 5.4
EN Pin Threshold Falling (V)
1.19 Soft Start Current (mA) 5.2
1.15 5.0
1.11 4.8
1.07 4.6
±50 ±25 0 25 50 75 100 125 ±50 ±25 0 25 50 75 100 125
VIN = 12 V VIN = 12 V
Figure 6-15. EN Pin Threshold Falling vs Temperature Figure 6-16. SS Pin Charge Current vs Temperature
5.5 3.5
High Side Current Limit (A)
5.3 3.3
5.1 3.1
4.9 2.9
4.7 2.7
±50 ±25 0 25 50 75 100 125 ±50 ±25 0 25 50 75 100 125
VIN = 12 V VIN = 12 V
Figure 6-17. Buck1 High-Side Current Limit vs Temperature Figure 6-18. Buck2 High-Side Current Limit vs Temperature

TPS65261, TPS65261-1

3.5 1.25
VDIV Pin Threshold (V)

3.3 1.24
3.1 1.23
2.9 1.22
2.7 1.21
±50 ±25 0 25 50 75 100 125 ±50 ±25 0 25 50 75 100 125
VIN = 12 V Figure 6-20. VDIV Pin Threshold vs Temperature
Figure 6-19. Buck3 High-Side Current Limit vs Temperature

TPS65261, TPS65261-1
7 Detailed Description
7.1 Overview
The TPS65261, TPS65261-1 is a monolithic triple synchronous step-down (buck) converter with 3A/2A/2A
output currents. A wide 4.5V to 18V input supply voltage range encompasses the most intermediate bus
voltages operating off 5V, 9V, 12V or 15V power bus. The feedback voltage reference for each buck is 0.6V.
Each buck is independent with dedicated enable, soft-start and loop compensation pins.
The TPS65261, TPS65261-1 implements a constant frequency, peak current mode control that simplifies
external loop compensation. The wide switching frequency of 250kHz to 2MHz allows optimizing system
efficiency, filtering size and bandwidth. The switching frequency can be adjusted with an external resistor
connected between ROSC pin and ground. The switching clock of buck1 is 180° out-of-phase operation from
the clocks of buck2 and buck3 channels to reduce input current ripple, input capacitor size and power supply
induced noise.
The TPS65261, TPS65261-1 has been designed for safe monotonic startup into pre-biased loads. The default
start up is when VIN is typically 4.5V. The ENx pin also can be used to adjust the input voltage under voltage
lockout (UVLO) with an external resistor divider. In addition, the ENx pin has an internal 3.6uA current source, so
the EN pin can be floating to automatically power up the converters.
The TPS65261, TPS65261-1 reduces the external component count by integrating a bootstrap circuit. The bias
voltage for the integrated high-side MOSFET is supplied by a capacitor between the BST and LX pin. A UVLO
circuit monitors the bootstrap capacitor voltage VBST-VLX in each buck. When VBST-VLX voltage drops to the
threshold, LX pin is pulled low to recharge the bootstrap capacitor. The TPS65261, TPS65261-1 can operate at
100% duty cycle as long as the bootstrap capacitor voltage is higher than the BOOT-LX UVLO threshold which is
typically 2.1V.
The TPS65261, TPS65261-1 features a PGOOD pin to supervise each output voltage of the buck converters.
The TPS65261, TPS65261-1 has power good comparators with hysteresis, which monitor the output voltages
through feedback voltages. When all bucks are in regulation range and power sequence is done, PGOOD is
asserted to high.
The SS (soft start/tracking) pin is used to minimize inrush currents or provide power supply sequencing during
power up. A small value capacitor or resistor divider is connected to the pin for soft start or voltage tracking.
At light loading, TPS65261 will automatically operate in pulse skipping mode (PSM) to save power.
The TPS65261, TPS65261-1 is protected from overload and over temperature fault conditions. The converter
minimizes excessive output overvoltage transients by taking advantage of the power good comparator. When
the output is overvoltage, the high-side MOSFET is turned off until the internal feedback voltage is lower than
105% of the 0.6V reference voltage. The TPS65261, TPS65261-1 implements both high-side MOSFET overload
protection and bidirectional low-side MOSFET overload protection to avoid inductor current runaway. If the
overcurrent condition has lasted for more than the OC wait time (256 clock cycles), the converter will shut down
and re-start after the hiccup time (8192 clock cycles). The TPS65261, TPS65261-1 shuts down if the junction
temperature is higher than the thermal shutdown trip point. When the junction temperature drops 20°C typically
below the thermal shutdown trip point, the TPS65261, TPS65261-1 will be restarted under control of the soft
start circuit automatically.

TPS65261, TPS65261-1
7.2 Functional Block Diagram
ROSC
VIN VIN
V3V OSC/Phase Shift
V7V LDO
CLK1
CLK3
CLK2
V7V Bias
V7V
clk PVIN2
V7V clk en_buck2 enable VIN VIN
VIN PVIN1 BST2
VIN enable en_buck1 BST
BST1 BUCK2 LX2
BST MODE LX
LX1 BUCK1 PGND2
LX MODE PGND
PGND1 Comp 5 µA
PGND SS2
5 µA Comp vfb SS
SS1
SS vfb FB2
FB1
COMP1
1 µA
1 µA COMP2
VIN
1.23 V Power
VDIV Failure
deglitch
RESET clk V7V
PVIN3
PGOOD Power en_buck3 enable VIN VIN
Good BST3
BST
3.6 µA 3 µA FB1 LX3
BUCK3
FB2 MODE LX
MODE FB3 PGND3
PGND
2K 1.2 V Comp 5 µA
6.3 V SS3
vfb SS
3.6 µA 3 µA
EN1 FB3
en_buck1
2K 6.3 V 1.2 V
State en_buck2
Machine
3.6 µA 3 µA en_buck3
EN2
COMP3
2K 6.3 V 1.2 V
OT Over AGND
3.6 µA 3 µA
Temp
EN3
2K 6.3 V 1.2 V
7.3 Feature Description

7.3.1 Adjusting the Output Voltage
The output voltage of each buck is set with a resistor divider from the output of buck to the FB pin. It is
recommended to use 1% tolerance or better resistors.
Vout
R1
FB
COMP
R2
0.6 V
Figure 7-1. Voltage Divider Circuit
0.6
R2 = R1 ´
Vout - 0.6 (1)

TPS65261, TPS65261-1
To improve efficiency at light loads, consider using larger value resistors. If the values are too high, the regulator
is more sensitive to noise. The recommended resistor values are shown in Table 7-1.
Table 7-1. Output Resistor Divider Selection
OUTPUT VOLTAGE R1 R2
(V) (kΩ) (kΩ)
1 10 15
1.2 10 10
1.5 15 10
1.8 20 10
2.5 31.6 10
3.3 45.3 10
3.3 22.6 4.99
5 73.2 10
5 36.5 4.99
7.3.2 Power Failure Detector

The power failure detector monitors the voltage on VDIV, and sets open-drain output RESET low when VDIV
is below 1.23V. There is deglitch on the rising edge, 534 frequency cycles. Figure 7-2 shows the power failure
detector timing diagram.
VIN 1 µA V7V Threshold_r

Threshold_f
ih VIN
1 µA
R1
1.23 V V7V
Power
ip
VDIV Failure
RESET
RESET
R2 Delay Time
534 Cycles
Figure 7-2. Power Failure Detector Timing Diagram

TPS65261, TPS65261-1
The thresholds can be calculated using Equation 2 and Equation 3.
æ R1 ö
Threshold _ r = Vref ç 1 + ÷ - Ip ´ R1
è R2 ø (2)
æ R1 ö
Threshold _ f = Vref ç 1 + ÷ - (IP + Ih )´ R1
è R2 ø (3)
The divider resisters can be calculated using Equation 4 and Equation 5.
Threshold _ r - Threshold _ f
R1 =
Ih (4)
Vref
R2 =
Threshold _ r - Vref
´I + I
Threshold _ r - Threshold _ f h p (5)
Where Ih = 1µA, Ip = 1µA.

7.3.3 Enable and Adjusting Undervoltage Lockout
The EN1/2/3 pin provides electrical on/off control of the device. After the EN1/2/3 pin voltage exceeds the
threshold voltage, the device starts operation. If each ENx pin voltage is pulled below the threshold voltage, the
regulator stops switching and enters low Iq state.
The EN pin has an internal pull-up current source, allowing the user to float the EN pin to enable the device. If an
application requires controlling the EN pin, use open drain or open collector output logic to interface with the pin.
The device implements internal UVLO circuitry on the VIN pin. The device is disabled when the VIN pin voltage
falls below the internal VIN UVLO threshold. The internal VIN UVLO threshold has a hysteresis of 500mV. If an
application requires either a higher UVLO threshold on the VIN pin or a secondary UVLO on the PVINx in split
rail applications, then the ENx pin can be configured as shown in Figure 7-3, Figure 7-4 and Figure 7-5. When
using the external UVLO function, it is recommended to set the hysteresis to be greater than 500mV.
The EN pin has a small pull-up current Ip which sets the default state of the pin to enable when no external
components are connected. The pull-up current is also used to control the voltage hysteresis for the UVLO
function because it increases by Ih after the EN pin crosses the enable threshold. The UVLO thresholds can be
calculated using Equation 6 and Equation 7.
æV ö
VSTART ç ENFALLING ÷ - VSTOP
R1 = è VENRISING ø
æ V ö
IP ç 1 - ENFALLING ÷ + Ih
è VENRISING ø (6)
R1 ´ VENFALLING
R2 =
VSTOP - VENFALLILNG + R1 Ih + Ip ( ) (7)
Where Ih = 3µA, IP = 3.6uA, VENSRISING = 1.2V, VENFALLING = 1.15V.

TPS65261, TPS65261-1
VIN PVIN
ih ih
R1 R1
ip ip
EN EN
R2 R2
Figure 7-3. Adjustable VIN Undervoltage Lockout Figure 7-4. Adjustable PVIN Undervoltage Lockout,
VIN>4.5V
PVIN
VIN
ih
R1
ip
EN
R2
Figure 7-5. Adjustable VIN and PVIN Undervoltage Lockout
7.3.4 Soft-Start Time

The voltage on the respective SS pin controls the start-up of the buck output. When the voltage on the SS pin
is less than the internal 0.6V reference, the TPS65261, TPS65261-1 regulates the internal feedback voltage to
the voltage on the SS pin instead of 0.6V. The SS pin can be used to program an external soft-start function
or to allow output of the buck to track another supply during start-up. The device has an internal pull-up current
source of 5µA (typical) that charges an external soft-start capacitor to provide a linear ramping voltage at the
SS pin. The TPS65261, TPS65261-1 regulates the internal feedback voltage to the voltage on the SS pin,
allowing VOUT to rise smoothly from 0V to its regulated voltage without inrush current. The soft-start time can be
calculated approximately by Equation 8.
Css(nF) ´ Vref(V)
Tss (ms ) =
Iss(µA) (8)
Many of the common power supply sequencing methods can be implemented using the SSx and ENx pins.
Figure 7-6 shows the method implementing ratio-metric sequencing by connecting the SSx pins of three buck
channels together. The regulator outputs ramp up and reach regulation at the same time. When calculating the
soft-start time, the pull-up current source must be tripled in Equation 8.

TPS65261, TPS65261-1
31 EN
EN1 EN threshold=1.2 V
32
EN2
1
EN3
Vout3 = 3.3 V
24
SS1
Vout2 1.8 V
8
SS2 Vout1 1.2 V
17
SS3 PGOOD
Css
Tss = Css*0.6 V/15 µA PGOOD Deglitch Time
Figure 7-6. Ratio Metric Power Up Using SSx Pins

TPS65261, TPS65261-1
Simultaneous power supply sequencing can be implemented by connecting capacitor to SSx pin, shown in
Figure 7-7. The capacitors can be calculated using Equation 8 and Equation 9.
Css1 Css2 Css3

= =
Vout1 Vout2 Vout3 (9)
31 EN
EN1 EN threshold = 1.2 V
32
EN2
1
EN3
Vout3 = 3.3 V
24
SS1
Css1
Vout2 1.8 V
8
SS2
Vout1 1.2 V
Css2
17
SS3
PGOOD
Css3
Tss = Css3*0.6 V/5 µA PGOOD Deglitch Time
Figure 7-7. Simultaneous Startup Sequence Using SSx Pins
7.3.5 Power Up Sequencing

TPS65261, TPS65261-1 features a comprehensive sequencing circuit for the 3 bucks. If the MODE pin ties high
to V7V, three buck start up and shutdown is in sequence according to different buck enable pin setup. If the
MODE pin ties low to ground, three buck on/off is separately controlled by three enable pins.
7.3.5.1 External Power Sequencing
The TPS65261, TPS65261-1 has a dedicated enable pin and soft-start pin for each converter. The converter
enable pins are biased by a current source that allows for easy sequencing with the addition of an external
capacitor. Disabling the converter with an active pull-down transistor on the ENs pin allows for a predictable
power-down timing operation. Figure 7-8 shows the timing diagram of a typical buck power-up sequence by
connecting a capacitor at ENx pin.

TPS65261, TPS65261-1
VIN
V7V
EN Threshold
ENx Rise Time Charge CEN EN

Dictated by CEN with 6.6 µA Threshold
ENx
Soft Start Rise Time

Pre-Bias Startup
Dictated by Css
VOUTx
PGOOD Deglitch Time
t = CSS × 0.6 V / 5 µA
t = CEN × (1.2 - 0.4) V / 3.6 µA
t = CEN × 0.4 V / 1.4 µA
PGOOD
Figure 7-8. Startup Power Sequence
7.3.5.2 Automatic Power Sequencing

The TPS65261, TPS65261-1 starts with a pre-defined power-up and power-down sequence when the MODE pin
ties high to V7V. As shown in Table 7-2, the sequence is dictated by the different combinations of EN1 and EN2
status. EN3 is used to start/stop the converters. Buck2 and buck3 are identical converters and can be swapped
in the system operation to allow for additional sequencing stages. Figure 7-9 shows the power sequencing when
EN1 and EN2 are pulled up high.
Table 7-2. Power Sequencing
MODE EN1 EN2 EN3 Start Sequencing Shutdown Sequencing
High High High Buck1→Buck2→Buck3 Buck3→Buck2→Buck1
Used to start/stop
Automatic Power High Low High Buck2→Buck1→Buck3 Buck3→Buck1→Buck2
bucks in sequence
Sequencing High High Low Buck2→Buck3→Buck1 Buck1→Buck3→Buck2
High Low Low Reserved Reserved Reserved
Externally
Used to start/stop Used to start/stop Used to start/stop
controlled Low x x
buck1 buck2 buck3
sequencing

TPS65261, TPS65261-1
VIN
V7V
MODE
EN1
EN2
EN3
Buck1
Buck2
Buck3
PGOOD
t1 t2 t3 t4
T psdelay = t1 = t2 = t3 = t4 = 1024*(1/fsw)
Figure 7-9. Automatic Power Sequencing
7.3.6 V7V Low Dropout Regulator and Bootstrap

Power for the high-side and low-side MOSFET drivers and most other internal circuitry is derived from the V7V
pin. The internal built-in low dropout linear regulator (LDO) supplies 6.3V (typical) from VIN to V7V. A 10µF
ceramic capacitor must be connected from V7V pin to power ground.
If the input voltage, VIN, decreases to UVLO threshold voltage, the UVLO comparator detects the V7V pin
voltage and forces the converter off.
Each high-side MOSFET driver is biased from the floating bootstrap capacitor, CB, shown in Figure 7-10, which
is normally recharged during each cycle through an internal low-side MOSFET or the body diode of a low-side
MOSFET when the high-side MOSFET turns off. The boot capacitor is charged when the BST pin voltage is less
than VIN and BST-LX voltage is below regulation. The recommended value of this ceramic capacitor is 47nF. A
ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10V or higher is recommended
because of the stable characteristics over temperature and voltage. Each low-side MOSFET driver is powered
from the V7V pin directly.
To improve drop out, the device is designed to operate at 100% duty cycle as long as the BST to LX pin voltage
is greater than the BST-LX UVLO threshold, which is typically 2.1V. When the voltage between BST and LX
drops below the BST-LX UVLO threshold, the high-side MOSFET is turned off and the low-side MOSFET is
turned on allowing the boot capacitor to be recharged.

TPS65261, TPS65261-1
VIN
LDO
+ (VBSTx – VLXx)
nBootUV
– 2.1 V
PVINx
V7V BSTx
CBIAS
High-side
10 µF UVLO Bias Buck nBootUV Gate MOSFET CB
Controller Driver
PWM
LXx
Low-side
nBootUV BootUV Gate MOSFET
PWM Protection Driver
CLK
Figure 7-10. V7V Linear Dropout Regulator and Bootstrap Voltage Diagram
7.3.7 Out-of-Phase Operation

To reduce input ripple current, the switch clock of buck1 is 180° out-of-phase from the clock of buck2 and buck3.
This enables the system, having less input current ripple, to reduce the input capacitors’ size, cost and EMI.
7.3.8 Output Overvoltage Protection (OVP)
The device incorporates an output overvoltage protection (OVP) circuit to minimize output voltage overshoot.
When the output is overloaded, the error amplifier compares the actual output voltage to the internal reference
voltage. If the FB pin voltage is lower than the internal reference voltage for a considerable time, the output
of the error amplifier demands maximum output current. After the condition is removed, the regulator output
rises and the error amplifier output transitions to the steady state voltage. In some applications with small output
capacitance, the load can respond faster than the error amplifier. This leads to the possibility of an output
overshoot. Each buck compares the FB pin voltage to the OVP threshold. If the FB pin voltage is greater
than the OVP threshold, the high-side MOSFET is turned off preventing current from flowing to the output and
minimizing output overshoot. When the FB voltage drops lower than the OVP threshold, the high-side MOSFET
turns on at the next clock cycle.
7.3.9 Slope Compensation
To prevent the sub-harmonic oscillations when the device operates at duty cycles greater than 50%, the device
adds built-in slope compensation, which is a compensating ramp to the switch current signal.
7.3.10 Overcurrent Protection
The device is protected from overcurrent conditions with cycle-by-cycle current limiting on both the high-side
MOSFET and the low-side MOSFET.
7.3.10.1 High-side MOSFET Overcurrent Protection
The device implements current mode control which uses the COMP pin voltage to control the turn off of the
high-side MOSFET and the turn on of the low-side MOSFET on a cycle-by-cycle basis. During each cycle, the
switch current and the current reference generated by the COMP pin voltage are compared, when the peak
switch current intersects the current reference, the high-side switch is turned off.
7.3.10.2 Low-side MOSFET Overcurrent Protection
While the low-side MOSFET is turned on, its conduction current is monitored by the internal circuitry. During
normal operation, the low-side MOSFET sources current to the load. At the end of every clock cycle, the

TPS65261, TPS65261-1
low-side MOSFET sourcing current is compared to the internally set low-side sourcing current limit. If the
low-side sourcing current is exceeded, the high-side MOSFET is not turned on and the low-side MOSFET stays
on for the next cycle. The high-side MOSFET is turned on again when the low-side current is below the low-side
sourcing current limit at the start of a cycle.
The low-side MOSFET can also sink current from the load. If the low-side sinking current limit is exceeded, the
low-side MOSFET is turned off immediately for the rest of that clock cycle. In this scenario both MOSFETs are
off until the start of the next cycle.
Furthermore, if an output overload condition (as measured by the COMP pin voltage) has lasted for more than
the hiccup wait time which is programmed for 256 switching cycles shown in Figure 7-11, the device will shut
down itself and restart after the hiccup time of 8192 cycles. The hiccup mode helps reduce the device power
dissipation under severe overcurrent condition.
OCP peak inductor current threshold
OC limiting (waiting) time hiccup time soft start time

256 cycles 8192 cycles t = Css × 0.6 V / 5 µA
Output over loading
iL
Inductor Current
Soft-start is reset after OC waiting time
About 2.1 V
SS OC fault removed, soft-start, and output recovery 0.6 V
SS Pin Voltage
Output hard short circuit
Vout
Output Voltage
Figure 7-11. Overcurrent Protection
7.3.11 Power Good

The PGOOD pin is an open drain output. After feedback voltage of each buck is between 95% (rising) and
105% (falling) of the internal voltage reference, the PGOOD pin pull-down is de-asserted and the pin floats. It is
recommended to use a pull-up resistor between the values of 10kΩ and 100kΩ to a voltage source that is 5.5V
or less. The PGOOD is in a defined state after the VIN input voltage is greater than 1V, but with reduced current
sinking capability. The PGOOD achieves full current sinking capability after the VIN input voltage is above UVLO
threshold, which is 4.25V.
The PGOOD pin is pulled low when any feedback voltage of a buck is lower than 92.5% (falling) or greater than
107.5% (rising) of the nominal internal reference voltage. Also, the PGOOD is pulled low if the input voltage is
undervoltage locked up, thermal shutdown is asserted, the EN pin is pulled low or the converter is in a soft-start
period.

TPS65261, TPS65261-1
7.3.12 Adjustable Switching Frequency

The ROSC pin can be used to set the switching frequency by connecting a resistor to GND. The switching
frequency of the device is adjustable from 250KHz to 2MHz.
To determine the ROSC resistance for a given switching frequency, use Equation 10 or the curve in Figure 7-12.
To reduce the solution size, set the switching frequency as high as possible, but tradeoffs of the supply efficiency
and minimum controllable on time must be considered.
ƒosc (kHz ) = 39557 ´ R(kW)-0.975 (10)

200
175
150
125
ROSC (k
100
75
50
25
0
0 200 400 600 800 1000 1200 1400 1600 1800 2000
Switching Frequency (kHz) C010
Figure 7-12. ROSC versus Switching Frequency
7.3.13 Thermal Shutdown

The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds
160°C typically. The device reinitiates the power up sequence when the junction temperature drops below 140°C
typically.
7.4 Device Functional Modes
7.4.1 Pulse Skipping MODE (PSM)
The TPS65261 can enter high efficiency pulse skipping mode (PSM) operation at light load current.
When a controller is enabled for PSM operation, the peak inductor current is sensed and compared with 230mA
current typically. Because the integrated current comparator catches the peak inductor current only, the average
load current entering PSM varies with applications and external output filters. In PSM, the sensed peak inductor
current is clamped at 230mA.
When a controller operates in PSM, the inductor current is not allowed to reverse. The reverse current
comparator turns off the low-side MOSFET when the inductor current reaches zero, preventing it from reversing
and going negative.
Due to the delay in the circuit and current comparator tdly (typical 50ns at VIN = 12V), the real peak inductor
current threshold to turn off high-side power MOSFET, can shift higher depending on inductor inductance and
input/output voltages. The threshold of peak inductor current to turn off high-side power MOSFET can be
calculated by Equation 11.
Vin - Vout
ILPEAK = 230 mA + ´ tdly
L (11)
After the charge accumulated on the Vout capacitor is more than loading need, COMP pin voltage drops to low
voltage driven by the error amplifier. There is an internal comparator at the COMP pin. If COMP voltage is lower
than 0.35V, the power stage stops switching to save power.

TPS65261, TPS65261-1
230 mA
Turn off
high-side Power MOSFET
Inductor
Current Peak
Current
Sensing Current Comparator
IL_Peak x1 Delay: tdly
Inductor Peak Current
Figure 7-13. PSM Current Comparator

TPS65261, TPS65261-1
8 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information

The devices are triple synchronous step down dc/dc converters. They are typically used to convert a higher
dc voltage to lower dc voltages with continuous available output current of 3A/2A/2A. The following design
procedure can be used to select component values for the TPS65261 and TPS65261-1. This section presents a
simplified discussion of the design process.
8.2 Typical Application
C26 C15
R263 R153 22 pF
22 pF 20 K 19.5 K
R262 20 K R152 39 K
C24 C231 C17

10 nF 3.3 nF C181 10 nF
2.2 nF
R20
C232 R23 73.2 K R18 C182
22 pF 20 K 30 K 22 pF
24
23
22
21
20
19
18
17
SS1
COMP1
FB1
FB3
COMP3
SS3
AGND
ROSC
Vout1 R25 25 16 R16 Vout3

BST1 BST3
+1.2 V 0 0 + 1.8 V
L1 C25 C16 L3
Max. 3 A 47 nF 47 nF Max. 2 A
26 15
LX1 LX3
4.7 uH 4.7 uH
C261 C262 C151 C152
22 uF 22 uF 27 14 22 uF 22 uF
PGND1 PGND3
C28 C13
10 uF 13 10 uF
Vin
Vin 28 PVIN1 PVIN3
TPS65261
Vin 29 TPS65261-1 12 Vin
VIN PVIN2
R29 C29 C12
146 K 1 uF 10 uF
30 11
VDIV PGND2
R30 L2 C101 C102
20 K 22 uF 22 uF
31 10
EN1 LX2
C9 4.7 uH
Vout2
32 9 R9 47 nF + 3.3 V
EN2 BST2
PGOOD
COMP2
0 Max. 2 A
RESET
MODE
EN3
FB2
SS2
V7V
1
R7 C72
30 K 22 pF
C5 C8
R2 10 uF C71 10 nF
2.2 nF
100 K
PULL
R3 R102 39 K
100 K
R103
PGOOD
RESET
8.67 K C10
22 pF
Figure 8-1. Typical Application Schematic

TPS65261, TPS65261-1
8.2.1 Design Requirements

This example details the design of triple synchronous step-down converter. A few parameters must be known
in order to start the design process. These parameters are typically determined at the system level. For this
example, we start with the following known parameters:
Table 8-1. Design Parameters
DESIGN PARAMETER EXAMPLE VALUE
Vout1 1.2 V
Iout1 3A
Vout2 3.3 V
Iout2 2A
Vout3 1.8 V
Iout3 2A
Transient Response 1A Load Step ±5%
Input Voltage 12 V normal, 4.5 V to 18 V
Output Voltage Ripple ±1%
Switching Frequency 600 kHz
8.2.2 Detailed Design Procedure

8.2.2.1 Output Inductor Selection
To calculate the value of the output inductor, use Equation 12. LIR is a coefficient that represents the amount of
inductor ripple current relative to the maximum output current. The inductor ripple current is filtered by the output
capacitor. Therefore, choosing high inductor ripple currents impact the selection of the output capacitor because
the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In
general, the inductor ripple value is at the discretion of the designer; however, LIR is normally from 0.1 to 0.3 for
the majority of applications.
Vinmax - Vout Vout

L= ´
Io ´ LIR Vin max ´ ƒ sw (12)
For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded.
The RMS and peak inductor current can be found from Equation 14 and Equation 15.
Vinmax - Vout Vout

Iripple = ´
L Vinmax ´ ƒ sw (13)
2
æ Vout ´ (Vinmax - Vout ) ö
çç ÷÷
2 è Vinmax ´ L ´ ƒ sw ø
ILrms = IO +
12 (14)
Iripple
ILpeak = Iout +
2 (15)
The current flowing through the inductor is the inductor ripple current plus the output current. During power up,
faults or transient load conditions, the inductor current can increase above the calculated peak inductor current
level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of
the device. For this reason, the most conservative approach is to specify an inductor with a saturation current
rating equal to or greater than the switch current limit rather than the peak inductor current.

TPS65261, TPS65261-1
8.2.2.2 Output Capacitor Selection

There are three primary considerations for selecting the value of the output capacitor. The output capacitor
determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in
load current. The output capacitance needs to be selected based on the most stringent of these three criteria.
The desired response to a large change in the load current is the first criteria. The output capacitor needs to
supply the load with current when the regulator cannot. This situation can occur if there are desired hold-up
times for the regulator where the output capacitor must hold the output voltage above a certain level for a
specified amount of time after the input power is removed. The regulator is also temporarily not able to supply
sufficient output current if there is a large, fast increase in the current needs of the load such as a transition from
no load to full load. The regulator usually needs two or more clock cycles for the control loop to see the change
in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor must
be sized to supply the extra current to the load until the control loop responds to the load change. The output
capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing a
tolerable amount of drop in the output voltage. Equation 16 shows the minimum output capacitance necessary to
accomplish this.
2 ´ DIout
Co =
ƒ sw ´ DVout (16)
Where ΔIout is the change in output current, fsw is the regulators switching frequency and ΔVout is the allowable
change in the output voltage.
Equation 17 calculates the minimum output capacitance needed to meet the output voltage ripple specification.
Where fsw is the switching frequency, Voripple is the maximum allowable output voltage ripple, and Ioripple is the
inductor ripple current.
1 1
Co > ´
8 ´ ƒ sw V oripple
Ioripple (17)
Equation 18 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple
specification.
Voripple
Resr <
Ioripple (18)
Additional capacitance de-ratings for aging, temperature and DC bias must be factored in, which increases this
minimum value. Capacitors generally have limits to the amount of ripple current they can handle without failing or
producing excess heat. An output capacitor that can support the inductor ripple current must be specified. Some
capacitor data sheets specify the root mean square (RMS) value of the maximum ripple current. Equation 19 can
be used to calculate the RMS ripple current the output capacitor needs to support.
Vout ´ (Vinmax - Vout )

Icorms =
12 ´ Vinmax ´ L ´ ƒ sw (19)
8.2.2.3 Input Capacitor Selection

The TPS65261, TPS65261-1 requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of
at least 10 µF of effective capacitance on the PVIN input voltage pins. In some applications, additional bulk
capacitance can also be required for the PVIN input. The effective capacitance includes any DC bias effects.
The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must
also have a ripple current rating greater than the maximum input current ripple of The TPS65261, TPS65261-1.
The input ripple current can be calculated using Equation 20.

TPS65261, TPS65261-1
Vout (Vinmin - Vout )

Iinrms = Iout ´ ´
Vinmin Vinmin (20)
The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to
the capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material
that is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator
capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. The
output capacitor must also be selected with the DC bias taken into account. The capacitance value of a capacitor
decreases as the DC bias across a capacitor increases. The input capacitance value determines the input ripple
voltage of the regulator. The input voltage ripple can be calculated using Equation 21.
Iout max ´ 0.25

DVin =
Cin ´ ƒ sw (21)
8.2.2.4 Loop Compensation

The TPS65261, TPS65261-1 incorporates a peak current mode control scheme. The error amplifier is a trans-
conductance amplifier with a gain of 300 µS. A typical type II compensation circuit adequately delivers a phase
margin between 60° and 90°. Cb adds a high frequency pole to attenuate high frequency noise when needed. To
calculate the external compensation components, follow these steps.
1. Select switching frequency fsw that is appropriate for application depending on L and C sizes, output ripple,
and EMI. Switching frequency between 500kHz to 1MHz gives best trade-off between performance and cost.
To optimize efficiency, lower switching frequency is desired.
2. Set up cross over frequency, ƒc, which is typically between 1/5 and 1/20 of fsw.
3. RC can be determined by
2p ´ ƒc ´ Vo ´ Co
RC =
Gm _EA ´ Vref ´ Gm _PS (22)
Where Gm_EA is the error amplifier gain (300µS), Gm_PS is the power stage voltage to current conversion
gain (7.4A/V).
æ 1 ö
ç ƒp = ÷.
4. Calculate CC by placing a compensation zero at or before the dominant pole è Co ´ RL ´ 2p ø
RL ´ Co
CC =
RC (23)
5. Optional Cb can be used to cancel the zero from the ESR associated with CO.
RESR ´ Co
Cb =
RC (24)

TPS65261, TPS65261-1
LX VOUT
iL
RESR
Current Sense RL
Gm_PS = 7.4 A / V
I/V Converter Co
R1 C1
Vfb
COMP – FB
EA
+
Vref = 0.6 V
R2
Rc Gm_EA = 300 uS
Cb
Cc
Figure 8-2. DC/DC Loop Compensation

TPS65261, TPS65261-1
8.2.3 Application Curves
Figure 8-3. BUCK1, Soft-Start with No Load Figure 8-4. BUCK1, Soft-Start with Full Load

TPS65261, TPS65261-1
Figure 8-9. BUCK1, PSM Mode, Steady State

Operation at Light Load Figure 8-10. BUCK1, Steady State Operation with
Full Load
Figure 8-11. BUCK2, PSM Mode, Steady State Figure 8-12. BUCK2, Steady State Operation with
Operation at Light Load Full Load
Figure 8-13. BUCK3, PSM Mode, Steady State

Figure 8-14. BUCK3, Steady State Operation with
Operation with Light Load
Full Load

TPS65261, TPS65261-1
Figure 8-15. BUCK1, Load Transient, 0.75 A to 1.5 Figure 8-16. BUCK1, Load Transient, 1.5 A to 2.25
A SR = 0.25 A/µs A SR = 0.25 A/µs
Figure 8-17. BUCK2, Load Transient, 0.5 A to 1.0 A Figure 8-18. BUCK2, Load Transient, 1.0 A to 1.5 A
SR = 0.25 A/µs SR = 0.25 A/µs
Figure 8-19. BUCK3, Load Transient, 0.5 A to 1.0 A Figure 8-20. BUCK3, Load Transient, 1.0 A to 1.5 A
SR = 0.25 A/µs SR = 0.25 A/µs

TPS65261, TPS65261-1
Figure 8-21. BUCK1, Overcurrent Protection Figure 8-22. BUCK1, Hiccup and Recovery

TPS65261, TPS65261-1
Figure 8-27. Automatic Power Sequencing, Figure 8-28. Automatic Power Sequencing,
MODE=EN1=EN2=HIGH MODE=EN1=EN2=HIGH
Figure 8-29. Automatic Power Sequencing, Figure 8-30. Automatic Power Sequencing,
MODE=EN1= HIGH, EN2=LOW MODE=EN1=HIGH, EN2=LOW
Figure 8-31. Automatic Power Sequencing,

MODE=EN2=HIGH, EN1=LOW
Figure 8-32. Automatic Power Sequencing,
MODE=EN2=HIGH, EN1=LOW

TPS65261, TPS65261-1
Figure 8-33. Trigger Voltage 1.23V, Reset vs VDIV Figure 8-34. Deglitch Time, Reset vs VDIV
VIN = 12 V VOUT1 = 1.2 V/1.5 A VOUT2 = 3.3 V/1 A VIN = 12 V VOUT1 = 1.2 V/3 A VOUT2 = 3.3 V/2 A
VOUT3 = 1.8 V/1 A VOUT3 = 1.8 V/2 A
EVM Condition 4 Layers, 64 mm × 69 mm, TA = 27.2°C EVM Condition 4 Layers, 64 mm × 69 mm, TA = 27.2°C
Figure 8-35. Thermal Signature of TPS65261EVM Figure 8-36. Thermal Signature of TPS65261EVM
8.3 Power Supply Recommendations

The devices are designed to operate from an input voltage supply range between 4.5 V and 18 V. This input
power supply must be well regulated. If the input supply is located more than a few inches from the TPS65261 or
TPS65261-1 converter additional bulk capacitance can be required in addition to the ceramic bypass capacitors.
An electrolytic capacitor with a value of 47 μF is a typical choice.
8.4 Layout
8.4.1 Layout Guidelines
The TPS65261, TPS65261-1 can be laid out on 2-layer PCB, illustrated in Figure 8-37.
Layout is a critical portion of good power supply design. See Figure 8-37 for a PCB layout example. The top
contains the main power traces for PVIN, VOUT, and LX. Also on the top layer are connections for the remaining
pins of the TPS65261, TPS65261-1 and a large top side area filled with ground. The top layer ground area must
be connected to the bottom layer ground using vias at the input bypass capacitor, the output filter capacitor and
directly under the TPS65261, TPS65261-1 device to provide a thermal path from the exposed thermal pad land
to ground. The bottom layer acts as ground plane connecting analog ground and power ground.
For operation at full rated load, the top side ground area together with the bottom side ground plane must
provide adequate heat dissipating area. There are several signals paths that conduct fast changing currents or
voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power
supplies performance. To help eliminate these problems, the PVIN pin must be bypassed to ground with a low

TPS65261, TPS65261-1
ESR ceramic bypass capacitor with X5R or X7R dielectric. Care must be taken to minimize the loop area formed
by the bypass capacitor connections, the PVIN pins and the ground connections. The VIN pin must also be
bypassed to ground using a low ESR ceramic capacitor with X5R or X7R dielectric.
Because the LX connection is the switching node, the output inductor must be located close to the LX pins, and
the area of the PCB conductor minimized to prevent excessive capacitive coupling. The output filter capacitor
ground must use the same power ground trace as the PVIN input bypass capacitor. Try to minimize this
conductor length while maintaining adequate width. The small signal components must be grounded to the
analog ground path.
The FB and COMP pins are sensitive to noise so the resistors and capacitors must be located as close as
possible to the IC and routed with minimal lengths of trace. The additional external components can be placed
approximately as shown.

TPS65261, TPS65261-1
8.4.2 Layout Example
VOUT1 VOUT3
COMP1
COMP3
AGND
ROSC
SS1
FB1
FB3
SS3
BST1 BST3
LX1 LX3
PGND1 PGND3
PVIN1 PVIN3
PVIN PVIN
VIN PVIN2
VDIV PGND2
EN1 3 LX2
VIN
EN2 BST2
PGOOD
COMP2
RESET
MODE
EN3
V7V
FB2
SS2
VOUT2
TOPSIDE
GROUND
AREA
0.010 in. Diameter

Thermal VIA to Ground Plane
VIA to Ground Plane
Figure 8-37. PCB Layout

TPS65261, TPS65261-1
9 Device and Documentation Support

9.1 Documentation Support
9.1.1 Related Parts
PART NUMBER DESCRIPTION COMMENTS
TPS65262 4.5 V to 18 V, triple buck with dual adjustable Triple buck 3-A/1-A/1-A output current, dual LDOs 100-mA/200-mA
LDOs output current, automatic power sequencing
TPS65263 4.5 V to 18 V, triple buck with I2C interface Triple buck 3-A/2-A/2-A output current, I2C controlled dynamic voltage
scaling (DVS)
TPS65651-1/2/3 4.5 V to 18 V, triple buck with different Triple buck 3-A/2-A/2-A output current, support 1s, 32-ms, 256-ms
PGOOD deglitch time PGOOD deglitch time, adjustable current limit setting by external resistor
TPS65287 4.5 V to 18 V, triple buck with power switch Triple buck 3-A/2-A/2-A output current, up to 2.1-A USB power with
and push button control overcurrent setting by external resistor, push button control for intelligent
system power-on/power-off operation
TPS65288 4.5 V to 18 V, triple buck with dual power Triple buck 3-A/2-A/2-A output current, 2 USB power switches current
switches limiting at typical 1.2 A (0.8/1.0/1.4/1.6/1.8/2.0/2.2A available with
manufacture trim options)
9.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
9.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
9.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 24-Apr-2023
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
TPS65261-1RHBR ACTIVE VQFN RHB 32 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS Samples
65261-1
TPS65261-1RHBT ACTIVE VQFN RHB 32 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS Samples
65261-1
TPS65261RHBR ACTIVE VQFN RHB 32 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS Samples
65261
TPS65261RHBT ACTIVE VQFN RHB 32 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS Samples
65261
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 24-Apr-2023
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 4-Aug-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS TAPE DIMENSIONS

K0 P1
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2 Q1 Q2
Q3 Q4 Q3 Q4 User Direction of Feed
Pocket Quadrants
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS65261-1RHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.1 8.0 12.0 Q2
TPS65261-1RHBT VQFN RHB 32 250 180.0 12.4 5.3 5.3 1.1 8.0 12.0 Q2
TPS65261RHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.1 8.0 12.0 Q2
TPS65261RHBT VQFN RHB 32 250 180.0 12.4 5.3 5.3 1.1 8.0 12.0 Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 4-Aug-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS65261-1RHBR VQFN RHB 32 3000 346.0 346.0 33.0
TPS65261-1RHBT VQFN RHB 32 250 210.0 185.0 35.0
TPS65261RHBR VQFN RHB 32 3000 346.0 346.0 33.0
TPS65261RHBT VQFN RHB 32 250 210.0 185.0 35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RHB 32 VQFN - 1 mm max height
5 x 5, 0.5 mm pitch PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224745/A
www.ti.com
PACKAGE OUTLINE
RHB0032E SCALE 3.000
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
5.1 B
A
4.9
PIN 1 INDEX AREA
5.1 (0.1)
4.9
SIDE WALL DETAIL

OPTIONAL METAL THICKNESS
20.000
C
1 MAX
SEATING PLANE
0.05
0.00 0.08 C
2X 3.5
3.45 0.1 (0.2) TYP
9 16 EXPOSED
THERMAL PAD
28X 0.5
8
17 SEE SIDE WALL
DETAIL
2X SYMM
33
3.5
0.3
32X
0.2
24 0.1 C A B
1
0.05 C
32 25
PIN 1 ID SYMM
(OPTIONAL) 0.5
32X
0.3
4223442/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHB0032E VQFN - 1 mm max height
( 3.45)
SYMM
32 25
32X (0.6)
1 24
32X (0.25)
(1.475)
28X (0.5)
33 SYMM
(4.8)
( 0.2) TYP
VIA
8 17
(R0.05)
TYP
9 16
(1.475)
(4.8)
LAND PATTERN EXAMPLE

SCALE:18X
0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND
SOLDER MASK
METAL OPENING
SOLDER MASK METAL UNDER

OPENING SOLDER MASK
NON SOLDER MASK

SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS

4223442/B 08/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RHB0032E VQFN - 1 mm max height
4X ( 1.49)
(R0.05) TYP (0.845)
32 25
32X (0.6)
1 24
32X (0.25)
28X (0.5)
(0.845)
SYMM
33
(4.8)
8 17
METAL
TYP
9 16
SYMM
(4.8)
SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 33:

75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4223442/B 08/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023, Texas Instruments Incorporated

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SLVSCD3C – DECEMBER 2013 – REVISED MAY 2023

TPS6526x 4.5-V to 18-V Input Voltage, 3-A/2-A/2-A Output Current

(1) For all available packages, see the orderable addendum at

Changes from Revision A (December 2013) to Revision B (May 2014) Page

2 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: TPS65261 TPS65261-1

5 Pin Configuration and Functions

Figure 5-1. RHB Package 8-Pin VQFN (Top View)

Table 5-1. Pin Functions

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3

Product Folder Links: TPS65261 TPS65261-1

Table 5-1. Pin Functions (continued)

4 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: TPS65261 TPS65261-1

6.2 ESD Ratings

6.3 Recommended Operating Conditions

6.4 Thermal Information

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 5

Product Folder Links: TPS65261 TPS65261-1

6.5 Electrical Characteristics

6 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: TPS65261 TPS65261-1

6.5 Electrical Characteristics (continued)

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 7

Product Folder Links: TPS65261 TPS65261-1

6.6 Typical Characteristics

Figure 6-1. BUCK 1 Efficiency Figure 6-2. BUCK 2 Efficiency

Output Voltage (V) 3.31

VOUT = 1.2 V VOUT = 3.3 V

Output Voltage (V)

VOUT = 1.8 V VOUT = 1.2 V

8 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: TPS65261 TPS65261-1

6.6 Typical Characteristics (continued)

Output Voltage (V)

VOUT = 3.3 V VOUT = 1.8 V

0.604 Oscillator Frequency (kHz)

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 9

Product Folder Links: TPS65261 TPS65261-1

6.6 Typical Characteristics (continued)

EN Pin Threshold Raising (V)

VIN = 12 V EN = 1.5 V VIN = 12 V

1.19 Soft Start Current (mA) 5.2

High Side Current Limit (A)

10 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: TPS65261 TPS65261-1

6.6 Typical Characteristics (continued)

VDIV Pin Threshold (V)

VIN = 12 V Figure 6-20. VDIV Pin Threshold vs Temperature

Figure 6-19. Buck3 High-Side Current Limit vs Temperature

Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 11

Product Folder Links: TPS65261 TPS65261-1

12 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated

Product Folder Links: TPS65261 TPS65261-1

7.2 Functional Block Diagram

7.3 Feature Description