PIC CONTROLLERS

MPMC
 TYPES OF MICROCONTROLLERS
• INTEL 8051

• ARM PROCESSORS (FROM MANY VENDORS) USING ARM7 OR CORTEX-M3 CORES ARE GENERALLY MICROCONTROLLERS

• STMICROELECTRONICS STM8 (8-BIT), ST10 (16-BIT) AND STM32 (32-BIT)

• ATMEL AVR (8-BIT), AVR32 (32-BIT), AND AT91SAM (32-BIT)

• FREESCALE COLDFIRE (32-BIT) AND S08 (8-BIT)

• HITACHI H8, HITACHI SUPERH (32-BIT)

• MIPS (32-BIT PIC32)

• NEC V850 (32-BIT)

• MICROCHIP PIC (8-BIT PIC16, PIC18, 16-BIT DSPIC33/PIC24)

• POWERPC ISE

• PSOC (PROGRAMMABLE SYSTEM-ON-CHIP)

• TEXAS INSTRUMENTS MICROCONTROLLER MSP 430 (16-BIT), C2000 (32-BIT), AND STELLARIS (32-BIT)

• TOSHIBA TLCS-870 (8-BIT/16-BIT)

• ZILOG EZ8 (16-BIT), EZ80 (8-BIT) ………………………………….

 PIC (PERIPHERAL INTERFACE CONTOLLER)

• PIC WAS DEVELOPED IN THE YEAR 1993 BY THE GENERAL INSTRUMENTS

MICROCONTROLLERS.
• PIC IS A POPULAR 8/ 16/ 32 BIT FAMILY OF MC FROM MICROCHIP
TECHNOLOGY.
• PIC MICROCONTROLLERS ARE USED IN APPLICATIONS SUCH AS
SMARTPHONES, AUDIO ACCESSORIES, AND ADVANCED MEDICAL DEVICES.
• THE PIC MC IS BASED ON RISC ARCHITECTURE.
• ITS MEMORY ARCHITECTURE FOLLOWS THE HARVARD PATTERN OF SEPARATE
MEMORIES FOR PROGRAM AND DATA, WITH SEPARATE BUSES.
 HARVARD VS VON NEUMANN
ARCHITECTURE ARCHITECTURE
 CONT..

• VON NEUMANN (PRINCETON) ARCHITECTURE.

• THE SAME BUS IS USED FOR ACCESSING BOTH THE CODE AND DATA
• PENTIUM PROCESSOR IS BASED ON VON NEUMANN ARCHITECTURE
• HARVARD ARCHITECTURE
• SEPARATE BUSES ARE USED FOR ACCESSING THE CODE AND DATA MEMORY.
• THAT MEANS THAT WE NEED FOUR SETS OF BUSES:
1. A SET OF DATA BUSES FOR CARRYING DATA INTO AND OUT OF THE CPU,
2. A SET OF ADDRESS BUSES FOR ACCESSING THE DATA,
3. A SET OF DATA BUSES FOR CARRYING CODE INTO THE CPU, AND
4. AN ADDRESS BUS FOR ACCESSING THE CODE
• THIS IS EASY TO IMPLEMENT INSIDE AN IC CHIP SUCH AS A MICROCONTROLLER WHERE BOTH
ROM CODE AND DATA RAM ARE INTERNAL (ON-CHIP) AND DISTANCES ARE ON THE MICRO
AND MILLIMETER SCALE
 RISC VS CISC
• CISC (COMPLEX INSTRUCTION SET COMPUTER)
• A LARGE NUMBER OF INSTRUCTIONS, TYPICALLY FROM 100 TO 250 INSTRUCTIONS
• SOME INSTRUCTIONS THAT PERFORM SPECIALIZED TASK AND ARE USED INFREQUENTLY
• A LARGE VARIETY OF ADDRESSING MODES, TYPICALLY FROM 5 TO 20 DIFFERENT MODES
• VARIABLE-LENGTH INSTRUCTION FORMATS

• RISC (REDUCED INSTRUCTION SET COMPUTER)

• RELATIVELY FEW INSTRUCTIONS
• RELATIVELY FEW ADDRESSING MODES
• FIXED-LENGTH, EASILY DECODED INSTRUCTION FORMAT
 PIC MICROCONTROLLER PRODUCT FAMILY
• FIRST FAMILY: PIC10 (10FXXX) CALLED LOW END OR BASELINE
• 12 BIT INSTRUCTION SET ARCHITECTURE (ISA), 6-40 PIN PACKAGES.

• SECOND FAMILY: PIC12 (PIC12FXXX), PIC16 (16FXXX) CALLED MID-

RANGE
• SUPPORTS INTERRUPTS, ON CHIP PERIPHERALS, 14 BIT ISA, 8-64 PIN PACKAGES.

• THIRD FAMILY: PIC 17/18 (18FXXX) HIGH PERFORMANCE

• HIGH MEMORY DENSITY (128KB CM AND 4 KB DM), SUPPORTS ON-CHIP USB,
CAN; 16 BIT ISA, 16MBPS SPEED
 EXAMPLES
• 8-BIT MICROCONTROLLERS - PIC10, PIC12, PIC14, PIC16, PIC17, PIC18
• 16-BIT MICROCONTROLLERS - PIC24F, PIC24H
• 32-BIT MICROCONTROLLERS - PIC32
• 16-BIT DIGITAL SIGNAL CONTROLLERS - DSPIC30, DSPIC33F

• THE F IN A NAME GENERALLY INDICATES THE PICMICRO USES FLASH MEMORY AND CAN BE ERASED
ELECTRONICALLY.
• THE C GENERALLY MEANS IT CAN ONLY BE ERASED BY EXPOSING THE DIE TO ULTRAVIOLET LIGHT (WHICH IS
ONLY POSSIBLE IF A WINDOWED PACKAGE STYLE IS USED).
• AN EXCEPTION TO THIS RULE IS THE PIC16C84 WHICH USES EEPROM AND IS THEREFORE ELECTRICALLY
ERASABLE.
 POPULARITY OF PIC16F877A
• CHEAP, VERY EASY TO BE ASSEMBLED, THE ADDITIONAL COMPONENTS NEEDED TO MAKE THIS
IC WORK IS JUST A 5V POWER SUPPLY ADAPTER, A 20MHZ CRYSTAL OSCILLATOR AND 2
UNITS OF 22PF CAPACITORS.
• THIS IC CAN BE REPROGRAMMED AND ERASED UP TO 10,000 TIMES.
• THEREFORE IT IS VERY GOOD FOR NEW PRODUCT DEVELOPMENT PHASE.
• BUT THIS IC HAS NO INTERNAL OSCILLATOR SO YOU WILL NEED AN EXTERNAL CRYSTAL OF
OTHER CLOCK SOURCE.
 PIN DIAGRAM
Quad Flat Package (QFP)

Plastic Leaded Chip Carrier Package (PLCC)

Dual Inline Package (DIP)

ARCHITECTURE
 MEMORY OF THE PIC16F877
• DIVIDED INTO 3 TYPES OF MEMORIES:
• FLASH OR PROGRAM MEMORY
• A MEMORY THAT CONTAINS THE PROGRAM CODE (WRITTEN BY THE PROGRAMMER), AFTER BURNING INTO IT.
• PROGRAM COUNTER (13 BIT WIDE) EXECUTES COMMANDS STORED IN THE PROGRAM MEMORY, ONE AFTER THE OTHER.
• PC IS CABLE OF ADDRESSING 8 KB B OF PROGRAM MEMORY LOCATIONS.
• PM BUS IS 14 BIT WIDE-(0000-3FFFH) (THE SIZE OF THE PROGRAM MEMORY IS LARGER THAN THE SIZE OF DATA
MEMORY).
• THE PROGRAM MEMORY IS ORGANIZED IN WORDS OF 12, 14, OR 16 BITS

• DATA MEMORY
• THIS IS RAM MEMORY TYPE, WHICH CONTAINS A SPECIAL REGISTERS LIKE SFR (SPECIAL FUNCTION REGISTER) AND GPR
(GENERAL PURPOSE REGISTER).
• THE VARIABLES THAT WE STORE IN THE DATA MEMORY DURING THE PROGRAM ARE DELETED AFTER WE TURN OFF THE
MC.
• DBUS IS 8 BIT WIDE (000-1FFH)

• DATA EEPROM (ELECTRICALLY ERASABLE PROGRAMMABLE READ ONLY MEMORY)

• A MEMORY THAT ALLOWS STORING THE VARIABLES AS A RESULT OF BURNING THE WRITTEN PROGRAM.
• DIVIDED INTO PAGES OF 2KB EACH
 CONT..
• EACH ONE OF THEM HAS A DIFFERENT ROLE.
• PROGRAM MEMORY AND DATA MEMORY TWO MEMORIES THAT ARE NEEDED TO BUILD A
PROGRAM, AND DATA EEPROM IS USED TO SAVE DATA AFTER THE MICROCONTROLLER IS TURN OFF.
• DATA MEMORY PARTITIONED INTO BANKS (4 NOS)
• DM BANK SELECTED FROM RP1 AND RP0 BITS OF STATUS REGISTERS

Code Address Reg/ Mem Addr

DATA
PROGRAM MEMORY
PROCESSOR
MEMORY (SFR, W,
Instruction Data read/ write GPR)
 DATA MEMORY (RAM)
• MEMORY STORAGE FOR VARIABLES
• DATA MEMORY IS ALSO KNOWN AS REGISTER FILE AND CONSISTS OF TWO COMPONENTS.
• GENERAL PURPOSE REGISTER FILE (SAME AS RAM).
• SPECIAL PURPOSE REGISTER FILE (SIMILAR TO SFR IN 8051).
• ADDRESSES RANGE FROM 0 TO 511 AND PARTITIONED INTO 4 BANKS
• EACH BANK EXTENDS UP TO 7FH (128 BYTES).
• THE USER CAN ONLY ACCESS A RAM BYTE IN A SET OF 4 BANKS AND ONLY ONE BANK AT A TIME.
• THE DEFAULT BANK IS BANK0.
• TO ACCESS A REGISTER THAT IS LOCATED IN ANOTHER BANK, ONE SHOULD ACCESS IT INSIDE THE
PROGRAM.
• THERE ARE SPECIAL REGISTERS WHICH CAN BE ACCESSED FROM ANY BANK, SUCH AS STATUS
REGISTER.
 PIC16F877 REGISTERS
•W
• PC
• PCL
• PCLATH
• STATUS
• FSR
 W REGISTER

• W, THE WORKING REGISTER, IS USED BY MANY INSTRUCTIONS AS THE SOURCE OF AN

OPERAND.
• THIS IS SIMILAR TO ACCUMULATOR IN 8051.
• IT MAY ALSO SERVE AS THE DESTINATION FOR THE RESULT OF THE INSTRUCTION EXECUTION.
• IT IS AN 8-BIT REGISTER.
• USED IN ALL ALU OPERATIONS
 PROGRAM COUNTER, PCL & PCLATH
• PROGRAM COUNTER (PC)
• IT IS 13 BIT AND CAPABLE OF ADDRESSING AN 8K WORD X 14 BIT PROGRAM MEMORY SPACE.
• PC KEEPS TRACK OF THE PROGRAM EXECUTION BY HOLDING THE ADDRESS OF THE CURRENT INSTRUCTION.
• PC IS FORM BY THE CONTENTS OF THE TWO REGISTERS PCL AND PCH

• PCL REGISTER PCH (5 BIT) PCL (8 BIT)

• (PROGRAM COUNTER LOW BYTE) PCL IS ACTUALLY THE LOWER 8-BITS OF THE 13-BIT PROGRAM COUNTER. THIS IS A
BOTH READABLE AND WRITABLE REGISTER.

• PCLATH REGISTER
• (PROGRAM COUNTER LATCH) PCLATH IS A 8-BIT REGISTER WHICH CAN BE USED TO DECIDE THE UPPER 5-BITS OF THE PC.
• PCLATH IS NOT THE UPPER 5BITS OF THE PC.
• PCLATH CAN BE READ FROM OR WRITTEN TO WITHOUT AFFECTING THE PC.
• THE UPPER 3 BITS OF PCLATH REMAIN ZERO AND THEY SERVE NO PURPOSE.
• WHEN PCL IS WRITTEN TO, THE LOWER 5BITS OF PCLATH ARE AUTOMATICALLY LOADED TO THE UPPER 5BITS OF THE PC.
• **PCH IS WRITTEN INDIRECTLY FROM PCLATH. LOWER 5 BITS OF PCLATH IS COPIED INTO PCH WHEN PCL IS LOADED
WITH ANY VALUE (8 BIT) TO GENERATE THE COMPLETE 13 BIT ADDRESS.

0 0 0 PCLATH4 PCLATH3 PCLATH2 PCLATH1 PCLATH0

 STATUS REGISTER

• IT IS AN 8-BIT REGISTER THAT STORES THE STATUS OF THE PROCESSOR.

• IN MOST CASES, THIS REGISTER IS USED TO SWITCH BETWEEN THE BANKS (REGISTER BANK SELECT), BUT ALSO HAS OTHER CAPABILITIES.

IRP RP1 RP0 TO PD Z DC C

• IRP - REGISTER BANK SELECT BIT. IPR=0 BANK 0, 1 ( INDIRECT ADDRESS 000H TO 0FF H); IPR=1= BANK 2, 3 ( INDIRECT ADDRESS 100H TO 1FF H);

• RP1: REGISTER BANK SELECT BIT 1 RP1 RP0 MEMORY BANK

• RP0: - REGISTER BANK SELECT BIT 0.
0 0 0
• TO: TIME-OUT BIT; 1 AFTER POWER UP/EXECUTION OF CLRWDT// SLEEP INSTRUCTION; 0 ON WD TIMEOUT

• PD: POWER-DOWN BIT (USED IN CONJUNCTION WITH PIC’S SLEEP MODE)

0 1 1

• Z: ZERO BIT 1 0 2
• DC: DIGIT CARRY/BORROW BIT
1 1 3
• C: CARRY/BORROW BIT
 FSR
• FSR REGISTER (FILE SELECTION REGISTER)
• IT IS AN 8-BIT REGISTER USED AS DATA MEMORY ADDRESS POINTER.
• THIS IS USED IN INDIRECT ADDRESSING MODE TO ACCESS GPR/ SFR

• INDF REGISTER (INDIRECT THROUGH FSR)

• IT IS NOT A PHYSICAL REGISTER (VIRTUAL REGISTER).
• ACCESSING INDF IS ACTUALLY ACCESS THE LOCATION POINTED TO BY FSR IN INDIRECT
ADDERSSING MODE.
 MEMORY MAP REGISTERS

• STATUS REGISTER – CHANGES/MOVES FROM/BETWEEN THE BANKS.

• PORT REGISTERS – ASSIGNS LOGIC VALUES (“0”/”1”) TO THE PORTS
• TRISX (X=A/B/C/D/E) REGISTERS – DATA DIRECTION REGISTER (INPUT/OUTPUT)
• TRISX.N (SETS/ RESETS PARTICULAR PORT BIT)
 STACK

• AN INDEPENDENT 8-LEVEL HARDWARE STACK. (NOT A PART OF RW MEMORY)

• THE STACK IS ORGANIZED AS 8X13BIT REGISTERS.
• WHEN AN INTERRUPT OCCURS OR DURING CALL, THE PC IS PUSH-ED ONTO THE STACK.
• PC IS POP-ED OUT WHEN RETURN INSTRUCTION IS ENCOUNTERED
• STACK OPERATES AS A CIRCULAR QUEUE
• I/O PORTS:
PIC16F877 PERIPHERAL FEATURES
• PIC16F877 HAS 5 I/O PORTS:
• PORT A HAS 6 BIT WIDE, BIDIRECTIONAL
• PORT B, C, D HAVE 8 BIT WIDE, BIDIRECTIONAL
• PORT E HAS 3 BIT WIDE, BIDIRECTIONAL
• IN ADDITION, THEY HAVE THE FOLLOWING ALTERNATE FUNCTIONS:
Port A Alternate uses of I/O Pins No of I/O Pin
Port A AD Converter inputs 6
Port B External interrupt inputs 8
Port C Serial Port, Timer I/O 8
Port D Parallel Slave port 8
Port E AD Converter inputs 3
 ANALOG TO DIGITAL CONVERTER (ADC)
• ONLY AVAILABLE IN 14BIT AND 16BIT CORES
• FS (SAMPLE RATE) < 54KHZ
• THE RESULT IS A 10 BIT DIGITAL NUMBER
• CAN GENERATE AN INTERRUPT WHEN ADC CONVERSION IS DONE
• THE A/D MODULE HAS 4 REGISTERS:
• A/D RESULT HIGH REGISTER (ADRESH)
• A/D RESULT LOW REGISTER (ADRESL)
• A/D CONTROL REGISTER0 (ADCON0)
• A/D CONTROL REGISTER1 (ADCON1)

• MULTIPLEXED 8 CHANNEL INPUTS

• MUST WAIT T ACQ TO CHANGE UP SAMPLING CAPACITOR.

• CAN TAKE A REFERENCE VOLTAGE DIFFERENT FROM THAT OF THE CONTROLLER.

 TIMER/COUNTER MODULES

• GENERATE INTERRUPTS ON TIMER OVERFLOW

• CAN USE EXTERNAL PINS AS CLOCK IN/ CLOCK OUT
• THERE ARE 3 TIMER/COUNTER MODULES
 UNIVERSAL SYNCHRONOUS ASYNCHRONOUS
RECEIVER TRANSMITTER
• (USART/SCI) WITH 9-BIT ADDRESS DETECTION
• ASYNCHRONOUS COMMUNICATION:
• UART (RS 232 SERIAL)

• SYNCHRONOUS COMMUNICATION:
• SPI = SERIAL PERIPHERAL INTERFACE
• I2C = INTER IC
 CAPTURE, COMPARE, PWM (CCP) MODULES

• CAPTURE IS 16-BIT, MAX. RESOLUTION IS 12.5 NS

• COMPARE IS 16-BIT, MAX. RESOLUTION IS 200 NS
• PWM MAX. RESOLUTION IS 10-BIT
 PARALLEL SLAVE PORT (PSP)

• 8-BITS WIDE, WITH EXTERNAL RD, WR AND CS CONTROLS

 INTERRUPTS

• 14 INTERRUPT SOURCES
• INTCON (INTERRUPT CONTROL) REGISTER HOLDS INTERRUPT ENABLE BITS.
• ONLY 1 INTERRUPT VECTOR ADDRESS- 0004H
 WATCH DOG TIMER

• IT KEEPS TRACK OF THE PROPER OPERATION OF THE CONTROLLER

• DURING NORMAL OPERATION IT RESETS CONTROLLER AFTER A TIMEOUT
• DURING SLEEP MODE WD TIMER TIMEOUT WAKES UP MC AND PUTS CONTROLLER IN NORMAL
OPERATION OPERATION MODE
 RESET CONDITIONS

• POWER ON RESET→ VOLTAGE SUPPLY REACHES 0 TO 1.2-1.7V

• BROWN OUR RESET→ VOLTAGE LEVELS BELOW THRESHOLD VOLTAGE
• WATCH DOG RESET→ WD TIMEOUT
• EXTERNAL RESET

• POWER SAVING THROUGH SLEEP MODE

 PROGRAMMING THE PIC

• MP LAB FROM MICROCHIP TECHNOLOGIES IS THE IDE FOR PIC CONTROLLERS

END OF SLIDES