Microprocessor & Microcontroller

UPCIE501

Course Notes prepared and compiled

By

Ananya Dastidar
Assistant Professor
Department of Instrumentation and Electronics Engineering

For

B.Tech., Fifth Semester

As per
CET, Bhubaneswar (Autonomous) Syllabus

DEPARTMENT OF INSTRUMENTATION AND ELECTRONICS ENGINEERING

(Specialization in SIGNAL PROCESSING ENGINEERING)
COLLEGE OF ENGINEERING AND TECHNOLOGY, BHUBANESWAR (AUTONOMOUS)
Academic Session, 2020-21

1| UPCIE501 Microprocessor & Microcontroller Module I

 Module I
(Microprocessor)

2| UPCIE501 Microprocessor & Microcontroller Module I

Lecture 2

PIN DESCRPTION of Intel 8085

The 8085 microprocessor is available on a 40-pin Dual-in-Line package (DIP).

Source: https://electronicslesson.com/microprocessor/8085-microprocessor-pin/

The pins are grouped as:

 Frequency and power supply signals ( X1, X2, Vcc, Vss)
 Higher order address bus (A8-A15)
 Multiplexed address/data bus (AD7-AD0)
 Control and status signals (ALE, ̅̅̅̅ ̅̅̅̅̅ ̅ , S0, S1)

 Serial IO signals (SID, SOD)

 Externally or peripheral initiated signals. (TRAP, RST 7.5, RST 6.5, RST 5.5, INTR,
̅̅̅̅̅̅̅ , HOLD, HLDA, Ready, ̅̅̅̅̅̅̅̅̅̅̅, Reset Out, Clk)

3| UPCIE501 Microprocessor & Microcontroller Module I

The pin description is as follows:

X1, X2 (Input): Crystal Input

Crystal or RC network connections to set the internal clock generator X1 can also be an external
clock input instead of a crystal. The input frequency is divided by 2 to give the internal operating
frequency.

RESET OUT (Output):

Indicates CPU is being reset. Can be used as a system RESET. The signal is synchronized to the
processor clock.

SOD (output): Serial output data line

The output SOD is set or reset as specified by the SIM instruction.

SID (Input): Serial input data line

The data on this line is loaded into accumulator bit 7 whenever a RIM instruction is executed.

TRAP (Input):
Trap interrupt is a non-maskable restart interrupt. It is recognized at the same time as INTR. It is
unaffected by any mask or Interrupt Enable. It has the highest priority of any interrupt.

RST 5.5, RST 6.5, RST 7.5 (Inputs): Restart Interrupts

These three inputs have the same timing as INTR except they cause an internal RESTART to be
automatically inserted.
RST 7.5 --------- Highest Priority
RST 6.5---------- Medium Priority
RST 5.5--------Lowest Priority
The priority of these interrupts is ordered as shown above. These interrupts have a higher priority
than the INTR.

INTR (Input): Interrupt Request

It is used as a general purpose interrupt. It is sampled only during the next to the last clock cycle
of the instruction. If it is active, the Program Counter (PC) will be inhibited from incrementing
and an INTA will be issued. During this cycle a RESTART or CALL instruction can be inserted
to jump to the interrupt service routine. The INTR is enabled and disabled by software. It is
disabled by Reset and immediately after an interrupt is accepted.

̅̅̅̅̅̅̅ (Output): Interrupt Acknowledge

It is used instead of (and has the same timing as) RD during the Instruction cycle after an INTR
is accepted. It can be used to activate the 8259 Interrupt chip or some other interrupt port.

AD0 - AD7 (Input/ Output 3state): Multiplexed Address/Data Bus

Lower 8 bits of the memory address (or I/0 address) appear on the bus during the first clock
cycle of a machine state. It then becomes the data bus during the second and third clock cycles.
Tri stated during Hold and Halt modes.
Vss: Ground Reference.
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A15 – A8 (Output tri-state): Address Bus
The most significant 8 bits of the memory address or the 8 bits of the I/0 addresses, tri stated
during Hold and Halt modes.

ALE (Output): Address Latch Enable

It occurs during the first clock cycle of a machine state and enables the address to get latched
into the on chip latch of peripherals. The falling edge of ALE is set to guarantee setup and hold
times for the address information. ALE can also be used to strobe the status information. ALE is
never tri-stated.

̅̅̅̅ (Output tri-state): READ

Indicates the selected memory or 1/0 device is to be read and that the Data Bus is available or the
data transfer.

̅̅̅̅̅ (Output 3state): WRITE

Indicates the data on the Data Bus is to be written into the selected memory or 1/0 location.

S0, S1 (Output): Data Bus Status

Encoded status of the bus cycle:

S0 S1 Status

0 0 HALT
0 1 READ

1 0 WRITE

1 1 FETCH
S1 can be used as an advanced R/W status.

IO/ ̅ (Output): Input Output/ Memory Select

It indicates whether the Read/Write is to memory or l/O Tristated during Hold and Halt modes.

READY (Input):
If Ready is high during a read or write cycle, it indicates that the memory or peripheral is ready to
send or receive data. If Ready is low, the CPU will wait for Ready to go high before completing
the read or write cycle.

̅̅̅̅̅̅̅̅̅̅̅̅̅̅ (Input):
Reset sets the Program Counter to zero and resets the Interrupt Enable and HLDA flip-flops.
None of the other flags or registers (except the instruction register) are affected The CPU is held
in the reset condition as long as Reset is applied.
CLK (Output): Clock
Clock Output for use as a system clock when a crystal or R/ C network is used as an input to the
5| UPCIE501 Microprocessor & Microcontroller Module I
CPU. The period of CLK is twice the X1, X2 input period.

HLDA (Output): Hold Acknowledge

Indicates that the CPU has received the Hold request and that it will relinquish the buses in the
next clock cycle. HLDA goes low after the Hold request is removed. The CPU takes the buses
one half clock cycle after HLDA goes low.

HOLD (Input):
Indicates that another Master is requesting the use of the Address and Data Buses. The CPU,
upon receiving the Hold request. will relinquish the use of buses as soon as the completion of the
current machine cycle. Internal processing can continue. The processor can regain the buses only
after the Hold is removed. When the Hold is acknowledged, the Address, Data, RD, WR, and
IO/M lines are tristated.

Vcc: +5 volts supply.

6| UPCIE501 Microprocessor & Microcontroller Module I

ADDRESSING MODES OF 8085

An Instruction is a command given to the computer to perform a specified operation on given

data. The instruction set of a microprocessor is the collection of the instructions that
the microprocessor is designed to execute (in lecture on Instruction set).

Instruction= Op-code + Operand

An op-code is the first byte of an instruction in machine language which tells the
hardware what operation needs to be performed with this instruction.
Every processor/controller has its own set of op-code defined in its architecture.
An op-code is followed by an operand that can be a 16 bit address or 8 bit data etc. as
necessary.
To perform any operation, we have to give the corresponding instructions to the
microprocessor.

In each instruction, programmer has to specify 3 things:

Operation to be performed.
Address of source of data.
Address of destination of result.

The method by which the address of source of data or the address of destination of result is given
in the instruction is called Addressing Modes.

The term addressing mode refers to the way in which the operand of the instruction is specified.
Intel 8085 uses the following addressing modes:

1. Direct Addressing Mode

2. Register Addressing Mode
3. Register Indirect Addressing Mode
4. Immediate Addressing Mode
5. Implicit Addressing Mode

Direct Addressing Mode

In this mode, the address of the operand is given in the instruction itself.
Example
STA 2500H Store the contents of Accumulator into the memory location 2500H.
STA is the operation to be performed represented by 8 bit opcode 32.
2500 H is the 16 bit address of destination.
Accumulator is the source.
Other examples are LDA 4533H etc.

Register Addressing Mode

In this mode, the operand is in general purpose register.

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Example
MOV A, B Move the contents of B register to A register.
MOV is the operation.
B is the data source.
Accumulator is the destination.
Other examples are ADD B etc.

Register Indirect Addressing Mode

In this mode, the address of operand is specified by a register pair.
Example
MOV A, M
Move the contents of Memory location which is pointed to by HL register pair to A register.
MOV is the operation.
M is the memory location specified by H-L register pair.
Accumulator is the destination.
Other examples are LDAX B etc.

Immediate Addressing Mode

In this mode, the operand is specified within the instruction itself.
Example
MVI A, 45H
Move the content 45H to A register.
MVI is the operation.
22H is the immediate data.
Accumulator is the destination.
Other examples are ORI 26H etc.

Implicit Addressing Mode

If address of source of data as well as address of destination of result is fixed, then there is no
need to give any operand along with the instruction.
Example
CMA
Complements the Accumulator contents and stored into Accumulator.
CMA is the operation.
A is the source.
A is the destination.
Other examples are NOP etc.

Task
Mention the addressing Modes of the following instructions

SIM, ADI ABH, SBB B, XRI DEH, LDA CACAH

8| UPCIE501 Microprocessor & Microcontroller Module I