UNIT-III

INTERRUPTS AND PROGRAMMABLE

INTERRUPT CONTROLLERS
By
J.KRISHNA CHAITHANYA
ASSOCIATE PROFESSOR
DEPT. OF ECE
VCE, SHAMSHABAD – 501 218.
 Contents
 8086 Interrupts & Interrupt Responses
 Introduction to DOS and BIOS interrupts
 8259A Priority Interrupt Controller
 Software Interrupt Applications
 Asynchronous and synchronous data transfer
schemes
 8251 USART architecture and interfacing
 RS - 232C Serial data standard
 RS- 423A and RS - 422A
 Sample program of serial data transfer
 Interrupts
 The interrupts refer to a notification &
communicated to the processor/controller,
by a hardware device or software, on receipt
of which processor/controller momentarily
stops and responds to the interrupt.
 Interrupts
 State of continuous monitoring is known as polling.
 In polling, the microprocessor/controller keeps on
checking the status of other devices; and while doing
so it does no other operation and consumes all its
processing time for monitoring.
 This problem can be addressed by using interrupts. In
interrupt method, the controller responds to only
when an interruption occurs. Thus in interrupt
method, processor/controller is not required to
regularly monitor the status (flags, signals etc.) of
interfaced and inbuilt devices.
 Introduction to Interrupts
 To understand the difference better, consider the
following. The polling method is very much similar
to a salesperson. The salesman goes door-to-door
requesting to buy its product or service. Like
controller keeps monitoring the flags or signals one
by one for all devices and caters to whichever needs
its service. Interrupt, on the other hand, is very
similar to a shopkeeper. Whosoever needs a service
or product goes to him and apprises him of his/her
needs. In our case, when the flags or signals are
received, they notify the controller that they need
its service.
Interrupts:
•An interrupt is used to cause a temporary halt in the
execution of program.
•The meaning of ‘interrupts’ is to break the sequence of
operation. While the CPU is executing a program, an
‘interrupt’ breaks the normal sequence of execution of
instructions, diverts its execution to some other program
called Interrupt Service Routine (ISR).
•After executing ISR, IRET returns the control back again to
the main program.
•Interrupt processing is an alternative to polling.
Need for Interrupt:
•Interrupts are particularly useful when interfacing I/O
devices, that provide or require data at relatively low data
transfer rate.
 Sources of Interrupts
 An external signal applied to NMI or INTR
input pin (hardware interrupt).
 Execution of Interrupt instruction
(software interrupt).
 Interrupt raised due to some error
condition produced in 8086 instruction
execution process (divide by zero, overflow
errors etc).
 Interrupts

Hardware interrupts Software interrupts

Interrupts due to error conditions:
NMI INT 21h
TYPE 0(divide by zero) etc
INTR INT 3h etc

Main Program Main Program Main Program Main Program

Printer Interrupt Modem Interrupt Modem Interrupt

When an interrupt is raised, the following INTERRUPT
RESPONSE takes place:
1. Push Flag register into stack and decrement stack
pointer by 2.
2. INTR pin is disabled by clearing the interrupt flag
(IF) in flag register.
3. Trap flag (TF) will be reset in flag register.
4. Pushes the current Code segment register(CS) into
stack and stack pointer is decremented by 2
5. Pushes the current instruction pointer (IP) into
stack and stack pointer is decremented by 2.
6. Fetching the address of ISR is done and goes to that
address, executes ISR of that particular interrupt.
Interrupt Response
 BASIC INTERRUPT TERMINOLOGY
•Interrupt pins: Set of pins used in hardware interrupts
•Interrupt Service Routine (ISR) or Interrupt handler: code
used for handling a specific interrupt
•Interrupt priority: In systems with more than one interrupt
inputs, some interrupts have a higher priority than other.
They are serviced first if multiple interrupts are triggered
simultaneously
•Interrupt vector: Code loaded on the bus by the
interrupting device that contains the Address (segment and
offset) of specific interrupt service routine
•Interrupt Masking: Ignoring (disabling) an interrupt
•Non-Maskable Interrupt: Interrupt that cannot be ignored
(power-down)
Interrupt processing flow
Main program

Interrupt N
Req

Accept N
Interrupt

Get interrupt
vector

Jump to ISR
Save PC

Load PC
 Interrupt Vector or Interrupt pointer
 Each Interrupt service procedure (ISR) will have a 4
byte physical address(CS+IP)
 Each ISR(Interrupt Service Routine) should have 4
memory locations for giving the starting address of
ISR.
 Total 1 Kb memory is reserved in 8086 for interrupts.
So totally 256 interrupts are possible.
 The starting address of interrupt service procedure is
called as Interrupt Vector or Interrupt pointer.
 The 256 interrupts procedures can be stored in the
table known as Interrupt vector table or Interrupt
pointer table.
When an interrupt occurs (shown in above figure),
regardless of source, the 80x86 does the following:
1. The CPU pushes the flags register onto the
stack.
2. The CPU pushes a far return address (segment:
offset) onto the stack, segment value first.
3. The CPU determines the cause of the interrupt
(i.e., the interrupt number) and fetches the four
byte interrupt vector from address 0:vector*4.
4. The CPU transfers control to the routine
specified by the interrupt vector table entry.
 Hardware Interrupts – Interrupt pins and timing
 x86 Interrupt Pins
 INTR: Interrupt Request. Activated by a peripheral device to interrupt the processor.
 Level triggered. Activated with a logic 1.
 INTA: Interrupt Acknowledge. Activated by the processor to inform the interrupting device
the the interrupt request (INTR) is accepted.
 Level triggered. Activated with a logic 0.
 NMI: Non-Maskable Interrupt. Used for major system faults such as parity errors and power
failures.
 Edge triggered. Activated with a positive edge (0 to 1) transition.
 Must remain at logic 1, until it is accepted by the processor.
 Before the 0 to 1 transition, NMI must be at logic 0 for at least 2 clock cycles.
 No need for interrupt acknowledgement.

INTR

INTA΄

D7-D0 Vector
 The Intel x86 Vector Interrupts:- Protected
Mode (32-bit)
 In the 80386/80486/Pentium processors operating in the Protected Mode
(32-bit operation), the interrupt vector is a pointer to the Interrupt
Descriptor Table.
 The Interrupt Descriptor Table can be located anywhere in the memory.
 Its starting address is pointed by the Interrupt Descriptor Table
Register (IDTR).
 Each entry in the Interrupt Vector Table is 8 bytes long:
 Four bytes represent the 32-bit offset address, two the segment
selector and the rest information such as the privilege level.
 The first 32 vectors are reserved by Intel to be used by the processor.
 The vectors 33 to 255 are free to be used by the user.
7 Offset (A31 - A16) 6

The protected mode 5 PF 01110 00H 4

interrupt descriptor 3 Segment Selector 2
1 Offset (A15 - A0) 0
 Interrupt Vector Table – Real Mode (16-bit) Example
Using the Interrupt Vector Table shown below, determine the address
of the ISR of a device with interrupt vector 42H.
Answer: Address in table = 4 X 42H = 108H
(Multiply by 4 since each entry is 4 bytes)
Offset Low = [108] = 2A, Offset High = [109] = 33
Segment Low = [10A] = 3C,Segment High = [10B] = 4A
Address = 4A3C:332A = 4A3C0 + 332A = 4D6EAH
0 1 2 3 4 5 6 7 8 9 A B C D E F
00000 3C 22 10 38 6F 13 2C 2A 33 22 21 67 EE F1 32 25
00010 11 3C 32 88 90 16 44 32 14 30 42 58 30 36 34 66
......... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...
00100 4A 33 3C 4A AA 1A 1B A2 2A 33 3C 4A AA 1A 3E 77
00110 C1 58 4E C1 4F 11 66 F4 C5 58 4E 20 4F 11 F0 F4
......... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...
00250 00 10 10 20 3F 26 33 3C 20 26 20 C1 3F 10 28 32
00260 20 4E 00 10 50 88 22 38 10 5A 38 10 4C 55 14 54
......... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...
003E0 3A 10 45 2F 4E 33 6F 90 3A 44 37 43 3A 54 54 7F
003F0 22 3C 80 01 3C 4F 4E 88 22 3C 50 21 49 3F F4 65
The Intel x86 Interrupt Software Instructions
 All x86 processors provide the following instructions related to interrupts:
 INT nn: Interrupt. Run the ISR pointed by vector nn.
 INT 0 is reserved for the Divide Error
 INT 1 is reserved for Single Step operation
 INT 2 is reserved for the NMI pin
 INT 3 is reserved for setting a Breakpoint
 INT 4 is reserved for Overflow (Same as the INTO (Interrupt on overflow)
instruction.
 CLI: Clear Interrupt Flag. IF is set to 0, thus interrupts are disabled.
 STI: Set Interrupt Flag. IF is set to 1, thus interrupts are enabled.
 IRET: Return from interrupt. This is the last instruction in the ISR (Real
Mode only). It pops from the stack the Flag register, the IP and the CS.
 After returning from an ISR the interrupts are enabled, since the initial
value of the flag register is poped from the stack.
 IRETD: Return from interrupt. This is the last instruction in the ISR
(Protected Mode only). It pops from the stack the Flag register, the EIP and
the CS.
 8086 interrupt types
 Type 0 interrupt (DIVIDE BY ZERO INTERRUPT):
This interrupt occurs when a DIV operation or an IDIV
operation result is large to fit in a given
destination register .
When an type 0 interrupt is occurred, 8086 will do
the following things:
1. Pushes the flag register into stack
2. Resets interrupt flag(IF) and Trap Flag(TF)
3. Pushes the return address(CS,IP) on the stack
4. Gets the CS value for the start of interrupt service
procedure and also gets IP address.
CS-00002h, IP-00000h
Type 1 interrupt( Single step interrupt):
Single-Step Interrupt
•Useful in debugging
•To single step, Trap Flag (TF) should be set
•CPU automatically generates a type 1 interrupt after
executing each instruction if TF is set
•Type 1 ISR can be used to present the system state to
the user
When an type 1 interrupt is occurred, 8086 will do the
following things:
1. Pushes the flag register into stack
2. Resets interrupt flag(IF) and Trap Flag(TF)
3. Pushes the next instruction address(CS,IP) on the stack
4. Gets the CS value for the start of interrupt service
procedure and also gets IP address.
CS-00006h, IP-00004h
Type 2 interrupt (Non Maskable Interrupt):
•When NMI pin is high, 8086 will automatically do a type
2 interrupt.
When an type 2 interrupt is occurred, 8086 will do the
following things:
1. Pushes the flag register into stack
2. Resets interrupt flag(IF) and Trap Flag(TF)
3. Pushes the next instruction address(CS,IP) on the
stack
4. Gets the CS value for the start of interrupt service
procedure and also gets IP address.
CS-0000Ah, IP-00008h
Note: It is called as nonmaskable as this type 2 interrupt
can not be disabled by any program or instruction.
Type 3 interrupt (Breakpoint Interrupt):
•This type 3 interrupt is produced by execution of the INT
3 instruction. The main use of the type 3 interrupt is to
implement break point function in a system in the
process of debugging the program.
When an type 3 interrupt is occurred, 8086 will do the
following things:
1. Pushes the flag register into stack
2. Resets interrupt flag(IF) and Trap Flag(TF)
3. Pushes the next instruction address(CS,IP) on the
stack
4. Gets the CS value for the start of interrupt service
procedure and also gets IP address.
CS-0000Eh, IP-0000Ch
Type 4 interrupt(Overflow Interrupt):
•The 8086 overflow flag(OF) will be set if the signed result of an
arithmetic operation on two signed numbers is too large to be
represented in the destination register or memory location.
•There are two ways to detect and respond to an overflow error.
1. Put an Jump if Overflow instruction (JO) immediately after the
arithmetic instruction.
2. Put an Interrupt on Overflow instruction INTO immediately
after arithmetic instruction in the program.
When an type 4 interrupt is occurred, 8086 will do the following
things:
1. Pushes the flag register into stack
2. Resets interrupt flag(IF) and Trap Flag(TF)
3. Pushes the next instruction address(CS,IP) on the stack
4. Gets the CS value for the start of interrupt service procedure
and also gets IP address.
CS-000012h, IP-00010h
 Priority of 8086 Interrupts

Interrupt Priority

Divide by zero error, INT n, INTO Highest priority

NMI Second highest priority

INTR Third Highest priority

Single step Lowest priority

•Interrupt 0 -- Divide Overflow: generated when a DIV or IDIV operation produces
an overflow. The interrupt 0 routine displays the message "DIVIDE OVERFLOW" and
returns control to DOS.
•Interrupt 1 -- Single Step: generated when the TF is set.
•Interrupt 2 -- Nonmaskable Interrupt: cannot be masked out by clearing the IF. The
IBM PC uses this interrupt to signal memory and I/O parity errors that indicate bad
chips.
•Interrupt 3 -- Breakpoint: used by debuggers to set up breakpoints.
•Interrupt 4 -- Overflow: generated by the instruction INTO (interrupt if overflow)
when OF is set. Programmers may write their own interrupt routine to handle
unexpected overflows.
•Interrupt 5 -- Print Screen: The BIOS interrupt 5 routine sends the video screen
information to the printer. An INT 5 instruction is generated by the keyboard
interrupt routine (INT 9) when the PrtScr key is pressed.
•Interrupts 6&7 are reserved by Intel
•Interrupt 8 -- Timer: A timer circuit generates an interrupt once every 54.92
milliseconds. The BIOS interrupt 8 routine services the timer circuit. It users the
timer signals to keep track of the time of day.
•Interrupt 9 -- Keyboard: generated by the keyboard whenever a key is pressed or
released.
•Interrupt E -- Diskette Error: The BIOS interrupt routine Eh handles diskette errors
The interrupt routines 10h - 1Fh are software interrupts which can be
called by application programs to perform various I/O operations and
status checking.
•Interrupt 10h -- Video: The BIOS interrupt 10h routine is the video driver.
•Interrupt 11h -- Equipment Check: returns the equipment configuration
of the particular PC.
•Interrupt 12h -- Memory Size: returns in AX the amount of conventional
memory.
•Example: Suppose a computer has 512KB of conventional memory. What
will be returned in AX if the instruction INT 12h is executed?
Sol.-: 512 = 200h, hence AX = 200h.
•Interrupt 13h -- Disk I/O: The BIOS interrupt 13h routine is the disk driver;
it allows application programs to do disk I/O.
•Interrupt 14h -- Communications: The communications driver that
interacts with the serial ports.
•Interrupt 15h -- Cassette: Used by the original PC for the cassette
interface.
•Interrupt 16h -- Keyboard: the keyboard driver.
•Interrupt 17h -- Printer I/O: the printer driver. supports 3 functions,
given by AH=0,1, or 2.
1. Function 0: writes character to the printer
2. Function 1: initializes a printer port
3. Function 2: gets printer status
•Interrupt 18h -- BASIC: transfers control to ROM BASIC.
•Interrupt 19h -- Bootstrap: reboots the system.
•Interrupt 1Ah -- Time of Day: allows a program to get and set the timer
tick count.
•Interrupt 1Bh -- Ctrl-Break: called by the INT 9 routine when Ctrl-Break
is pressed. The BIOS routine is a stub; it contains only an IRET
instruction. Users may write their own routines to handle the Ctrl-Break
key.
•Interrupt 1Ch -- Timer Tick: called by INT 8 each time the timer circuit
interrupts -- as in INT 1Bh, the routine is a stub.
•Interrupts 1Dh-1Fh: These interrupt vectors point to data instead of
instructions (video parameters, diskette parameters, and video graphics
characters, respectively).
DOS Interrupts
•The interrupt types 20h-3Fh are serviced by DOS routines that
provide high-level service to hardware as well as system
resources such as files and directories.
•The most useful is INT 21h, which provides many functions for
doing keyboard, video, and file operations.
DOS Interrupts 20h-27h
•Interrupt 20h -- Program Terminate: Terminates program, but
it is better to use INT 21h, function 4Ch.
•Interrupt 21h -- Function Request: Functions 0h-5Fh. These
functions may be classified as character I/O, file access, memory
management, disk access, networking, etc.
•Interrupt 22h-26h: These handle critical errors and direct disk
access.
•Interrupt 27h -- Terminate and Stay Resident: allows programs
to stay in memory after termination.
 Software Interrupt Applications

1.Interrupts are a commonly used technique

for computer multitasking, especially in real-time
computing. Such a system is said to be interrupt-driven.
2.Software interrupts can be used to insert break points
in debugging the programs.
3.Software interrupts can be used to test interrupt
procedure just by giving INT instruction with interrupt
type number.
4.Software interrupts can be used to perform I/O
operations or BIOS procedures can be done.
 8259A Priority Interrupt Controller (PIC)
Need of 8259A:
I/O devices require servicing in an efficient manner. The PIC
allows I/O devices to be serviced using the "interrupt" technique
rather than with a CPU "polling" technique.
How does 8259A PIC work ?
•The PIC receives an interrupt request from an I/O device and
tells the microprocessor.
•The CPU completes whatever instruction it is currently executing
and then fetches a new routine that will service the requesting
device.
•Once this peripheral service is completed, the CPU resumes
doing exactly what it was doing when the interrupt request
occurred.
•The PIC functions as an overall manager of hardware interrupt
requests in an interrupt driven system environment.
When an interrupt is raised, the 8259A PIC will do the following things:
1.The device requiring service signals the PIC via one of the eight PIC
interrupt request (IR) input lines. The corresponding bit in the PIC Interrupt
Request register (IRR) is set.
2.The PIC activates the INT line which is connected to the CPU INTR line.
3.If the interrupts are not masked at the CPU, it finishes the currently
executing instruction and sends one interrupt acknowledge (INTA) pulse to
the PIC.
4.In an X86 environment, the PIC responds by setting the highest priority In
Service Register (ISR) bit and the corresponding IRR bit is reset. There is no
PIC activity on the data bus in this cycle.
5.The CPU will initiate a second INTA pulse. During this pulse, the PIC
releases an 8-bit pointer(interrupt type number) on to the data bus where it
is read by the CPU.
6.The CPU reads the interrupt-type number, determines the associated
address of the interrupt service routine (ISR), then fetches and executes the
ISR.
7.In the Automatic End Of Interrupt (AEOI) Mode the ISR bit is reset at the
end of the second INTA pulse. Otherwise the ISR bit remains set until an
appropriate EOI command is issued at the end of the ISR.
8259A Block Diagram
8259A Pin Diagram
 Programming the PIC
• Initialization
• Operation
Initialization Command Words (ICWs) determine the basic
operating mode of the PIC. Two to four ICW bytes must be
used. The ICW inputs are timed by WR pulses. ICW1 and ICW2
must always be used. ICW3 and ICW4 are used only if they are
required by specifying so in ICW1. ICWs must be completed
before continuing on to the second type of command word.

Operation Command Words (OCWs) can be written into the

PIC anytime after the ICWs are written. There are three OCWs.
The OCWs customize the priority features and give the user
the ability to write/read various registers. The OCWs also tell
the PIC to operate in various interrupt modes.
ICW 1
ICW 2
ICW 3
ICW 4
OCW 1
OCW 2
OCW 3
 Modes of 8259A
•Fully nested mode:
This is a general purpose mode where all IR’s are arranged in
highest to lowest.IR0 highest and IR7 lowest.
•Special Fully Nested Mode
•Used in more complicated systems.
•Similar to, normal nested mode.
•When an interrupt request from a certain slave is in service, this
slave can further send requests to the master.
•The master interrupts the CPU only.
•Automatic rotation mode:
In this mode a device after being serviced receives the lowest
priority.
•Specific rotation mode:
In this user can select any IR for lowest priority thus fixing all
priorities.
•Special Mask Mode
When a mask bit is set in OCW, it inhibits further
interrupts at that level and enables interrupt from
other levels, which are not mastered.
•Poll command
•The INT output is neglected, though it functions
normally by not connecting INT output or by
masking INT input of the microprocessor.
•This mode is entered by setting p=1 in OCW3.
•A poll command may give more than 64 priority
levels.
Data transfer in microcomputer
Serial Transmission
 First, serial networks can be extended over long
distances at much less cost
 Second, using only one physical wire means that there is
never a timing problem caused by one wire being
slightly longer than another
Parallel Transmission
 High speed: it can send N bits at the same time
 A parallel interface can operate N times faster than
an equivalent serial interface
 Match to underlying hardware: Internally, computer
and communication hardware uses parallel circuitry
 A parallel interface matches the internal hardware
of computer as well
 Serial transmission types
 Asynchronous
 Each byte is encoded for transmission
 Start and stop bits
 No need for sender and receiver synchronization
 Synchronous
 Sender and receiver must synchronize
 Done in hardware using phase locked loops (PLLs)
 Block of data can be sent
 More efficient
 Less overhead than asynchronous transmission
 Expensive
 Asynchronous serial transmission
1. The sender and receiver are not Synchronised.
2. The sender sends only one character at a time.
3. Each character needs a start bit and a stop bit, parity bit.
4. Start is denoted by low signal(0V) and end is denoted by high signal (5v)
5. There can be idle time between each character.
6. It is a slow and inefficient method of data transmission.
7. It is an inexpensive method for low speed transmission.
8. Parity is used in Asynchronous transmission.
9. Detects any errors in each character being sent.
10. A bit in each byte is set aside as the parity bit.
11. In even parity, the bit is set to 1 or 0 to ensure an even number of 1’s.
12. In odd parity, the bit is set to 1 or 0 to ensure and odd number of 1’s.
13. The receiving system checks the system being used and the number of
1’s
 Synchronous transmission
 The senders and the receivers clocks are synchronised.
 The sender sends a packet of data at a time.
 Synchronisation is achieved by sending a ‘start’ frame and
a ‘stop’ frame.
 It is a more efficient method of transmission as only a start
and stop frame are required with up to 8Kb of data in the
packet of data.
 Asynchronous has a much higher overhead.

Data bit1
Data bit2 Data bit3 Data bit4 Data bit5 Data bit6 Data bit7 Data bit8 Sync1 Sync2

Synchronous Bit Format

A communications channel is classified as one of three types:
(depending on the direction of transfer)
To Interface microcomputer with serial data lines, the data
must be converted to and from serial form.
To do this, two registers are used.
1. Serial in parallel out shift register
2. Parallel in serial out shift register
Digital data transmission using modems and standard phone lines:
8251 USART ARCHITECTURE AND INTERFACING
PIN DIAGRAM OF 8251
Control Words
There are two types of control word.
1. Mode instruction (setting of function)
2. Command (setting of operation)
3.STATUS word
1) Mode Instruction
Mode instruction is used for setting the function of the 8251. Mode
instruction will be in "wait for write" at either internal reset or external
reset. That is, the writing of a control word after resetting will be
recognized as a "mode instruction."
Items set by mode instruction are as follows:
• Synchronous/asynchronous mode
• Stop bit length (asynchronous mode)
• Character length=08
• Parity bit
• Baud rate factor (asynchronous mode)
• Internal/external synchronization (synchronous mode)
• Number of synchronous characters (Synchronous mode)
2) Command word
 Command is used for setting the operation of the
8251. It is possible to write a command whenever
necessary after writing a mode instruction and sync
characters.
Items to be set by command are as follows:
 Transmit Enable/Disable
 Receive Enable/Disable
 DTR, RTS Output of data.
 Resetting of error flag.
 Sending to break characters
 Internal resetting
 Hunt mode (synchronous mode)
3) Status Word It is possible to see the internal status of the 8251
by reading a status word. The bit configuration of status word
PROCEDURE FOR SENDING AND RECEIVING CHARACTERS using USART:
Data characters can be sent to and read from the 8251 on:
 Interrupt basis
 Polled basis
To send data on interrupt basis:
1. TxRDY pin of the 8251A is connected to an interrupt input of 8259A
2. The transmitter should be enabled
3. When CTS pin is low and 8251A buffer is ready for a character, TxRDY
pin will go high
4. 8259A, interrupt path should be enabled .
5. The processor goes to interrupt service procedure which writes data
character to 8251A .
6. TxRDY should reset until buffer is ready for receiving another
character.
7. Counter should be maintained for keeping track of how many
characters have been sent.
To receive data on interrupt basis:
1. RxRDY pin of the 8251A is connected to an interrupt input of
8259A
2. The receiver should be enabled
3. When 8251A buffer is ready to read a character, RxRDY pin
will go high
4. 8259A, interrupt path should be enabled .
5. The processor goes to interrupt service procedure which
reads data character.
6. RxRDY should reset until buffer is ready for another
character to be read.
7. Counter should be maintained for keeping track of how
many characters have been received.
To send and receive data on polled basis:
Program instructions should be written. The following are sequence of
instructions to be written for sending and receiving data on polled
method basis:
Asynchronous mode, even parity, 2 stop bits, 8 bit character, freq 160Khz and baud
of 10k. Write an ALP to transmit 100 bytes of data starting at location 2000:5000H
0FEH - mode word 11H control word
MOV AX, 2000H
MOV DS, AX
MOV SI, 5000H
MOV CL,64H
MOV AL, 0FEH
OUT 0FEH,AL
MOV AX,11H
OUT 0FEH,AL
WAIT: IN AL,OFEH
AND AL,01H
JZ WAIT
MOV AL,[SI]
OUT OFCH, AL
INC SI
DEC CL
JNZ WAIT
MOV AH, 4CH
INT 21H
ALP receive 100bytes and store at 3000:4000h
MOV AX,3000H
MOV DS, AX
MOV SI,4000H
MOV CL,64H
MOV AL,7EH
OUT 0FEH,AL
MOV AL,14H
OUT OFEH,AL
NXTBT: IN AL,OFEH
AND 38H
JZ READY
MOV AL,14H
OUT OFEH,AL
READY: IN AL,OFEH
AND 02H
JZ READY
IN AL, OFCH
MOV [SI], AL
INC SI
DEC CL
JNZ NXTBT
MOV AH, 4CH
INT 21H
 Serial communication data transmission
standards
The 3 standards we refer here are:

•RS232C[recommended standard 232 C version]

•RS423A[recommended standard 423 A version]

•RS422A[recommended standard 422 B version]

 RS 232C
SPECIFICATIONS
•Connection must be less than 50 feet.
•Data represented by voltages between +15v and -15v.
•25-pin connector, with specific signals such as data,
ground and control assigned to designated pins.
•Specifies transmission of characters between, e.g., a
terminal and a modem.
•Transmitter never leaves wire at 0v; when idle, transmitter
puts negative voltage on the wire.
TTL to RS-232
Connecting 2 - RS 232 compatible equipment:
Also called as NULL modem connection
RS232 Logic Waveform
Comparison of 3 standards: