SN54AHCT125, SN74AHCT125

QUADRUPLE BUS BUFFER GATES

WITH 3-STATE OUTPUTS
SCLS264O − DECEMBER 1995 − REVISED JULY 2003

D Inputs Are TTL-Voltage Compatible D ESD Protection Exceeds JESD 22

D Latch-Up Performance Exceeds 250 mA Per − 2000-V Human-Body Model (A114-A)
JESD 17 − 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)

SN54AHCT125 . . . J OR W PACKAGE SN74AHCT125 . . . RGY PACKAGE SN54AHCT125 . . . FK PACKAGE

SN74AHCT125 . . . D, DB, DGV, N, NS, (TOP VIEW) (TOP VIEW)
OR PW PACKAGE

1OE

4OE
1OE

VCC

VCC
NC
(TOP VIEW)

1A
1OE 1 14 VCC 1 14
3 2 1 20 19
1A 2 13 4OE 1Y 4 18 4A
1A 2 13 4OE
1Y 3 12 4A NC 5 17 NC
1Y 3 12 4A
2OE 4 11 4Y 2OE 6 16 4Y
2OE 4 11 4Y
5 10 2A 5 10 3OE NC 7 15 NC
2A 3OE
6 9 2Y 6 9 3A 2A 8 14 3OE
2Y 3A 9 10 11 12 13
7 8 7 8
GND 3Y

2Y

3Y
3A
GND
NC
3Y
GND
NC − No internal connection

description/ordering information
The ’AHCT125 devices are quadruple bus buffer gates featuring independent line drivers with 3-state outputs.
Each output is disabled when the associated output-enable (OE) input is high. When OE is low, the respective
gate passes the data from the A input to its Y output.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

ORDERING INFORMATION
ORDERABLE TOP-SIDE
TA PACKAGE†
PART NUMBER MARKING
QFN − RGY Tape and reel SN74AHCT125RGYR HB125
PDIP − N Tube SN74AHCT125N SN74AHCT125N
Tube SN74AHCT125D
SOIC − D AHCT125
Tape and reel SN74AHCT125DR
−40°C to 85°C SOP − NS Tape and reel SN74AHCT125NSR AHCT125
SSOP − DB Tape and reel SN74AHCT125DBR HB125
Tube SN74AHCT125PW
TSSOP − PW HB125
Tape and reel SN74AHCT125PWR
TVSOP − DGV Tape and reel SN74AHCT125DGVR HB125
CDIP − J Tube SNJ54AHCT125J SNJ54AHCT125J
−55°C
55 C to 125
125°C
C CFP − W Tube SNJ54AHCT125W SNJ54AHCT125W
LCCC − FK Tube SNJ54AHCT125FK SNJ54AHCT125FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Copyright © 2003, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments On products compliant to MIL-PRF-38535, all parameters are tested
standard warranty. Production processing does not necessarily include unless otherwise noted. On all other products, production
testing of all parameters. processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

SN54AHCT125, SN74AHCT125
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS264O − DECEMBER 1995 − REVISED JULY 2003

FUNCTION TABLE
(each buffer)
INPUTS OUTPUT
OE A Y
L H H
L L L
H X Z

logic diagram (positive logic)

1
1OE

2 3
1A 1Y

4
2OE

5 6
2A 2Y

10
3OE

9 8
3A 3Y

13
4OE

12 11
4A 4Y

Pin numbers shown are for the D, DB, DGV, J, N, NS, PW, RGY, and W packages.

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 SN54AHCT125, SN74AHCT125
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS264O − DECEMBER 1995 − REVISED JULY 2003

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
(see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
(see Note 2): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
(see Note 2): N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
(see Note 2): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
(see Note 2): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
(see Note 3): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3. The package thermal impedance is calculated in accordance with JESD 51-5.

recommended operating conditions (see Note 4)

SN54AHCT125 SN74AHCT125
UNIT
MIN MAX MIN MAX
VCC Supply voltage 4.5 5.5 4.5 5.5 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
VI Input voltage 0 5.5 0 5.5 V
VO Output voltage 0 VCC 0 VCC V
IOH High-level output current −8 −8 mA
IOL Low-level output current 8 8 mA
Δt/Δv Input transition rise or fall rate 20 20 ns/V
TA Operating free-air temperature −55 125 −40 85 °C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

SN54AHCT125, SN74AHCT125
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS264O − DECEMBER 1995 − REVISED JULY 2003

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
TA = 25°C SN54AHCT125 SN74AHCT125
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP MAX MIN MAX MIN MAX
IOH = −50 mA 4.4 4.5 4.4 4.4
VOH 45V
4.5 V
IOH = −8 mA 3.94 3.8 3.8
IOL = 50 mA 0.1 0.1 0.1
VOL 45V
4.5 V
IOL = 8 mA 0.36 0.44 0.44
II VI = 5.5 V or GND 0 V to 5.5 V ±0.1 ±1* ±1 mA
IOZ VO = VCC or GND 5.5 V ±0.25 ±2.5 ±2.5 mA
ICC VI = VCC or GND, IO = 0 5.5 V 2 20 20 mA
One input at 3.4 V,
ΔICC† 5.5 V 1.35 1.5 1.5 mA
Other inputs at VCC or GND
Ci VI = VCC or GND 5V 4 10 10 pF
Co VO = VCC or GND 5V 15 pF
* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
† This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or V .
CC

switching characteristics over recommended operating free-air temperature range,

VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
FROM TO LOAD TA = 25°C SN54AHCT125 SN74AHCT125
PARAMETER UNIT
(INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX
tPLH 3.8** 5.5** 1** 6.5** 1 6.5
A Y CL = 15 pF ns
tPHL 3.8** 5.5** 1** 6.5** 1 6.5
tPZH 3.6** 5.1** 1** 6** 1 6
OE Y CL = 15 pF ns
tPZL 3.6** 5.1** 1** 6** 1 6
tPHZ 4.6** 6.8** 1** 8** 1 8
OE Y CL = 15 pF ns
tPLZ 4.6** 6.8** 1** 8** 1 8
tPLH 5.3 7.5 1 8.5 1 8.5
A Y CL = 50 pF ns
tPHL 5.3 7.5 1 8.5 1 8.5
tPZH 5.1 7.1 1 8 1 8
OE Y CL = 50 pF ns
tPZL 5.1 7.1 1 8 1 8
tPHZ 6.1 8.8 1 10 1 10
OE Y CL = 50 pF ns
tPLZ 6.1 8.8 1 10 1 10
tsk(o) CL = 50 pF 1*** 1 ns
** On products compliant to MIL-PRF-38535, this parameter is not production tested.
*** On products compliant to MIL-PRF-38535, this parameter does not apply.

noise characteristics, VCC = 5 V, CL = 50 pF, TA = 25°C (see Note 5)

SN74AHCT125
PARAMETER UNIT
MIN MAX
VOL(P) Quiet output, maximum dynamic VOL 0.8 V
VOL(V) Quiet output, minimum dynamic VOL −0.8 V
VOH(V) Quiet output, minimum dynamic VOH 4.4 V
VIH(D) High-level dynamic input voltage 2 V
VIL(D) Low-level dynamic input voltage 0.8 V
NOTE 5: Characteristics are for surface-mount packages only.

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 SN54AHCT125, SN74AHCT125
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS
SCLS264O − DECEMBER 1995 − REVISED JULY 2003

operating characteristics, VCC = 5 V, TA = 25°C

PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance No load, f = 1 MHz 14 pF

PARAMETER MEASUREMENT INFORMATION

VCC
RL = 1 kΩ S1 Open
From Output Test From Output TEST S1
Under Test Point Under Test GND tPLH/tPHL Open
CL CL tPLZ/tPZL VCC
(see Note A) (see Note A) tPHZ/tPZH GND
Open Drain VCC

LOAD CIRCUIT FOR LOAD CIRCUIT FOR

TOTEM-POLE OUTPUTS 3-STATE AND OPEN-DRAIN OUTPUTS

3V
Timing Input 1.5 V
tw 0V
th
3V tsu
3V
Input 1.5 V 1.5 V
Data Input 1.5 V 1.5 V
0V 0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATION SETUP AND HOLD TIMES

3V 3V
Output
Input 1.5 V 1.5 V 1.5 V 1.5 V
Control
0V 0V

tPLH tPHL tPZL tPLZ

Output
VOH Waveform 1 ≈VCC
In-Phase 50% VCC 50% VCC 50% VCC
Output S1 at VCC VOL + 0.3 V
VOL (see Note B) VOL
tPHL tPLH tPZH tPHZ
Output
VOH VOH
Out-of-Phase Waveform 2 VOH − 0.3 V
50% VCC 50% VCC S1 at GND 50% VCC
Output
VOL (see Note B) ≈0 V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.

Figure 1. Load Circuit and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

 PACKAGE OPTION ADDENDUM

www.ti.com 10-Jun-2022

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

5962-9686901Q2A ACTIVE LCCC FK 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962- Samples
& Green 9686901Q2A
SNJ54AHCT
125FK
5962-9686901QCA ACTIVE CDIP J 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9686901QC Samples
& Green A
SNJ54AHCT125J
SN74AHCT125D ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AHCT125 Samples

SN74AHCT125DBR ACTIVE SSOP DB 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HB125 Samples

SN74AHCT125DG4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AHCT125 Samples

SN74AHCT125DGVR ACTIVE TVSOP DGV 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HB125 Samples

SN74AHCT125DR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 AHCT125 Samples

SN74AHCT125N ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 125 SN74AHCT125N Samples

SN74AHCT125NSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AHCT125 Samples

SN74AHCT125PW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HB125 Samples

SN74AHCT125PWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 HB125 Samples

SN74AHCT125PWRE4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HB125 Samples

SN74AHCT125PWRG4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HB125 Samples

SN74AHCT125RGYR ACTIVE VQFN RGY 14 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 HB125 Samples

SNJ54AHCT125FK ACTIVE LCCC FK 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962- Samples
& Green 9686901Q2A
SNJ54AHCT
125FK
SNJ54AHCT125J ACTIVE CDIP J 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9686901QC Samples
& Green A
SNJ54AHCT125J

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Jun-2022

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN54AHCT125, SN74AHCT125 :

• Catalog : SN74AHCT125
• Automotive : SN74AHCT125-Q1, SN74AHCT125-Q1
• Enhanced Product : SN74AHCT125-EP, SN74AHCT125-EP

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Jun-2022

• Military : SN54AHCT125

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
• Military - QML certified for Military and Defense Applications

Addendum-Page 3
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74AHCT125DBR SSOP DB 14 2000 330.0 16.4 8.35 6.6 2.4 12.0 16.0 Q1
SN74AHCT125DGVR TVSOP DGV 14 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1
SN74AHCT125DR SOIC D 14 2500 330.0 16.8 6.5 9.5 2.1 8.0 16.0 Q1
SN74AHCT125DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74AHCT125DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74AHCT125NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN74AHCT125PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74AHCT125PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74AHCT125PWRG4 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74AHCT125RGYR VQFN RGY 14 3000 330.0 12.4 3.75 3.75 1.15 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74AHCT125DBR SSOP DB 14 2000 356.0 356.0 35.0
SN74AHCT125DGVR TVSOP DGV 14 2000 356.0 356.0 35.0
SN74AHCT125DR SOIC D 14 2500 364.0 364.0 27.0
SN74AHCT125DR SOIC D 14 2500 356.0 356.0 35.0
SN74AHCT125DR SOIC D 14 2500 340.5 336.1 32.0
SN74AHCT125NSR SO NS 14 2000 356.0 356.0 35.0
SN74AHCT125PWR TSSOP PW 14 2000 364.0 364.0 27.0
SN74AHCT125PWR TSSOP PW 14 2000 356.0 356.0 35.0
SN74AHCT125PWRG4 TSSOP PW 14 2000 356.0 356.0 35.0
SN74AHCT125RGYR VQFN RGY 14 3000 356.0 356.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
5962-9686901Q2A FK LCCC 20 1 506.98 12.06 2030 NA
SN74AHCT125D D SOIC 14 50 506.6 8 3940 4.32
SN74AHCT125DG4 D SOIC 14 50 506.6 8 3940 4.32
SN74AHCT125N N PDIP 14 25 506 13.97 11230 4.32
SN74AHCT125N N PDIP 14 25 506 13.97 11230 4.32
SN74AHCT125PW PW TSSOP 14 90 530 10.2 3600 3.5
SNJ54AHCT125FK FK LCCC 20 1 506.98 12.06 2030 NA

Pack Materials-Page 3
 MECHANICAL DATA

MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000

DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE

24 PINS SHOWN

0,23
0,40 0,07 M
0,13
24 13

0,16 NOM
4,50 6,60
4,30 6,20

Gage Plane

0,25

0°–
8°
0,75
1 12
0,50
A

Seating Plane

0,15
1,20 MAX 0,08
0,05

PINS **
14 16 20 24 38 48 56
DIM

A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40

A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20

4073251/E 08/00

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 PACKAGE OUTLINE
J0014A SCALE 0.900
CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

PIN 1 ID A 4X .005 MIN

(OPTIONAL) [0.13] .015-.060 TYP
[0.38-1.52]

1
14
12X .100
[2.54] 14X .014-.026
14X .045-.065 [0.36-0.66]
[1.15-1.65]
.010 [0.25] C A B

.754-.785
[19.15-19.94]

7 8

B .245-.283 .2 MAX TYP .13 MIN TYP

[6.22-7.19] [5.08] [3.3]

C SEATING PLANE

.308-.314
[7.83-7.97]
AT GAGE PLANE

.015 GAGE PLANE

[0.38]

0 -15 14X .008-.014

TYP [0.2-0.36]

4214771/A 05/2017

NOTES:

1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.

www.ti.com
 EXAMPLE BOARD LAYOUT
J0014A CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

(.300 ) TYP
[7.62] SEE DETAIL B
SEE DETAIL A

1 14

12X (.100 )
[2.54]

SYMM

14X ( .039)
[1]

7 8

SYMM

LAND PATTERN EXAMPLE

NON-SOLDER MASK DEFINED
SCALE: 5X

.002 MAX (.063)

[0.05] [1.6]
ALL AROUND METAL
( .063)
SOLDER MASK [1.6]
OPENING

METAL

SOLDER MASK .002 MAX

(R.002 ) TYP [0.05]
OPENING
[0.05] ALL AROUND
DETAIL A DETAIL B
SCALE: 15X 13X, SCALE: 15X

4214771/A 05/2017

www.ti.com
 MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38
0,65 0,15 M
0,22
28 15

0,25
0,09
5,60 8,20
5,00 7,40

Gage Plane

1 14 0,25

A 0°–ā8° 0,95
0,55

Seating Plane

2,00 MAX 0,05 MIN 0,10

PINS **
14 16 20 24 28 30 38
DIM

A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90

A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150

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