ye my Out en Mern ony Organiaation 3 Thpuk-cutput” interface. provides q metnud for punstering information befroeey) internal storage, ema externa} To devices. Pferipherals connested fo 4 computer need spesied Commy nication \inka ter interfacing -them colt) the centred preceasing unit 2 The purpose of the Communicafioy link isto resdve the Aitterence Shed exist beroeen the cemte| compubey and eich Peripheral the mejuy difference cive. C DUE berveen Perigherd st 4. Perifherefs eve cleehomeshaniad end electromegenche Aevice and their manrier of operation is Aitevent from the operation S$ the cp end memay eahich ave efechonic device Therefore ,c4 conversion af Signed velueg May be required. 2. The dada trrnste vate of phesipherals ave uselly. slower than) the trnstey rete =P epy. end cons equentty. 4 synchronizaheg weeha nism may be needed, Te segvive. these differences , computer system includeg Specie} havdeoare components behwcen the cp ind peripherals te supervise cind Synchronize all] input eed outtut punstes. | | I f \ i > Thege Componenls ATE called interfuce. units thevefove “to lntevtase!) means 2 attic peo of mere Components or Systemy Via their -respethve interbuce points Fer daty exchange befuecy | them. 4 In addition, ecich device may have its ocon contrlley thet supervises the opevedio) rh the purtiadary meshanisea in the pesiphera}, Tp Bus end Trtettice Modules or Cownestivy vt To bus +e To Devices _Acide’ live Deda live. + To [exmtet Kine. | bus Precessoy” : a7 » Lo Lies interface. ae. | key bouvd ] Display 4 Here the processor has addvers line, data line and canta line. the form the ‘To bus. >The periphery device like keyhourd, display, printer an4 magnehe fepe cave connected fo the To bus throuzs Vo prterfece > To vrtevface decodes the addres and control signals received dem Te bug and forwards the decoded signal 4e the pevipheva| conteelier. . 4 Tris cjso wegponsble fir synehrnization of doty Pow and Supervising the dety trunsher behocey) the peripheral and Processoy 7 Every pesiphere| has ths own contrlley ‘may be in-built Ov edtuched sepavetely. Ati the pesipheral intevfaceg ave connected fo the processox” Anreugh Do bus: The processe¥ places the adarers oP the device. cohich IF counts to cCommyniate, The Le interfue consist af addres cleced ex” theak monitors the addres line. > ehen the imterdace sb q partaday device finds its oon device address on the addres line, a path is ojotivedtedHe Matped Ho i] J TE we doust count to weduce. If | the Memons address spare Memenp- Titel fees Address we aot a different te ada res Add re9s see space. copert from fof} mement ae [lt Space i which is ctie| Io cop Meme Pace Cid Co space. metped To technique. | Here the advantage is qyaijable. but new the ynemong Tetabed inshtehens dees neh cork. Hhesefore The proccss” ean only, use hig voode iP rt bas i speeja} imsmictions Por Ho qpelated operstins such qs Tle red, Ho worite. et Pal] memory eagrera space ts Mermeny meered To — a Proceasot provid | gpace. for memeng, Usuetty , processee provides 1e48 > Memen. amd Ho Shave the oy separed® ele 8 entire creldress SPACE ob ree and To devices. 3 Vsuadly , processoy provides move cradrers UNS for acoersing caress tings Per ciccessing TH? memenz therefor neve decoding || trove jose clenoding Is require) ig weauived. > Memon contr} signs eve used) ste contol signs areused fo conten reel and conte To |) Contol rexel and conte Tho aperedtims opera). Lo versus memont Bus cageg coith Tio as well as yemeyy. 4 precesse® communi 2 meme PHS hag ded Vines, dares lines cand wer} forthe contr] Hired. 2 Three Mays jo commynicate Processot bused with re Shine iio’ memoy and HeO Teo alifferent buseg cire used, one fov memory and othe | dor xe Memory buseg Separetes buseg Used fer ynemont_ and Tio. @) One common bus is used Loe memory end Yo but both Cmemory cind To) have separate Contra} lines. Cavnmor dete; cing addres buy for rmeray. amd Tp ie 8 Memory, and Xo having one commen bus end commer Contre] lineg Sepavete contro} ime for memory end Tp,| Contr] commend fo start the tepe, Then the processor” cheeks the stubis oP the Tape cvith the help oP the stabs Command. cohen jtis confirmed that the tape is in covvead | Pesition ci dats oudtrat command is cent by the processor. the micrface communicedeg With the tepe contrliex cmd the deta is foroarded +o the tape amd stores} on it. Dede input commens) THis exer opposite athe datt outtah | command Here interface Feceivea detet Ror the pesther| : nen the processot cheeks date line Chug), civeilabi ity colts etubisg command and shen cetivebs data inpuk the hein of deda on the deta line eohidh is command. The interface. places | gemt to the processoy. Lo Interfacing Techniques 3 Wp veceitss Meee lees There ave Teo interfacing techniques, + Memory. mapped Hd - Tho mapped Zo. Memon Mepped Te Tn hig technique the tet remeron address spaceis pastitioned and part of Memeny. uls space is deveted te To exadvessing. Aes Tote) 2 when “this technique, is used, 4 vernon anes geterence. instruction hed ceuses the olery to tobe Fetched from or strred cb addvers | Acldvers space specified cructe modticodly beesmeg an To instyction (f that addvess js mate the address rPan Ilo Addrese space. 3The ysue) memon, Teleded Imstyciong gyre used Poy Uo elected aperatiens. the spesia) To inshyctions ave net wequived.befscen the processoy cind the periphera} device. 4 The wemeining peripheral connected Te the processor” ere disabled) by thelr intehuce. [> Apter cchwedion =P commynieadion ped bebseen the procetew | cind pexiphera} device , the processor” semdg an To command Tr thee aa ne Centr TE meme been tHe febhve perphera}. > The interpretution SF the Tp command depends of periphera] setected by the processes. Types at Commands — D Centeol command : Activeds the pesiphere]| and tells the periphera) cohad late be done. Example: Keyboard may be inspucted te move the curser te left, delete the selected Matter, Copy the content ete. Each peripheral has 15 own distinguished sequence ah central commands according ‘fe its operating mode. The spesihe contr] command olepends on the peripheral intertuced ooith The Precegsoy. @ stars command : Ysed te test various stos condifis inne jaterface end The pexipherel - the Bxunyie: The processor MT acento chests the stats 7F peripheral before starting. qre dake Srangher- ; 3 During dedy pamsfers emross may occur end detected the interface. These ex vats Cetuse setting of bits ing stens reste cing the precessor weds the stutig register after cestn ime intervels- @ Oars oufpub command) Hh enable the vnterchince see reaper: ¢ Exanepie: “In case rf 4 nagnerte rept) the precesse® Sends 4_ Asynchronous Dect Transher ee a the interns] operedions ab cligite] systems ave saynebrerirend b ; Y means of cock signe). The CPU and an Tlo inkrface. are two independent aigits systems xt they beth shave common efock pefoeen them the det qranstey between them js sald te be tn most cases, the internal timing im one digited other, in thet exich Useg 145. alety trunstiy between) Synchronous. System is independent From rhe own private Clock, In that case, the jn Nabare. eda Frangber” insread of commen assist the dete spun shew deta asynehre neously. behweey} (Z) Handshake. -Fhem is asynchronous Tn asynehwonous 4 chock, conte} Signets ave used to Two methods ere used +o trunsfey wo independent Units (D sttbe Steobe Control Ly strobe conhe| asynchr contol line Cstebe) is atsed po inditete Ander has te occur: The stoke sign eithex the source oF degtnatiey unit. sry Source mitered deda trunskes In this the shebe signe] inform the destined) unit -Yrec the valid alate |s eqved|adble on the daby bus devon the gource Unit: neous dete granster , slogle- jo the other unit cohen the a) Tay be achvated by, Decty bus Shobe- block diageurs - The source Unie Aixst places phe ajeter on The cede bus. the abtivetea the shebe. prise. the shebe signed and Ath Source on the deka bus remap in eetive sre For a1 cuftiaent Hime +o ad\ow the ajegtmedion unit se ceceive The deta. After the dade from the opebe is \nactivetes, and the source wemoveg the clota bus. atten the destination UPik Uses the, faling edge oH. the strbe pulse Ay Punsher the contents of the dadef bus in+e one ob its interna) vegister. ' Dts Me vet eer —> i Timing cliagsim. En Destmetion initiates) alata tunster. in hig ceise The deatinetion unit ejctivateg the shrebe pulse, informing the Qource. Te provide fhe debs. Dada bus Source. Destine) | Unit Strobe unit lous Aiayern) The Sour. Unit iy response. Fo strobe places the valid dates on the dada bus, The ded is made cirvedileble For enough period fo cdino He destinatiog unit fo weeelve ib. The fury esige +P the strobe pulse cum be used agein to triggey cy deghnatiocn Deqistey- wie TO Cb) Timing liege. @ Handshakin4 . The disadvantage TP steobe method is thed the Source Unit initedes the trunsfer has no iter eohethes the deatinetiv Umir has ctchielly eyceepted the dety sent by id. Similarly |g destineHoy Unit bhed iniieda the trunrey has no idesconether the source unit has eal, Pleceal the ety | on -the bug. The handsheke Method aolves His problem. by introducing one Wore signs cadied acknowledge sigvel- The qeknowled ge. Signa} provides 4 Teply fe the umir thet jritiates The cleft bensder. 2 Deda votre Deca Accept} NG ~ Here Pq shows the deta transport using handshake Signe) oben jnitiedteol by Source unit. Here, the Source unit initiates he data tounster by placing she deta on the bus and enabling the Gedy valic} signal In creaponse fo this, The dahnehin anit ciccepts the datu and ifsendg dtu crcceptea C Acknowledge) aignad +o the Source unit. The Source Unik then dlisubles its daty Vette signa) eahich invalidates the cluty on the bus The destinate Unik then disables its der cicceptes) eigna} ane the system geeg inte its init} stege- Date bus [>| Source DeStinetion Um OnitReady Foy Dect Dede vou tof U | Peter bus Verte] Dedy > Here Hy shows the data teunstey using handshaking signe] cohen initiaked by cegtinehe) Unlk- Here the degtnetion unit. crorivelts ready for daky signed cohen itis ready Fe accept alata from Source unit, Dn Tesponse te that) Fhe Source unit places the deta on the bus and inte the deter veld signa. The eleshvedion unit Anen accepts the daty fevrn the glazes bus and disables phe wendy for data signal. Then the gource Unik Aisebles aode valid signal cand invalidates deby on ‘phe bus. As wregult The system goes into its initied stage. Advantage zh handshaking Signed {CD The hardshaleing provides high degree ah Meribiiky end weltabitiby beeayse the Successht completion whey dedy trnster relics on crctive purtidpation by both units. (®D The scheme cain use timeouh signed fe defeat emy problem in completion xP dada teunshr. Por example th one unit enables its handshaleing contre] signa} and jb the webin handsheding signal Aves not respond carthin <4 gaven Hime peated, the unit defeats in exraa cand cictivates timeout signa} fo Interrupt Processes: In weaponse, processor excites a Service routine Hed Ree propriate. ervey reteve cH. op “4Sevicl Deda Transter Perret\ey Beta Treneferr Tt drunster dectey one bik [> Th cen Trunswnit more. than one. eta Hme. dady bir aba time Lowey detu tunsfer rete] a Pusrey deta transfer vete 3 Needs move number ah eoives te | |p qeeds less number of | eoives fo Conneer devices 7 conneet Heviees in the systen, ‘| the system | os eh suited fox long dictmeg OTHE iarercommeation penat hy nerenses beeuuse fewes eoires ave. ak Aistanw increases. Shus not used as compared To 4 parelicll suitable For ony distance conmmunieahe bus Apgsynehron ots serie} Commun iced oy). Asynchronmug Serted Commyniadin Synchronous Serie] Communion 3 Pounsmiters and seceivens ave | ATrimemitices and Reeeivers nok synchronized by clock cre synchronized by eteds. pits of deta aire transmitted + Dede bits cire tenswaitted wrth ct constant west. synchronize tion af cdede a character may arrive ob ang sete) 5 charasteY is received at constr ot receives” vede. 4 Deda Jensher is chaver chy oviented > Dade Poan ghey tee place in blocle. I — Psynehtenous Communication Interface o - Jo implemen? Sexja} Communicster) in micro precessoe sgstem we weed basically hoo devices. © Paradted Pe serie] conver ey CD Sevied fo parvedie}aThe sigmifiemce oh FIFO buftey \s |, Ero buffer is | pot gives inet 1? 4 To Trangmit byte Fats ibis meceasamy to convert byte into eight sexed bits . this can be alone by using the peralle Similar ab the veception thee semef bits ie serie} convester. 4 must be converted inte eardle) K-bib eta. ‘The semed be Pearedte] converted is used fo convert seoial daa bits ive the | pavalich eda. 3 The device designe) fe this Asynchreneus Receiver Transmitter CUABRT) , The device. cohich pravieles Synchrmous as well 4s asynchronous Apsumsmission purpose. are eaiieal Dniversel and weceptioy) are cotled 4s universe] sy nehvenous | casynchvenous wecejver~ spans HEY (OSART). Exes In - Pivsh- Oud ¢PEEO) Bult hate itis memeng umaih in conich ‘first inpub deta Cehaructet) is the Pingh orp ett Cohara cer) - 9 yoo units. A source, Unit placed befwee dag festinedion unit thet FIFO putter cm ereceives outro from The eIFo buffer: Actvertage oP ero hatter them weceve. The impel eb cestuin data punghyr rete and cain outpuk freak a different Prmshy were ro brejned From FTF buffer jg always im the ed of the input Fed toit fuster outpah dats Sam > Th can medeh slower inpub aleta coith y were end vise versa. Thus, prefered in the copplicohions phere csynchvonadsS data trnsfy Is used.Moda of Transtey Oo Progeermmed Do 3 To operetton cili meen q daly chunsfeY befweer) an To device. amd memo oy bebocen qn Tle device and the proceascy: > Tein any computer system To pperetions ore Completely contmied boy the precessoa’ then the system ty said to be using \ programmed To! 3 cohen sucha technique is used, processor enccubeg pregrerms shat imitates, diveer and ferminate the To sperahing ‘metuding Sensing device stubs, sendmg of peu) of cori. commana cing trunsfearing the deity. chee the. » His the responsiblity of the processes to period icalt telus athe Ho sysiem uml it finds thet the operating bo Complert- Sturt Ho Touma. Gter Do porta Stahis weyisteExam ple ~The processors ceftware cheeks eetch oF the To devices eve co bten. During this cheek, the processor” tests te see if cmy eviee. needs sewvicing above Hg shows flowchart fortis > The ecbove. ftrchayt cahich services ITo ports Aemd B- The. woutine cheeks fhe stebis of IJo ports in proper sequence. wo TH the veyuest bit js seb the Corresponding sexvice Souhine is catied to complete the To Tequest- 4 This test end Service procedure. continues until ed) the To post stots weqisters ve tested and 44) The To ports sequeating cenyice qire Sexvicedl. Once this is Aone, the procescoa” continued +o execute the norme} preganms 4 The woutine assigns patovities te the different “Ho devices. Oree. the routine is gturted . the service Tequeat bit at port fris adways cheaked first. once port A is checked , prt is cheeked and nen port C. However, the order Carn be changed by sioply chemging Phe woutine amd thus the poionties. © Tntesrupt -Lritiefed TO —————aaaeo 1 Somehme is necessary to have the computor Crate matically epee oneoba collection of specied woulineg coheneves” cently) Cendihims exists esithin 4 Pregaum. ox the computcy Spi eL This necessary. “thee computer system should give weaponse. fo device. Sich cy Rey bourd ; Semsoy and othex components cohen they wequest for Seavice - ~ je Energy voyust cfu sy | pee Toterreph Acknwledgena J This method provides an extema} csynchroneys input Pret could form phe processeY hel Be it should complete the cohabeveyi ooThe interregis cohich can not be masked undes sotto Contr} ave culled Nen- maskeble joterrupts we Handing Multiple Pevices = To handie patois Prom multiple devices precescor” has to pesform folreving asks. - ith Beargm) i to me ae the device wequesting cin intesruph: as to obtain the stuctigg addres of Interrupt sexvice- youtine corresponds fo intavupk request. Because ) : : @ eet intevrupt request has its oon intevuph Seavice weufine o Tt has to ediow the device +2 Mtevuph ahile cincthey intevrupl Is being Sexviced+ @ tb hes te eke decision Hhet cohich mtamyt should be serviced first cohen there ove simultuneous interwph vequetts From we Aifferent devices. 2 tn modem processors Ssh capabilites cre implemented by using + Veetored Interrupts > Dnterruph Nesting m Detevuph Priority. Veotered Teotertepls jeterrupts The a cohen The etterne] device jo excanbe, MacrreP processed Cinterreet pea wert) , precessey” has yp service voutine for servicing ned jntertuph. > th the interned cant) cicada ah the precessey produces 4 cate tb a predetermin oy which is The sorting adress ok yaier \s colted eater address and such parertuph are seer orf \ocati cuph Sexvice oupme Then thet Adres Corled veer intersupts -Jmstuetion that is cuvventty being executed cing fetch o new cyoutine C Dntercupt Service Routiwe) thed wil] sewvice the requesting device 3 After this servicing Ys completed, the prowasoy wood xvegume. enadty ashore i lee eff. the event that corses the internephi) is Canled interrupt and “the speela) weutine executed Js service the \ntervupt is codied Botertupt Sewvice Rowhne (Tse). 2 the interrupt Service Toutine iis different from subsoutine becuse. dre addvas of TsRis predefined ov ipis eveilable 10 Tnievuph Vester Table CEVL) cohereas Subroutine cidasers is neceasczily to be. gaven Wy Subroutine. CALL inshudion- 5 SRET insPicdion is used to vehi from Ish @hereds RET Tngbucion) ig used Po web From) swoveuhine « 4 EReT instruction westores frag. contents dong oith CS Code. Segment) emd IP CInsbyction Polnted) hewever RET instuctieg only estore CS end IP contents. a fr interrupt cetsed by orm externa] signal 1s referred f° 45 a hardaure inter repk- > Conditione) orerupts or Intervupts cerusedl by cpeelad Msrctioas crre coiled sottoure intorupts . Enabling and Disabling Dnterrupls caer coeaqns ave ence and cena ure prep control. by setting oF seating partiodar Pip fps in the precesser. 4 Enterrupts com be yoasked or unmasked wespectivls 5 cohen masked, processor dees Tok weatend fo the intoruph even rough Ane interrupt is eactiveted . Most of the Preceasots provide masking facili “1 Dn the precescoY Those micrsupts cobich cum be racked under sobpeure Conte) cre colle) maskeble interrupts.: in ; a vector raserrupts Fastest ead most exible reg ponse 1S obtednes| Since. Such cin imterrUPT conse. direeh hardoae Jyaglemented chransite 5 ~ ‘ " sition $e the carveeh internept= handling Prepem This technique is codied veotoring. > cohen processes is yotermupted , jb rends the veetr dd ras cand jeads if Into the PC: > there ave foo ways to support veety Interruphs. © Fixed veotr ciddlress ° Programmable vespr address. ~) The processoy conch supperk fired veeror aiddvets exppreah have defeuth yeoty odd ress doe exch interruph. The is uddresa. Programe can nok change +h prrogzarnmneble- yeator address 2. The processor onich supports capereach nein he Jubie io memory cotied the memgt veetor juble. . 4 The Trtarupr yeetor Jocehing cahich holds the veabr addresses ob interrepts Qupported by jhe prowesso™ > .Qohen intesreph ocers the veetr addres given in the interuph vearr -feble- cand proceed for execution af intorupt sevvice youline. ae The progey mess are ei owed $e change the veety Cyd dreaseg ered in the jntereph veer fuble hus the speble. CEVT) is an errvey of memory processot weds corresponding cuppreach is Known 4S prog mimyacble. veer odlress - Trteuph eating For some. dewieee 4 Ven Adag responding fe an initrapr wequesh may couse esrer if she operon ofComputer. Such interrupts qve tebe wo el goal end : Services even thaugh Precesgax is executing an Jntenuet service. Toutine. ter another device. aA system rh jaterrepts hed alles om intemyph service weutine +> be interuphed 3s nevon ag nesped Jntewupts . 4 Fer exemple o compidte het keeps x drerefe of the Hime of dey using weed Pre aloe. this veel Hme Clock weayests te the processor at vegulur Interveds Cand Processor Citeevdingty updates the. count of seronds, minutes cand heurs of fhe day. Per the proper” operaher Such an intewnph request Prom gee) dime clock must be. Precessex| vemen thigh computer 1S executing cin interruph sewice. fr anether device. Programmed To Interrupt dciven To. 4a Tn Programmed Lo 7D Externe] asynchroous \nped Frocescom hes to cheek eich is used + beh the processes theft To device in sequence. eine In effeck lack! each oneib i+ needs communtete with dre precessoy, This cheekin. 1S etehieved by Contin usy To device needs jie sewice and hence processoa” does not hee. +> cneele cohethes” Tlo device needs ib service or nop. feliing evde. und hence. processor” Coin net execute other insPyenons 397 Soa yenee ; 4.Puring polling processor Tn jadarupt deiven To is busy cine} trevefore have| The Processor \s adleweel FO Serius and cjecrement| execute HS sich 1M sequence.Peer on sysiem Hreughput | cind only step Jo service To | device, cohen i is jeld te doso by the adewice irseff. this increase : sysiem through ph fo This inplemente| ithouk — 9 This implemented using inteyngt hardaare Supp. interrepk havdware suppert. 4 Entessuph mush be enabled 4 If does nor depend upen sersupt cfviven To, poterrapt otedys- pe proces a initidizehin lo ct eed jnitistinedio af stad. |, I doce not need ot stack. | 9 System throughput decrease as) > Syste Yor sugh pub coed 0h number of Lip devices connected | depend on number of To device im the system ncrenseg. Canneated in the syst. Tn texrep Poierthy beohen intermph resuesh ctovived fam Yoo of more Avice the proceacey has fo deelde which requesh Simul ta neous ts 4 ve serviced firgk and ehich one Sheuld be delayed. she or qekes the decision ith the help oP jngesrupt The process primities. IF cceepts the wequelr having Pre highah perrihy. idenrity she. inesrep ting, Aewice, pater jeen a Tn cose poling 4-0 iS crude medticodry assigned by the ordey in cohich Aw pores: —4 No further arrange ment the is yequired te aleemocdeareprocessoy. Mosk commen way yo conmeat re devices is to Aor a dealsy chen ee ghoon in the below figure ENTR Processot cNTh The ner wesuesr line CENTA) ig common to ath devices “ ane intestupt qclenswoledgemen F ine CENTA) is connecteal an ing aalsy chain fushien- 4 Tn dleisy- che fashion The signal is edlowed 40 prepegete Sevially through the device. -» cahen more than Ene device issue an” intertuph request, tne INTR Nine 1S cuchivede] eine} The processor” Tes ponds by setting the cour Nine. THS signed 18 received by clevice 1. Device 1 passes the signed Fe The device 2 only if it does vor wequire any service. tf clevice 1 requires service, fF blocks the NTA line cind pets its jdenhiPreahiem codeen phe aleda lines. Therefore jn laisg chain era ngemenb, the device thet is elechrically ajoseet Fo The preceasor has the highest priority. >: Beow tig ehows phe anetnes currangement Por hand fey peiemby intesrupts . Here deaice ive onganized jn groups ind each gooup is connected ota different pevnly Jevel. eaithin cy geoup device ave connected in gy Aaisy- chain.a Veetored Tatewtup Paivrity avbibredion reat Toressupt Resist Tatar ft Request| —> yines - -——t + “Scheme | Poiority Trtengt Hardware PendingaArboue fig shows widely used veotered intersupt scheme. > As shown in figure interrupt wequeat signalg eve abre} in the intertuph wegicter: The pregnimmable Intcrruph mass register is used to disable ang or od) of the inturnepr Tequest, gets, one input isthe borermpr wequeal exond input is The inverted Prom intesruph Masks Vines, Fer ang AND Signe) from intermph register ends ymask condition for the same jaterrupt wanyister, Ohen any interrupk fg masked C4) phe inpeb te PND gett is 2e70, hence. output goes 260. this mers ehen the corresponding iInforepr requat lineis disebled. cohen twhenarh request ig preseny ber Uunmuasleed jntesruph , thet is Fag info a Peionihg. emodes cohich produces the addrag which is Aner inserted inte yntereupt is smasked , progmem coum np) Supe Jer Del & | P2| Ps | viva lv Peioatty Encocle Toleloalo | ef cao : ofelo {|r afar tA priemy encoder ts an siete pA | enuder cjreih thot mendes [STS Tg | ae the priory frunchen- alate jole L . 7 Dn privity ender We | o [tj 2 elasa fa if tes or more inpub are oaPnie a) to pa | ! a equal fe 1 edthe came time pe o} @ bet ey tf , . - efelele] « she input having he highest 4 lo} eo 4 4 1 7 Peioriny. coll) tuke precedence. [4 jela fepatef a 4 Fig shows the pruth tebie | aje|jtj +z lays 1. ob Whit prinily encodes. ae |e peal a . al\ale; trata 7 4 Teble shows Da yoperwity | 4 ja o 4 Jo 2 highest prihy ane Da inet LIE [a taba ty with loweat prioaihy .wr cohen Da Inpud is high wegerveless of other inputs ourpeh is CY) Yes nn. 4 The dz has the neh prionhy thus cohen Dao and Dat wegerdless of other wo liwer privy inpub; output is 40. > The output for D1 is generated only ib higher priory inpeds ave. Q und ca on: <5 The oubrut V Ca vedi output indicator’) indices, one or move. of the inputs ave equed to 1: Th al) inputs ove 0) V is equed +2 O amd The othey two outputs CY and Ye) of the cyreaik ave not ysed- . Logic Diagaum Dy Pa > DoDyreoy mement Acces comm) The qranster rE deta betwee 4 fast storege device. | Such as ragmetie disk ena] YHemeny often linntedd by the sree Jot dhe cfu. Removing the cpu fom The pethamna lethny the peoiphere} dlevice, manage Yhe. ynemong. buses clivestty owl | improve. the speed of dmunstes this srunstes technique. is | cotied direat memory access COMA), mA runsfer, the cP is idle cand has no contro] of @ Dura he memo bysed 3 A DMA contelles teke over the Aivertty befeeen the To device 4 + Pe CPD may be placed in on jdie stare ing variety rp ways. one common method extensively. used in rnicroptecessoy 'S +o Alseble. the buseg Horeugh specie} canpo] siqneds- 4 The bus Tequest CBR) input is used by the. Dinfr conte ler” to wequest the cPV +e meting vish contro| of the Buseg. coher) nis input ts active, the CPU deominates Phe execution of fhe current insbuetion) ane places jhe address bus the dads bus, cand the read and conte lines inte ct high impedance state. buses Jo manage “the pun sfr 4} memory. 3 The om thet origineta the bus mpequeat can Now duke embo] ab the buses to conduc memont spunsters eolthout precessoe jnterve ation. hen the om Jesmmetss the jransfer, if Aisableg bus qounth qedey Cob} he bug sequatiine, The CPv Neebieg the of buseg, amd webrn +o its norma} 4 when the DMA -pukees Contre] Bu aivestty with the memory The pun, coays @® Burst transfer In DMA burst qranstes ci block sequence consisting pa numpes of memoy coords is trunskerved in 4 2perahon aP-busey cygiom. ih communicates ser canbe madein sewers]continues buxst while the DMA contrelies is master af memory buses. stig mode al Juniper is needed for fust devices Such eg THegaetic disks cohese dedy runsmissivg comnet bE | stereed or slowed down until an entire block is jrinaterred. | cote stealmg : Tt ellows dhe DMA canbe lies to frenshar one cede word ata Time, aiPper aohich ib mush rebom contre| of the buses +o the cPu. The cPU mer ely atelays ite operetion for memory. ayele qe allow fhe divah memo Do seunspor te one Ngtead! one memont ode. wah DEES Bus Tequat ——38 — > Addverg bus ero Dety bus Bus gout <——| 6G Rend @R\ ys covite DMA Contoliev pmA contwhes needs Ye user 4 Ilo device. In addin Wr q count ssegishey ond aset lhe Communicate with athe cpu an needlg can cicldress wegistey, 4 Wor ak. adarers lines. The adaras Tegister und adddrers lines are used for Aivect communication coitn the memory, The coord count eh coords -phef must be trunshem wweitty between the denice and circus oan inrcrface Fo register speeifig the number The cede tunsher May be done. a memory. under Control of the oma. 4 Hee below 44 Shows the block Alagzm of ex Tyrie PMA Conteher. The unit communicdes colth the C0 vie the date bus and conte| line.Ald yess bus FT er] b 6S Regiterselat: > | RS — | Conre| ishev __ bn reauest BMA Arckneledas. ithe ced has welinquished the bused and cefeo divest. cath the smemort by vesting the Inte e—| Doterpt mere + To Device 4 Here when BG1>1_ ahe omA can cornmun | sreahymg om adders be je cadavers bus ond och pers! Arn adarers registy, ste: +o specify. fhe deaived jncsemen RD oy OR conhe), 9 The Omer contoliey has theee Tes cy covrd Count B egishee and cq conte) 1H 4 The da Tees Tegsicr cones an cy TERS, The yA dregs Tegister is "t athe iS goansterved Po memMeny. ldg the number rh coords fe be Jocadivn iy vee odtes each coors] asthe ore count tegiskey he rungherred. This Tegister Is alecwemente hy one after each coord qounsher and internedly tested t= 2er0. , The conte] Tegistey specifies the mode of trensher.DAR Pransher a 25] Taterepe 8% ceo eweandovn access Be maemon, CRAM) Ro @R Addears 1 DIMA cickenesoledad DS y pirear Meme to lero coma) Feniphered cS connaner | OM sequate device. Bas Dros uph yee pevighered deuce sends a DMA weguest ,fhe OMA me informing the cpu te welingaish the 4 hen controls aachivetes the BR It buses. “the Cfo vesponds coith its Ber Nine infosming The pms hak its buses ave disabled. 5 when The pestpher] device Teceiveg a DMA ccknow ledge, +r inthe deca bus Chor coritt) or seceves 4 coved From puts a eoord fhe data bus Cher eread)). > For each cook thet {s pounsferred, caddeess Tegistey’ and decsements 1S courd count wegishy sh the eword count oes nok vesich 2ev0, the DMA ebrerks the. wequest line Coming Brom the the OMA inesements 745 pevipreral. rh the caore) countTegistes weuchea 2e¥0. “the DMA stops any furthes drunsfer and wemoves ifs bus Tequest. Th also ints thecfV rh the interrupt: cohen the cpu ds -the contgor of the word 2 nareetes thet” The meron unit phe communicahs is codied mein memond. . Devices that previ are cuted auxi bang ymemoy. a Memory Hiewarehy cpu Ke] he memory clireedty. ecoith the cpu | de backup strage- Mein Memon L 4 Mag netic. ) ropes ' 4 Avalon. | ) i ( Wen 2 ee ee ne ed memnent 2 The memer{ hierarchy system Consists af cal} storage device employed ing computes systkm fom the slow but high- cospacity, ox unti fiery ynemmony tog welatively Fuster mem meme. de ayy even smalley and faster cache memong. creceasivle by. cthe high speed processor. o Main Memont The main memory, isthe centr] untk in cy computed sgsiem-stris a reejetivel Jarge ane preqmms and det Aung +he com athe principal cbechnolegy Us semjcnduceyr intergrated 4) Tnreg rebed circa RAM oye rating mode, static 4% RAM ch | Stee 7 w The static RAM esseahelly. consict of interna} Hip Hops thet etote Tre bine jnfosmeho) the stored informatrey vem valid og long a8 power is epprree| po The unit. as > State RAM contune ess memen cells pet unt area. > Th has | ess accessg LIMO hence facter memort€3. 4 Refreshing Cire) by ig nek gequyred - ciscults - fest memong seq te store pubs operat). mein memort. is baged ern eal for ps are. avedledole in too possible aaynannc. Dynamre RAM. Dynan Ram gteres The yaformetin yn the form of char geh Pret are epptied to rhe copacias 4% by mes 2 The bine esecne che coeaatr provided inside ‘the chi cpunsise¥5- The stored charge on he compres ers tend f dischar; game and fre copadters must be coll wrecnarged by cefrashing mement wi pexbodt she Aynawnie amnemnen! gteahc RAM POO unit Aree fame is greahor thar THs ceces stare RAMS is required | } 2 Refreshing. ciscuits fo meinem cthe charge on the fee wniliseends coupeccitoas after every. Costis more Extra hurdoure is required to conte] wefreshing His weds jhe. System clestgn complicuped. Cost is less | | |3 stare RAM Is used fr | 5 Dynaraie mei RAM is used implemen tng the cache dor implementing the main memory memory. Sermicondudey feel only Memories ckoM) 3 THs nen-volanle yneanent jecun held defy even ip pews is duamed off 5 the inbrmeahn shved in Rom dees net change 4 Data is stered mde ag Rom anentbis ynanufact vee: prom C.Programam aol e- Read only memory) 4 The PROMS are one time prodaummalle. Once. preg mmm ea, the mfrmain stored 's geymanent eprom (_Evaseble Programmable Read only memory) | 9 be prog srrmmed by the uses cotth a special BPRoM ave come - EPROMS ca pregarmme: ' Hraweled= a The mrertant point jg Hhe we ee erase The steved dady in The the chip Te ott Vs quartz. cond oD Cum Eproms by expesing Vieled Nght Through dar 1S fe 20 minatts- 4 THis nob possible Ae evage setecHve | sarbrmeahion, che) erased the entire | jafermatinn is Jost J | 4 fhis chip com be wepreg marnmed: . 4 hig memonp 1S Tae guitebte fy produc devel freely | j akon! since this 4 ip pment projets and college Julbo re eA, | expres Ames. con ve peused Many EepRom C Electrically Evaseble firoqms mmeble Reel only Meme Seton ¢ Electraly Prasat, Regret Feed emi om) 3 EErReM allows Sel ecnive. erasing ab the vegisht Jeve) wether” ince the informaher cam be than erasing ai) whe informahn ho ced bu ueing Clechicd signals.2 the EEPReM memonp has 4 spesial chip erase mode by conic entve chil cem be evased. 3 CEPROMS cre most expensive Bootstrap Loader The compubey start up hitns on the campuder system and Imbaka the pregnim enecuneg af phe imibted progaum, > As the power is firmed on the program counter is seh to the frst address xP the bootstrap fecdey by the compute’ hardodve. + the. past ot opercuing System 15 loaded from the disk te main memonp by the bectsirap leader ind Huss the contml 1S green te Tne operating system thes the Com peta” is enable for general purpose Associedive. Memont_ he Hime. required fond an item stored m memento be yeauced considerably. if shred dada cm be identified fir access, by the content of the datq itself rethey than by an address. 2 A memeng unit exccassed by The content is cedied cin ergsociahive ymemory ow Content Add vesseble memory ce am). _ythis type ek memonp 15 accessed shmultyneously cand in parellel onthe basis st alata Content rather Than by “speeiPic. eva vt ox jocah'n 4 cohen q coord 19 avtten in cin associabve rnemor{ no cidd re, ig given). The memory is cupaple at finding em emphy unused Jocahim te stre the word. 4 eshen g courd io bh be read Few an etssoctabive meme spre content af coord or paatrf coord is specified, “The memory [vcates ad) aotds ahich match the specified eantent and marke them for reading. > An assectative. tmemong. is move eApensive than q random aecers memor4. because each cel] rust have stvrazps Capabilitycas cell as \ogic circuits fox metehing 11S content coth ay extemal qrrgument for this weason) asgocjuhve. memories cre used in appiicahey coheve the search time 1S very cmttieed cane} yoush be. ven shork Cache Meme “a af the eyehve peotens af the pregsam end dota cave. placed Ing fast small ynemonp the average memons access Hme enn be seduced. hus weducing The spore) exeruhen me of the. preg, such 4 fash smi nem on is weferced fo ag q cache memory >this placed betocen the chy end mein memont ~ The cache. memory access time. js feag than the access Hime of maly memory - ~. Th is the fustest Component in The wre mort. hieverrdny ~~ Tre findament} jen of cerche organization is hab by keeping she west foequentty crceeased iMshychons end daby inthe freak Cache memory . ~3 The basic operation af the cache is as follews. cohen the cry needs fo acess memory, the cache Is examined. ££ the coord is found inthe euche, It Is read fom the fart memory. af the Coord adereased by The CPU is not found in-the cache, the main me mony is cicceased “fo Bead the word. 2 The pesfermance wh cache meme is Frequent mesure im seams af 4 auantihy entied Hit vatio- | 4 conen the cpu refer to recmeny dats and 44 found in The | Cache ‘ig cabled hit. if pre data 1s nef found ibis cee} miss. | «the etic of the numbed of hits clivided by the feta cPU yeherences Chit Hmies) 16 the ik tofre mMacping 3 The transfer malin of data from main Trem en fo cache memong 1s referred Toas a mapping Process - “4y Three types op rmapring Proceduves ave of pracheal imicvest hen Considering the orgemization ob cache ynem ont « Assodative Mapping athe fastest and most frexible cache oxganizedio] used cm agsecah ve memory » The assoeiahive meme of the memory. qris any. data fom mein memory, a The fig shews -rree A CPO addtTes is placed m the. argument vregishey cpu aad 4 etoreg beth the addres amd daty perenits ony Jocution in cache to store coords presentty stored in the cache. TES [Aegement vegas K-Addrex—a}<— data —s 2090 3BuSD OL FFE GHO 2234s 1234 Qscodeahve memo 4 TE the ciddvets is found, the corresponding data is read cand cent te the CPU TE no match occurs, the main yrerneng is auesed son predate ~The. address — deta pay is The Cache Memon af the cache is must be altselaced fo 7 ome} net presentty. Cfissociedive Mapping. cache) and the is searched fy a smnedehing. Qddvess 0 cpungferrea| te the ccocfehve fay ,an cadres - ata ply eke goer fory palit tharis needed} in the cache.Direct Mapping sAscodedive memerith cire expensive compared fe wundom c1ccerd mement because. of. the added Joie. Ussogated with each cell. 3 The possibility of HsIQG oY Bendom accers memory. for the. cuche is investigated. The CPU adavers of IS bits is clivided inte two felde, The nine least significant bit conshihete the index freld ena -the wen ehning sin bit form the tag field Memory Mernoy caty Landex crdaros & caddies | TH 0000 1220 poo eortrl 2340 | Olooe 340 OVttT a4seo sae Ov 6410 02000 S6HO CH) Cache memory. o2ttH cio | Mein Meme ne ¢ of che. The. deat i the cyche- The i jeetten Fig shows the interne orgeni2 ey ve desta sane) 8 coset she cache is clivteraiminda i@ cont: SEE ae CPU generete, “the mement. Yeyuest- the jndes Fietd re i used for the addres te aiceers fre auche. The tag fel of the | PY addres is compare| with the tay daty read from “the cache TE the two tags match thereisa ht and desired gota in the Cuche- 4 of +hercis wo math, there isa wiss undthe vequive| dary 36 weed frm main memory - t 22 The disad vantage Of divet vnegping is thar the hit restio cay deep ib wo daki cohese addres have He same Index but Aitferent tugs ave accessed vepemtedly., > However” this possibility is minimized by The fuck the such daty ave weretvely bar epart in the addveas Tenge oxeavaple- “The daby ab ad4vers Os presenty gtwred in -pre euche Cindeg = 000, Tug =©0, dali = 1220), Suppese That he GU ned counts Paced the aaredaty od add rex, o2000, The inder caddverg is 000 but the addres tg IS 02, colic) does nob produce. a meth. thoehy the mein me mary ls acregsed| cand data SBtO is punsferre| to phe Cey, Th cache dake ck inclee ciddresg 000 is Then replaced coith a1 tag ot 02. and data of scpo Set - Associative. Megeing | 7 Disadvantage of direst rmepping 15 Shak tee defy cot the same indea in the address but ait Arfferenh Tag vetues cam nol wealtde In cache memory eb the same time a Ateid type eb cuche organization cited seb- associate ™mepring is an improvement oveY phe ctiveet mapping organization in thab each o Saat at cuche cum stort a0 of move undct He same index address ~> AM examele thg set—ascociahve cache organization fore ser size. af 2 is shown in fyure. Ooo Tnder Tag Dott Tag Ooty ay 34S0 oD SéfO O2. ohio od 234d AFFExich index addres rely te two daty eine phely cpscocieted tags La Herve dete spreq at aiddves oa}o0o and d2000 ae mein ynemory cave store} m coiche Temont. ad inde ciddread& 000+ DSimlarty the aby at ciddveas O2FF% and 00447 Ue steref In cache ot Iwoler epddvess 944 2 The hit yahoo aill improve as the sebsize increases becuuse more dak coith the same Index bub different tugs redid in cache owhen eg miss cecurs Ing seb-assodahve ceiche end the setis full ie is necessary to replace. 6ne of the tuy-data tem aith4 new value. the mest common replacement cdgon'thm used art: wenden replacement, Best-in Syst -owt CPTF) and least wecently used CLRDY Viataa Mernory Wievatehy. system, pregerms amd eaby aye first 3 Tn gq meme shred in cuaiiiany memory. ; i mony oS oy Patton af cs progmm or dled ave brought inte men memo sheg are needed by fhe CPV. Vidtuel memont 184 Concept used in some large compurey Systems Thar peamik the use¥ to censhueh peogmur aig though a lavge mmemary. SpHce were clrvejlable equal fo dhe Aetedihy of ch ugk Hern. memneny 4 Bach address Thetis weReverceed by the CPV groea Hereugh cm address mereing frm the So-cedied virbied addras PS errsicd addrad in mem memo 2 Varied rnemeny 1S used To give pregarmmer” he Musion The javge mem memny. even theagh opeledivel 4 gmel} memory. sqsrem) provides 4 mecha nisy By Arunslabing inte cayresk memonf locations- the compete Ahey have. & Cicely has 4 a i Vial memo Pree gencrateel ddregses4 This is done Agnamicel ty cohile progaums being executed In Pre. CPU. “The translation ox mepping is havelieal crude motion by the hervdwoave by meeins ob a wae ping tuble