VietNam National University

University of Engineering and Technology

EMBEDDED SYSTEM FUNDAMENTALS

(ELT3240, NHẬP MÔN HỆ THỐNG NHÚNG)

Dr. Nguyễn Kiêm Hùng

Email: kiemhung@vnu.edu.vn

Laboratory for Smart Integrated Systems

 Introduction to VietNam National University
Week
Embedded Systems 1-2
University of Engineering
Introduction to Cand Technology
Week
Languague 3

CPU: Week
ARM Cortex-M 4

Curriculum Memory
and Bus
Week
5-6

Path ARM-based Week

7
Embedded System

Embedded Software Week

8-9

Real-time Week
Operating systems 10-12

Interfacing Embedded Week

With Real-World 13-14

Project Week
Laboratory for Smart Integrated Systems 15
 Objectives

In this lecture you will be introduced to:

– Embedded system architecture and
components.
– Essential concepts of Bus, Memory

3
 Outline
• Busses.
– Basic Concepts
– DMA
– Arbitration
– Multilevel Bus Architectures
• Memory devices.
• Summary

5
 Communication Mechanism
 Computer system’s
components communicate
through an interconnection
network
 Provides the means for data
transfer and
exchange of status and
control information
 Interconnection network can
be:
– Direct connections.
– Shared bus
– Network-on-Chip

6
 A simple bus

• Wires:
– Uni-directional or bi-directional
– One thick line may represent multiple
wires rd'/wr
Processor Memory

• Bus enable
addr[0-11]
– Set of wires with a single function data[0-7]
• Address bus, data bus
– Or, entire collection of wires bus
bus structure

• Address, data and control

• Associated protocol: rules for
communication

7
 Ports

Processor rd'/wr Memory

port enable

addr[0-11]

data[0-7]

bus
• Conducting device on periphery
• Connects bus to processor or memory
• Often referred to as a pin
– Actual pins on periphery of IC package that plug into socket on printed-circuit board
– Sometimes metallic balls instead of pins
– Today, metal “pads” connecting processors and memories within single IC
• Single wire or set of wires with single function
– E.g., 12-wire address port

8
 BUS
• A bus is, at a minimum, a collection of wires but it
also defines a protocol by which the CPU, memory,
and devices communicate.
• The signals that make up the bus provide the
necessary communication: the data itself, addresses, a
clock, and some control signals.

9
 Microprocessor busses
The major components on a typical bus include:
• Clock provides
synchronization.
• R/W’ is true when
reading (R/W’ is
false when reading).
• Address is a-bit
bundle of address
lines.
• Data is n-bit bundle
of data lines.
• Data ready signals
when n-bit data is
ready. 10
 Timing Diagrams

• Most common method for describing a rd'/wr

communication protocol
enable
• Time proceeds to the right on x-axis
addr
• Control signal: low or high
– May be active low (e.g., go’, /go, nGo, data
or go_L)
tsetup
– Use terms assert (active) and deassert tread

– Asserting go’ means go=0 read protocol

• Data signal: not valid or valid
rd'/wr
• Protocol may have subprotocols
– Called bus cycle, e.g., read and write enable
– Each may be several clock cycles addr
• Read example
data
– rd’/wr set low,
tsetup twrite
– address placed on addr for at least tsetup
time before enable asserted, enable write protocol
triggers memory to place data on data
wires by time tread
12
 Basic protocol concepts

• Bus protocol determines how devices

communicate:
– when components on the bus can use certain
signals
– and what those signals mean
• Devices on the bus go through sequences of
states.
– Protocols are specified by state machines, one
state machine per actor in the protocol.
• May contain asynchronous logic behavior.

13
 Basic protocol concepts
• Actor: master initiates, servant (slave) respond
• Direction: sender, receiver
• Addresses: special kind of data
– Specifies a location in memory, a peripheral, or a register within a peripheral
• Time multiplexing
– Share a single set of wires for multiple pieces of data
– Saves wires at expense of time

Time-multiplexed data transfer

Master req Servant Master req Servant
data(15:0) data(15:0)
addr data addr data

mux demux mux demux

data(8) addr/data

req req
data 15:8 7:0 addr/data addr data

data serializing address/data muxing

14
Basic protocol concepts: control methods
Control methods are schemes for initiating and ending the transfer.

Master Servant Master req Servant

req

ack

data
data

req 1 3
req 1 3
ack 2 4
data 2 4
data
taccess

1. Master asserts req to receive data 1. Master asserts req to receive data
2. Servant puts data on bus within time taccess 2. Servant puts data on bus and asserts ack
3. Master receives data and deasserts req 3. Master receives data and deasserts req
4. Servant ready for next request 4. Servant ready for next request
Simple; Fixed timing More complex; Flexible timing
Slower when response time is known
Strobe protocol Handshake protocol

15
A strobe/handshake compromise

Master req Servant

wait

data

req 1 3 req 1 4
wait wait 2 3
data 2 4 data 5

taccess taccess
1. Master asserts req to receive data 1. Master asserts req to receive data
2. Servant puts data on bus within time taccess 2. Servant can't put data within taccess, asserts wait ack
(wait line is unused) 3. Servant puts data on bus and deasserts wait
3. Master receives data and deasserts req 4. Master receives data and deasserts req
4. Servant ready for next request 5. Servant ready for next request

Fast-response case Slow-response case

16
 QUIZ

Bus multiplexing?

data enable Enable

data
CPU Address/Data
Device
adrs
Adrs enable

21
 Bus multiplexing

data enable Enable

data
CPU
Device
adrs

adrs
Address
/Data Address Data

Adrs enable Adrs

Enable
Data
Enable

Adrs Address

Data Address Data

22
 Outline
• Busses.
– Basic Concepts
– DMA
– Arbitration
– Multilevel Bus Architectures
• Memory devices.
• Summary

23
 DMA
• Direct memory access (DMA) performs data transfers without
executing instructions.
– CPU sets up transfer.
– DMA controller performs read and write operations directly between
devices and memory.
• DMA controller is a separate unit.
– DMA controller can act as a bus master

24
 Bus mastership
• By default, CPU is bus master and initiates transfers.
• DMA must become bus master to perform its work.
– CPU can’t use bus while DMA operates.
• Bus mastership protocol:
– Two additional bus signals: Bus request and Bus grant.
– Control method: a four-cycle handshake

25
 DMA operation
• The CPU controls the DMA operation through registers in the DMA
controller:
– A starting address register specifies where the transfer is to begin.
– A target address register specifies where the data is transferred to.
– A length register specifies the number of words to be transferred.
– A status register allows the DMA controller to be operated by the CPU.
• The CPU initiates a DMA transfer by
– setting starting address and length registers and target address appropriately.
– Setting “start transfer” bit in DMA’s status register.
• Once DMA is bus master, it transfers automatically.
– May run continuously until complete.
– May use every nth bus cycle.

26
 Peripheral to memory transfer with DMA

0: initialization: P configure the DMA ctrl Program memory μP Data memory

registers 0x0000 0x0001
1(a): P is executing its main program.
No ISR needed!
1(b): P1 receives input data in a register System bus
with address 0x8000.
... Dack
Main program DMA ctrl P1
... Dreq
0x0001 ack
100: instruction PC 0x8000 req 0x8000
101: instruction
100

28
 Peripheral to memory transfer with DMA (cont’)

2: P1 asserts req to request servicing Program memory μP Data memory

by DMA ctrl. 0x0000 0x0001
No ISR needed!
3: DMA ctrl asserts Dreq to request System bus
control of system bus
... Dack
Main program DMA ctrl P1
... Dreq
100: instruction 1 0x0001 ack
PC 0x8000 req
101: instruction 0x8000
100 1

29
 Peripheral to memory transfer with DMA (cont’)

4: After executing instruction 100, P sees Program memory μP Data memory

Dreq asserted, releases the system bus, 0x0000 0x0001
asserts Dack, and resumes execution, P
No ISR needed!
stalls only if it needs the system bus to System bus
continue executing.
... 1
Dack DMA ctrl P1
Main program Dreq
... 0x0001 ack
100: instruction PC 0x8000 req 0x8000
101: instruction
100

30
 Peripheral to memory transfer with DMA (cont’)

5: DMA ctrl (a) asserts ack, (b) reads data Program memory μP Data memory
from 0x8000, and (c) writes that data to 0x0000 0x0001
0x0001.
No ISR needed!
System bus
(Meanwhile, processor still executing if not
stalled!)
... Dack
Main program DMA ctrl P1
... Dreq 1
0x0001 ack
100: instruction PC
101: instruction 0x8000 req 0x8000
100

31
 Peripheral to memory transfer with DMA (cont’)

6: DMA de-asserts Dreq and ack Program memory μP Data memory

completing the handshake with P1. 0x0000 0x0001
No ISR needed!
System bus

... Dack
Main program DMA ctrl P1
... Dreq 0
0 0x0001 ack
100: instruction PC 0x8000 req 0x8000
101: instruction
100

32
Bus transfer sequence diagram
What is the CPU doing during a DMA transfer?

33
 Concurrency in DMA operation
• Once DMA is bus master, it may
– Run continuously until complete.
– Use every nth bus cycle to prevent the CPU from idling for too long.

Scheduling for concurrency during DMA

34
 Outline
• Busses.
– Basic Concepts
– DMA
– Arbitration
– Multilevel Bus Architectures
• Memory devices.
• Summary

35
 Arbitration: Priority arbiter

• Consider the situation where multiple peripherals request service from

single resource (e.g., microprocessor, DMA controller) simultaneously -
which gets serviced first?
• Priority arbiter
– Single-purpose circuit
– Peripherals make requests to arbiter, arbiter makes requests to resource
– Arbiter connected to system bus for configuration only
Micro-
processor
System bus 7
Inta 5
Priority Peripheral Peripheral
Int arbiter 1 2
3
Ireq1 2 2
Iack1 6
Ireq2
Iack2

36
Arbitration using a priority arbiter

Micro-
processor
System bus 7
Inta 5
Priority Peripheral Peripheral
Int arbiter 1 2
3 2 2
Ireq1
Iack1 6
Ireq2
Iack2

1. Microprocessor is executing its program.

2. Peripheral1 needs servicing so asserts Ireq1. Peripheral2 also needs servicing so asserts Ireq2.
3. Priority arbiter sees at least one Ireq input asserted, so asserts Int.
4. Microprocessor stops executing its program and stores its state.
5. Microprocessor asserts Inta.
6. Priority arbiter asserts Iack1 to acknowledge Peripheral1.
7. Peripheral1 puts its interrupt address vector on the system bus
8. Microprocessor jumps to the address of ISR read from data bus, ISR executes and returns
(and completes handshake with arbiter).
9. Microprocessor resumes executing its program.
37
 Arbitration: Priority arbiter

• Types of priority
• Fixed priority
– each peripheral has unique rank
– highest rank chosen first with simultaneous requests
– preferred when clear difference in rank between peripherals
• Rotating priority (round-robin)
– priority changed based on history of servicing
– better distribution of servicing especially among peripherals
with similar priority demands

38
Arbitration: Daisy-chain arbitration

• Arbitration done by peripherals

– Built into peripheral or external logic added
• req input and ack output added to each peripheral
• Peripherals connected to each other in daisy-chain manner
– One peripheral connected to resource, all others connected “upstream”
– Peripheral’s req flows “downstream” to resource, resource’s ack flows
“upstream” to requesting peripheral
– Closest peripheral has highest priority
P
System bus

Peripheral1 Peripheral2
Inta
Ack_in Ack_out Ack_in Ack_out
Int Req_out Req_in Req_out Req_in 0

Daisy-chain aware peripherals

39
 Arbitration: Daisy-chain arbitration
• Pros/cons
– Easy to add/remove peripheral - no system redesign
needed
– Does not support rotating priority
– One broken peripheral can cause loss of access to other
peripherals
Micro-
P
processor System bus
System bus
Int
a Priority Periphera Periphera Peripheral1 Peripheral2
Int arbiter l1 l2 Inta
Ack_in Ack_out Ack_in Ack_ou
Ireq1 Int Req_o Req_i t
Req_ou Req_i 0
Iack1 ut n t n

Ireq2
Daisy-chain aware peripherals
Iack2

40
 Outline
• Busses.
– Basic Concepts
– DMA
– Arbitration
– Multilevel Bus Architectures
• Memory devices.
• Summary

41
 Multilevel bus architectures
• Don’t want one bus for all communication
– Peripherals do not need high-speed, processor-specific bus interface
• excess gates, power consumption, and cost; less portable
– Too many peripherals slows down bus
• Processor-local bus Micro- Cache Memory DMA
– High speed, wide, most frequent processor controller controller
communication
– Connects microprocessor, cache, memory
controllers, etc. Processor-local bus

• Peripheral bus Peripheral Peripheral Peripheral Bridge

– Lower speed, narrower, less frequent

communication
– Typically industry standard bus (ISA, PCI)
Peripheral bus
for portability
• Bridge
– Single-purpose circuit converts communication between busses
– The bridge allow the buses to operate independently, thereby providing some
parallelism in I/O operations
42
 Example: ARM AMBA bus
• Two varieties:
– AHB is high-performance.
– APB is lower-speed, lower
cost.
• AHB supports pipelining,
burst transfers, split
transactions, multiple bus
masters.
• All devices are slaves on
APB.

45
 Outline
• Busses.
• Memory devices.
• Summary

46