CHAPTER - 9 _VO SYSTEMS. a INTRODUCTION + An VO system is used to manage and contro! VO operations and I/O devices. + WO device technology exhibits two conflicting trends: ° Increasing, Standardization of software and hardware interfaces. * Increasing broad variety of 1/0 devices, * The device drivers provide a uniform device ~ access interface to the I/O subsystem. 93 VOHARDWARE UNOM—Apr'13 Marks $ Outline - + Polling * Handshaking Process * Interrupts * Interrupt Driven 1/0 Cycle + DMA ° Steps To Perform DMA Transfer 92.1 Common Concepts * Adevice communicates with the computer system by sending signals over a cable or through air. * The communication is done through a connection point called ‘Port’. * Ifone or more devices use a common set of wires, the connection is called a ‘Bus’. + In the given figure 9.1, PCI (Peripheral Component Interconnect) bus structure connects the processor. (@) Memory subsystem is connected to the fast devices and an expansion bus connects to slow devices — Keyboard, Serial and parallel port.92 12 Oyen sel oe ys are connected together on sey VG, ‘on four disks (b) In the upper right ern bi plugged {nto a SCSI controller, Computer System Inter : an operate a port, OA i ler is a collection aetectonies that ° e til bus op c) Acontroller 1s ‘special I/O instruct 7 (@) Thecommunication can ocert tnt ideas ton the transfer of a byte o" word toa" i + Daisy Chain . . it ce B, and'de «When device A has cable th PE ino dove eter re ‘ ‘ ice C ugs intoa port on putter. This ar pigs int doviee candgevion P a fs calied a ‘Daisy chain” * An I/O port consists of four registers: rz Contains bits that can be read by the host. (1) Status Registe start the col (2) Control Register: the host to sia TIANA Of ha mode of a device. t (3) Data (A) Data - Out Register: written by the host Can be written by sr; Read by the host to get the input. to send the output. +e Gs) \ SCSI bus monitor processor ;——_{ cache graphics bride Sairoler agememery |_T mmemery SCSI controller u PCI bus : IDE dick controler expansion bus interface keyboard @) & parallel ‘serial port port Figure 9.1 ypical PC bus structure 9.2.2 Polling + The host is said to be busy ~ wait > be busy — waiting or polling which i over and over ntl he sy bt besmes eons = OoP eines se id3 wo systems Handshaking Process + Handshaking-is the : . and @ controller. Complete protocol for interaction between the host e Assume that 2 bits a re use i = 1 relationship between the controlle 'd to coordinate the producer ~ consume! T and the host, Controller Indicates its state through the busy bit in the status register. Sets the busy bit when it is busy working. Clears the busy bit when itis ready to accept the next command. Host ¢ Signals its wishés via the command ~ ready bit in the command register- + Sets the command ~ ready bit when a command is available for the controller to execitte. +The steps to be, followed forthe interaction between the host and the controller by handshaking are: (1) The host repeatedly reads the busy bit until that bit becomes clear. 1. i —out (2) The host sets the write bit inthe command register and writes a byte into dats — OM register. (3) The host sets the command ready bit. (4) When the controller notices thatthe command ready bit is se, it sets the busy Bit P the (5) The controller reads the command register and sees the write command. It reads data out register and does the 1/O to that device. eT ‘i i ied (©) The controller clears the command ready bit to indicate that device 1/0 is complet and the busy bit is‘cleared to indicate that it is done. + Repeat the above steps for each byte. « Instep 1, the host is busy waiting or polling; that is it performs the loop by reading the status register again and again until the busy bit becomes cleat. 923 Interrupts + The hardware mechanism that enables a device to notify the CPU is called an Interrupt. Mechanism + The CPU hardware has a wire called the Interrupt Request Line. + ‘The CPU senses that line after executing every instruction, + When the CPU finds that a controller has made the signal on the interrupt request line, ‘the CPU jumps to the Interrupt handler routine.ee a i t perf )perating System an interrupt performs th, he aus of to the CPU to continug The Interrupt handler fins nt im interrupt ~ . e Inter are essing and executes OT the sate prior the intorrup! vaste PU —" device driver initiaies VO Le initiates VO. ! ing checks for CPU executing che spactions interrupts between ins! ee eT CPU receiving inerruPh transfers control © interrupt handler input ready, output ~gamplete, or error "generates interrupt signal 5 ee interrupt handler py dala, * retums from interrupt 6 PU resumes processing of interrupted task Figure 9.2 Interrupt Driven 1/0 Cycle Features of Interrupt — handling (1) The ability to defer interrupts handling during critical processing. (2) An efficient way to dispatch to the appropriate interrupt handler for a device with first polling all the devices to see which one raised the interrupt, (3) Use of Multilevel interrupts - the Operating system can distiriguish between high low priority interrupts and can respond with the appropriate degree of importance. Interrupt Request Lines + The CPU has two interrupt request lines: 2 Non — Maskable Interrupt: The interrupt line which is reserved for events! unrecoverable memory errors. © Maskable Interrupt: Recoverable and the CPU in oft Mask can be turned off in sti situations when the sequence of instructions is interrupted, The maskable ite" is used by device controllers to request service, ‘divide error debug exception ull interrupt breakpoint INTO-detected overtiow bound range exception invalid opcode | device not available double fault ‘coprocessor segment overrun (reserved) invalid task state segment ‘Segment not present stack fault general protection Page fault (lntel reserved, do not use) floating-point error ‘alignment check machine check {Intel reserved, do not use) maskable interrupts Figure 9.3 Intel Pentium Processor event vector table + The vector contains the memory addresses of specialized interrupt handlers. + Reduce the need for a single interrupt handler to search all possible interrupts to determine which one needs service. sources of t Memory Access UNOM—Apr’15 Marks 5 Ditect Memory Access ; + DMA is used to avoid programmed 1/O for large data movement. It requires pie controller and by passes CPU to transfer data directly between I/O device and memory: + Many computers avoid burdening the main CPU wit loading some of its work to s special purpose processor Controller. + To begin a DMA transfer © The host writes a DMA command block into memory. ith the programmed V/O by off called a Direct Memory Access © The block contains * A pointer to the source and destination of transfer. + Account of the number of bytes to be transferred. Handshaking Process + The handshaking between the DMA controller and the device controller is performed through a pair of wires called DMA — Request and DMA ~ Acknowledge.ESN TSS ‘Steps to perform DMA transfer . 9. Operadi ing System jon the DMA Request Wite hen signa! + The device controler places ® © is available for transfer. + This signal causes the DM! © Toseize the memory bus: address om ne DMA- AC ives the (A controller the memory — address wires, senowledge Wire. pMA~Acknowledge signal, * To place the desired © Toplace asignal ont + When the device controller rece! i nory: © Transfers the word of data (0 men + Removes the DMA ~Reques sign i Gd 1. device driver is to transfer disk data CPU to bulfer at address X B.DMAcontroller 2. davico driver iels transfers bytes to isk controller 10 bulfer X, increasing transfer C byles memory address” tem dsktobufer [cache and decreasing C at address X until = 0 6. when C = 0, DMA t interrupts CPU to signal | JOerPE transfer completion SaaS 3. disk controller initiates: IDE disk |, DMA transfer r contraer | 4, disk controller sends each byte to DMA controller Figure 9.4 Steps in a DMA transfer (1) Device driver is told to transfer disk data to buffer at address X. (2) Device driver tells disk controller to transfer C bytes from disk to buffer at adies x. i‘ 3 (3) Disk controller initiates DMA transfer. (4) Disk controller sends each byte to DMA controller. (5) DMA controller transfers bytes to buffer X, increasi é creasing C until C= 0. 7G rsa sary so (©) When C= 0, DMA interrupts CPU to signal transfer completion.oe sytems_ 82 , sharable or Dedicated «A sharable device - - can by dedicated device cannot, “S°4 Concurrently by several processes or threads: a Speed of operation « Device speeds range fro, M a few bytes . : « Read—write, read only, or write on Per second to a few gigabytes second. + Some devices perform direction. both input and output, but others support only one data 43 Bock and Character Devices lock device +The block ~ device interface : ing disk dri and other block ~erented deca al te espects necessary for accessing disk drives «Block devices include disk drives. Commands include o Read rf «Write + Seek + Rawl/O or file—system access * Mode of accessing a block device is as simple as accessing a linear array 0! + Memory mapped file access «Provides access to disk storage via an array of bytes in main memory. f blocks. character device ‘The character device is a device that is accessed through a character stream interface. + Includes keyboards and serial ports. 434 Network Devices + Most operating systems provide a network I/O interface that is different from the read ( ), write (), seek () interface used for disks. + An interface available in many operating systems is the network socket interface, * UNIX and Windows NT/2000 include socket interface. + Separates network protocol from network operation. ° * Includes select functionality. * Approaches vary widely —pipes, FIFOs, streams, queues and mailboxes.9. uO Sheree 93.5 Clocks and Timers Functions of clocks and timers socks and timers are: * The three basic fumetions provided bY hardware © Giving the current time. © Giving the elapsed time. ® Set a timer to trigger operation Xatti * These functions are used heavily by te ol applications. ime T. ae well as by ti erating systems, as Wel by time Seni, Programmable Interval Timer + The hardware to measure elapsed time interval timer. It is used for and trigger operations is called a Programm, © Timing Interrupt ‘ in + Set to wait a certain amount of time and then generate an interrupt, © Periodic Interrupt * Set to do this once or to repeat the pi he * On many computers, the interrupt rate generated by the hardware clock is between and 60 ticks per second. rocess to generate periodic interrupts, 9.3.6 Blocking and Non — Blocking /O UNOM—Nov'l3 Marty) Blocking VO + Process execution is suspended until 1/0 is completed. © Application is moved back to the wait queue to resume execution. + Easy to use and understand. + Insufficient for some needs. Non - Blocking /O | + 1/0 call returns as much as available. + User interface, data copy. + Implemented via multi threading. * Does not halt the execution of an application for an extended time. * Returns quickly with count of bytes read or written, | Example: . | © A user interface that receives keyboard and mouse input while processing an displaying data on the screen. * A video application that reads frames from a file on disk while simultaneously decompressing and displaying the output on the display, |r 0 reer spronous 1/0 ase 4 + Process TUNS While 1/9, executes, Difficult to use, ° » Vos ubsystem signals process When 1/0 is completed -ompleted. REVIEW QUESTIONS pifferentiate between Blocking 1/0, ‘and Non blocking 1/0. ing 1/0. UNOM -Nov’13 Marks 2 KERNEL /O SUBSYsTEy ~~ MSU~Aprit 09 Apriv'10 Nov'll Marks 06, Marks 12 Outline 7 UNOM -Nov'l4Apr'ss Marks 10 Services Related To » VO Scheduling ° Buffering Cache * — Spooling And Device Reservation Error Handling Kernel Data Structure + The kernel provides several services related to I/O. 441 VO Scheduling + Scheduling a set of /O request in a good order in which it executes. + Scheduling can improve the overall system performance by sharing device access among process and can reduce the average waiting time for the I/O to complete, © Suppose a disk arm is near the beginning of the disk and three application issues are’ done to that disk. (1) Request a block near the end of a disk. (2) Request a block near the beginning. (3) Request is in the middle of the disk. © The operating system can reduce the distance travelled by the disk or by serving the application in the order 2, 3, | $42 Buffering UNOM -Nov’12,Apr’15 Marks 2 * Amemory area that stores data while there are transfer between two devices or between a device and an application.12 Operating Sytem - XC reasons: © . match between the *. Buffering is done for th ’ (1) To cope up with the speed ™! data stream. joes that have different data mater Sizes, In Su, (2) Used to adapt between ale and reassem lin messag 8. buffers are used for fragin rates’ for application 1/0, i ort ‘Copy semal P ae (3) Use of buffering to su notte la writen to disk is a. With Copy semantics, the vel are ; ication system call. aversion at the time of the application sy* bs Independent of any changes nthe 2 2 943° Cache NE ies ot ies of.data access, + The Cache isa region of fast memary tht hold coPres “CT oxi * Accessing the cached copy is more efficient than access to iginal. + The difference between a buffer and a cache is that: / xecuting copy of a data item. * The Buffer may hold the ony € : +A Cache hold a copy on faster storage ofan item thats stored elsewhere, 9.4.4 Spooling & Device Reservation . * ASpool (Simultaneous Peripheral Operations Online) is a buffer that holds Output f, device like printer that can’t accept interleaved data streams. + The Operating system solves this problem by saving the application output ina separy disk file, ° When an application finishes printing, the spooling system queues are removed, 3 3 & $ 8 8s iB a 8 i lication buffer. ‘¢ Device Control Block y : * ADevice Control Block maintains the device characteristics and device description + When the parameters for a device are supplied, routine matches the parameters wit + DCB. 8 * The Data structure of BCB includes: * Device ID. ° Device status, * Device Characteristics. * Device descriptor, * List of processes waiting for a device, * The current processes using the device, 9.4.5 Error Handling +> An Operating system that uses protected m ' so hardware and application errors. lemory can guard against many kintwo systems 9-13 + Incase of a device failure, the fy (a) Sense Key: Identifies the go @) Additional Sense Code, g @) Additional Sense Coae g lowing information can be helpful: eral nature of failure. Pecifies the category of failure. ualifier: Gives more specific details about failure. “ Kernel Data Structure 4 roe As vartay °;alttin the state information about the use of VO components through a variety of 4 Connections’. “7! Sttuctures, such as the “Open File table’ and ‘Network «The Open File Table pie. Ope Contents points to function like Read, Write, and Close + Some use object — oriented Methods and message passing to implement 1/O. Review Questions aw Describe the components of Kerne] 1/0. subsystem, , MSU~Apr’09 Apr°10 Nov'ld Marks 6,12 UNOM ~ Apr 12 Nov'14 Apr’15 Nov'15 Marks 10 2) ‘What is buffering? ‘ UNOM —Apr’15 Nov’15 Marks 2 £9 Giveeny two reasons for buffering, UNOM —Nov’12 Marks 2 ( Compare a buffer witha cache, f UNOM —Apr’12 Marks 2 45 TRANSFORMING I/O REQUEST TO HARDWARE OPERATIONS UNOM - Nov'I4 , Nov’13 Marks 5 Outline iP + Steps To Transform I/O Request To Hardware Operations * Life Cycle OF An I/O Request + The steps to transform an I/O operation to Hardware operations which consumes a number of CPU cycles are as follows: (1) A process issues a blocking read ( ) system call to a file descriptor of a file that has been opened previously. (2) The system call in the kernel checks the parameter and if the data are available in cache: ‘Yes: The data is returned to the process and /O is completed. No: The process is removed from the running queue and places waiting queue for the Device. (3) Depending on the OS, the request is sent through the subroutine or via kernel message. (4) The device driver allocates kernel buffer space to receive the remaining -data and schedule 1/0,414 Op iting ‘System i ‘dware to perf (5) The device controller operates the device har Perform the day, through DMA. (6) The driver may poll the Stat generates an interrupt. (7) The interrupt handler receives | stores the data, signals the devi (8) When 1/0 request has been comple! process from waiting queue ; (9) Moving the process to the ready queue unblocks the processes, us and the transfer is managed by DMA cont rer, rupt through the Interrupt Veg inter an .d returns from interrupt, ‘ora ice driver an ted, the kernel transfer data an, dm VO completed, input ‘data available, oF output completed t Return from system call Request 10 User process ‘System call “Transfer data {ifappropriate) to process, return pletion or error code No ‘Send request to device driver, block process if Kemel ‘sppropriate WO subsystem Process request, issue Determine which YO ‘commands to controller, Devi completed, indicate state ‘configure controler to ane change to VO subsystem block until interrupted | Receive interrupt, store o data in device-driver Device-controller Interrant buffer ifs input, signal to amas a [sisi | 7 interrupt Devi 1 Monitor device, i ‘ntrrupt whea VO completed VP completed ‘enerate interrupt time Figure 9.6 Life Cycle of an /0 request Review Questions “| (1) How to transfer /O requests to hardware operations? UNOM —Nov’14, Nov'lS mars4 Operating System 11.73 Authentication Or Eneryption AlgOrHH™ + Symmetric Eneryption Algorithm © E(K) can be derived from D (0 © The secrecy of E (K) must be protected to the same extent as D (K), chnology (NIST) adopted a — Te © National Institute of Standards and Te ial Instit ryption Standard (AES) to plc eM, algorithm called Advances Encryption Standard (DES). * Asymmetric Encryption Algorithm © Itis infeasible to derive D (8) fo act as the public key. * D(K)is the private key: © RSA signature algorithm can in E (K), 80 E (K) need not be kept see Nd, i provide an asymmetric encryption algorithm ique 11.7.4 Properties Of Good Encryption Techni Je for authorized users to enc Pt de, + Agood encryption technique must be simp! data, f «The encryption scheme depends on a parameter called the encryption key, | + Must be extremely difficult for an intruder to determine the encryption key, Review Questions UNOM Apr’l4, Nov’15~ i PI lov'’15, Maris, (1) What is encryption? (2) Describe in detail about encryption. UNOM Apr’12, Nov'12— Maris; 0 UNOM Nov'15-Marig: (3) What are the components of an encryption algorithm?92 12 Oyen sel oe ys are connected together on sey VG, ‘on four disks (b) In the upper right ern bi plugged {nto a SCSI controller, Computer System Inter : an operate a port, OA i ler is a collection aetectonies that ° e til bus op c) Acontroller 1s ‘special I/O instruct 7 (@) Thecommunication can ocert tnt ideas ton the transfer of a byte o" word toa" i + Daisy Chain . . it ce B, and'de «When device A has cable th PE ino dove eter re ‘ ‘ ice C ugs intoa port on putter. This ar pigs int doviee candgevion P a fs calied a ‘Daisy chain” * An I/O port consists of four registers: rz Contains bits that can be read by the host. (1) Status Registe start the col (2) Control Register: the host to sia TIANA Of ha mode of a device. t (3) Data (A) Data - Out Register: written by the host Can be written by sr; Read by the host to get the input. to send the output. +e Gs) \ SCSI bus monitor processor ;——_{ cache graphics bride Sairoler agememery |_T mmemery SCSI controller u PCI bus : IDE dick controler expansion bus interface keyboard @) & parallel ‘serial port port Figure 9.1 ypical PC bus structure 9.2.2 Polling + The host is said to be busy ~ wait > be busy — waiting or polling which i over and over ntl he sy bt besmes eons = OoP eines se id3 wo systems Handshaking Process + Handshaking-is the : . and @ controller. Complete protocol for interaction between the host e Assume that 2 bits a re use i = 1 relationship between the controlle 'd to coordinate the producer ~ consume! T and the host, Controller Indicates its state through the busy bit in the status register. Sets the busy bit when it is busy working. Clears the busy bit when itis ready to accept the next command. Host ¢ Signals its wishés via the command ~ ready bit in the command register- + Sets the command ~ ready bit when a command is available for the controller to execitte. +The steps to be, followed forthe interaction between the host and the controller by handshaking are: (1) The host repeatedly reads the busy bit until that bit becomes clear. 1. i —out (2) The host sets the write bit inthe command register and writes a byte into dats — OM register. (3) The host sets the command ready bit. (4) When the controller notices thatthe command ready bit is se, it sets the busy Bit P the (5) The controller reads the command register and sees the write command. It reads data out register and does the 1/O to that device. eT ‘i i ied (©) The controller clears the command ready bit to indicate that device 1/0 is complet and the busy bit is‘cleared to indicate that it is done. + Repeat the above steps for each byte. « Instep 1, the host is busy waiting or polling; that is it performs the loop by reading the status register again and again until the busy bit becomes cleat. 923 Interrupts + The hardware mechanism that enables a device to notify the CPU is called an Interrupt. Mechanism + The CPU hardware has a wire called the Interrupt Request Line. + ‘The CPU senses that line after executing every instruction, + When the CPU finds that a controller has made the signal on the interrupt request line, ‘the CPU jumps to the Interrupt handler routine.ee a i t perf )perating System an interrupt performs th, he aus of to the CPU to continug The Interrupt handler fins nt im interrupt ~ . e Inter are essing and executes OT the sate prior the intorrup! vaste PU —" device driver initiaies VO Le initiates VO. ! ing checks for CPU executing che spactions interrupts between ins! ee eT CPU receiving inerruPh transfers control © interrupt handler input ready, output ~gamplete, or error "generates interrupt signal 5 ee interrupt handler py dala, * retums from interrupt 6 PU resumes processing of interrupted task Figure 9.2 Interrupt Driven 1/0 Cycle Features of Interrupt — handling (1) The ability to defer interrupts handling during critical processing. (2) An efficient way to dispatch to the appropriate interrupt handler for a device with first polling all the devices to see which one raised the interrupt, (3) Use of Multilevel interrupts - the Operating system can distiriguish between high low priority interrupts and can respond with the appropriate degree of importance. Interrupt Request Lines + The CPU has two interrupt request lines: 2 Non — Maskable Interrupt: The interrupt line which is reserved for events! unrecoverable memory errors. © Maskable Interrupt: Recoverable and the CPU in oft Mask can be turned off in sti situations when the sequence of instructions is interrupted, The maskable ite" is used by device controllers to request service, ‘divide error debug exception ull interrupt breakpoint INTO-detected overtiow bound range exception invalid opcode | device not available double fault ‘coprocessor segment overrun (reserved) invalid task state segment ‘Segment not present stack fault general protection Page fault (lntel reserved, do not use) floating-point error ‘alignment check machine check {Intel reserved, do not use) maskable interrupts Figure 9.3 Intel Pentium Processor event vector table + The vector contains the memory addresses of specialized interrupt handlers. + Reduce the need for a single interrupt handler to search all possible interrupts to determine which one needs service. sources of t Memory Access UNOM—Apr’15 Marks 5 Ditect Memory Access ; + DMA is used to avoid programmed 1/O for large data movement. It requires pie controller and by passes CPU to transfer data directly between I/O device and memory: + Many computers avoid burdening the main CPU wit loading some of its work to s special purpose processor Controller. + To begin a DMA transfer © The host writes a DMA command block into memory. ith the programmed V/O by off called a Direct Memory Access © The block contains * A pointer to the source and destination of transfer. + Account of the number of bytes to be transferred. Handshaking Process + The handshaking between the DMA controller and the device controller is performed through a pair of wires called DMA — Request and DMA ~ Acknowledge.ESN TSS ‘Steps to perform DMA transfer . 9. Operadi ing System jon the DMA Request Wite hen signa! + The device controler places ® © is available for transfer. + This signal causes the DM! © Toseize the memory bus: address om ne DMA- AC ives the (A controller the memory — address wires, senowledge Wire. pMA~Acknowledge signal, * To place the desired © Toplace asignal ont + When the device controller rece! i nory: © Transfers the word of data (0 men + Removes the DMA ~Reques sign i Gd 1. device driver is to transfer disk data CPU to bulfer at address X B.DMAcontroller 2. davico driver iels transfers bytes to isk controller 10 bulfer X, increasing transfer C byles memory address” tem dsktobufer [cache and decreasing C at address X until = 0 6. when C = 0, DMA t interrupts CPU to signal | JOerPE transfer completion SaaS 3. disk controller initiates: IDE disk |, DMA transfer r contraer | 4, disk controller sends each byte to DMA controller Figure 9.4 Steps in a DMA transfer (1) Device driver is told to transfer disk data to buffer at address X. (2) Device driver tells disk controller to transfer C bytes from disk to buffer at adies x. i‘ 3 (3) Disk controller initiates DMA transfer. (4) Disk controller sends each byte to DMA controller. (5) DMA controller transfers bytes to buffer X, increasi é creasing C until C= 0. 7G rsa sary so (©) When C= 0, DMA interrupts CPU to signal transfer completion.yale Stealing " , The Cycle stealing can slow dow, + Offloading the data transfey work + Direct Virtual memory the CPU computa translation. ‘Access (DMA) undergoes virtual to physical memo! Review Questions w Write short notes on 1/0 hardware, @ aive the significance of non maskable interrupt. 6) Diseus the concept of DMA, (a) Mention the basic hardware elements in /0 systems. o} Discuss the concept of | interrupts, 3 APPLICATION 1/0 INTERFACE 9.7 tion. ance. toa DMA controller improves the system perform ry address UNOM -Apr'13 Marks 5 UNOM —Apr’13 Marks 2 UNOM-Apr’15 Marks 5 UNOM ~Apr'16 Marks 2 UNOM - Nov'13 Marks 5] Outline tr + Introduction Characteristics of /0 Devices ° Various Dimensions of a Device * Block and Character Devices * Network Devices . Clocks and Timers * Blocking and Non Blocking /O 931. Introduction + WOsystem calls encapsulate device behaviors in generic classes. + Device driver layer hides differences among I/O cont 932 Characteristics of I/O Devices rollers from kernel. + Each general kind is accessed through a standardized set of functions — ‘Interface’. +» Devices vary on many dimensions, as given below. ‘Aspect Variation Example Data— transfer mode _| Character, block ‘Terminal disk ‘Access method Sequential , Random Modem, CD ROM TTansfer schedule Synchronous, Asynchronous ‘Tape, Keyboard Staring Dedicated, Sharable Tape, KeyboardVO direction Tatency, Seek ti Read only. Writ Write operations ROM, - @ g kernel VO subsystem 8 PCI bus floppy SCSI | keyboard | mouse device device device | device | device Giver | deer driver driver driver | SCSI | keyboard | mouse leg Gory ae oevies | dee? ntroller | controller @ | Controller | controller | controller o $ Ato to Ld e, floppy: Ane | "| | devices Scsl i : a ird| | mouse eee PCI bus disk di ce | oe || ae drives) | Figure 9.5 Kernel 1/0 structure I3.21 Various Dimensions Of A Device * Character — stream or block * A character stream device transfers bytes one by one, whereas a block dee transfers a block of bytes as a unit. * Sequential or Random access * A sequential device transfers data in a fixed order determined by the device. ¢ The user of a random access device can instruct the device to seek to any off available data storage locations. * Synchronous or Asynchronous * Asynchronous device performs data transfers with predictable response tims. * “An Asynchronous device exhibits irregular or unpredictable response times.