D.K.T.E. Society's Yashwantrao Chavan Polytechnic, Ichalkaranji
D.K.T.E. Society's Yashwantrao Chavan Polytechnic, Ichalkaranji
D.K.T.E. Society's Yashwantrao Chavan Polytechnic, Ichalkaranji
Society’s
Yashwantrao Chavan Polytechnic, Ichalkaranji.
Department of
Computer Science & Engineering.
Academic Year: 2021-22
*PROJECT REPORT*
ON
“7 Segment Display Decoder Circuit”
BY
Roll Name
No.
45 Naveli Kanake
DEPARTMENT OF
CERTIFICATE
THIS IS TO CERTIFY,
Seat No Name Sign
Naveli Kanake
Aditya Raju Patil
Ayaj Amir Mulla
Muskan Arif Nadaf
Prof. A. P. KOTHALI
(PRINCIPLE)
ACKNOWLEDGEMENT
An endeavor over long period can be successful only with advice &
guidance of many well-wishers. We thanks to H.O.D Prof. R.A.HATGINE of
Second year for this opportunity . We would like to thank the Computer science
and engineering department for assistance and constant source of
encouragement.
We wish to express our profound and deep sense of gratitude to Prof.
R.S.GHAT, for sparing their valuable time to extend help in every step of our
project.
45 Naveli Kanake
46 Aditya Raju Patil
47 Ayaj Amir Mulla
Thank You!
ABSTRACT
This paper presents the design and implementation of a digital system that uses a 7-
segment display to indicate the number of drug tablets in a tablet-bottling assembly line. As well
as display the number of tablets in a bottle (from 0 – 9), the display can also indicate the name of
the vitamin tablet being assembled (Vitamin A, b, C, d, E). This work presents the digital
implementation comprising the logic expression, logic circuit and VHDL code for the Vitamin type
in the bottle. A digital implementation to display the number of Vitamins in the tablet bottle as well
as the Vitamin type with a BBC microbit microcontroller is presented. The application of this work
can be extended to give a visual indication of any industrial application that requires indication of
the current production stage/phase.
INDEX
SR.
TITLE PAGE NO
NO.
1. Introduction
5. Conclusion
6. References
Introduction
Most often seven-segment displays are used to display the digits in digital watches,
calculators, clocks, measuring instruments and digital counters, etc. Generally, LCD and LED
segments provide the display output of numerical numbers and characters. However to display
the characters and numbers (in order to produce the decimal readout), seven-segment displays
are most commonly used. Mostly these displays are driven by the output stages of digital ICs (to
which the visual indication of the output stages has to be performed) such as latches and decade
counters, etc. But these outputs are in the form of 4-bit binary coded decimal (BCD), and not
suitable for directly driving the seven-segment displays. A display decoder is used to convert a
BCD or a binary code into a 7 segment code. It generally has 4 input lines and 7 output lines.
Here we design a simple display decoder circuit using logic gates. Even though commercial
BCD to 7 segment decoders are available, designing a display decoder using logic gates may
prove to be beneficial from economical as well as knowledge point of view.
Principle of Display Decoder Circuit
The basic idea involves driving a common cathode 7-segment LED display using combinational logic
circuit. The logic circuit is designed with 4 inputs and 7 outputs, each representing an input to the
display IC. Using Karnough’s map, logic circuitry for each input to the display is designed.
The first and foremost aspect of this circuit is decoder. A decoder is a combinational circuit which is
used to convert a binary or BCD (Binary Coded Decimal) number to the corresponding decimal
number . It can be a simple binary to decimal decoder or a BCD to 7 segment decoder.
Another relevant section is the combinational logic circuitry. A combinational logic circuit is a system
of logic gates consisting of only outputs and inputs. The output of a combinational logic circuit depends
only on the present state of the inputs and nothing else. Best examples of such circuits are Encoders and
Decoders, Multiplexers and De-multiplexers, Adders, Subtractor etc.
To understand the design and operation of these logic circuits, one needs to have a good knowledge
about Boolean algebra and logic gates. For example few basic Boolean algebra rules to be followed are
the complementary law, associative law, De-Morgan’s law etc.
A 7 segment LED display consists of an arrangement of 8 LEDs such that either all the anodes are
common or cathodes are common. A common cathode 7 segment display consists of 8 pins – 7 input
pins labeled from ‘a’ to ‘g’ and 8th pin as common ground pin.
7 Segment Display Decoder Circuit Design
Step 1: The first step of the design involves analysis of the common cathode 7-segment display. A 7-
segment display consists of an arrangement of LEDs in an ‘H’ form. A truth table is constructed with
the combination of inputs for each decimal number. For example, decimal number 1 would command a
combination of b and c (refer the diagram given below).
Step 2: The second step involves constructing the truth table listing the 7 display input signals,
decimal number and corresponding 4 digit binary numbers.
The truth table for the decoder design depends on the type of 7-segment display. As we
mentioned above that for a common cathode seven-segment display, the output of decoder or
segment driver must be active high in order to glow the segment.
The figure below shows the truth table of a BCD to seven-segment decoder with common
cathode display. In the truth table , there are 7 different output columns corresponding to each of
the 7 segments.
Suppose the column for segment a shows the different combinations for which it is to be
illuminated. So ‘a’ is active for the digits 0, 2, 3, 5, 6, 7, 8 and 9.
Truth Table:
From the above truth table, the Boolean expressions of each output functions can be written as
a = F1 (A, B, C, D) = ∑m (0, 2, 3, 5, 7, 8, 9)
b = F2 (A, B, C, D) = ∑m (0, 1, 2, 3, 4, 7, 8, 9)
c = F3 (A, B, C, D) = ∑m (0, 1, 3, 4, 5, 6, 7, 8, 9)
d = F4 (A, B, C, D) = ∑m (0, 2, 3, 5, 6, 8)
e = F5 (A, B, C, D) = ∑m (0, 2, 6, 8)
f = F6 (A, B, C, D) = ∑m (0, 4, 5, 6, 8, 9)
g = F7 (A, B, C, D) = ∑m (2, 3, 4, 5, 6, 8, 9)
Step 3: The third step involves constructing the Karnough’s map for each output term and then
simplifying them to obtain a logic combination of inputs for each output.
K-Map Simplification
The below figures shows the k-map simplification for the common cathode seven-segment decoder in
order to design the combinational circuit.
From the above simplification, we get the output values as
Step 4: The final step involves drawing a combinational logic circuit for each output signal. Once the
task was accomplished, a combinational logic circuit can be drawnusing 4 inputs (A,B,C,D)and a 7-
segment display (a,b,c,d,e,f,g) as output.
Display Decoder Circuit Operation
The circuit operation can be understood through the truth table itself. When all the inputs are connected
to low logic , the output of the combinational logic circuit would be so as to drive all the output LEDs
except ‘g’ to conduction. Thus the number 0 will be displayed. Similar operation would take place for
all other combinations of the input switches.
Applications of Display Decoder Circuit
1. This circuit can be modified using timers and counters to display the number of clock pulses.
2. This circuit can be modified to develop an alphabet display system instead of a decimal number
display system.
3. It can be used as a timer circuit.