MICRO CONTROLLER 89C51

Introduction
A Micro controller consists of a powerful CPU tightly coupled with memory, various
I/O interfaces such as serial port, parallel port timer or counter, interrupt controller, data
acquisition interfaces-Analog to Digital converter, Digital to Analog converter, integrated on
to a single silicon chip.
If a system is developed with a microprocessor, the designer has to go for external
memory such as RAM, ROM, EPROM and peripherals. But controller is provided all these
facilities on a single chip. Development of a Micro controller reduces PCB size and cost of
design.
One of the major differences between a Microprocessor and a Micro controller is that a
controller often deals with bits not bytes as in the real world application.
Intel has introduced a family of Micro controllers called the MCS-51.
The Major Features:

 Compatible with MCS-51 products

 4k Bytes of in-system Reprogrammable flash memory
 Fully static operation: 0HZ to 24MHZ
 Three level programmable clock
 128 * 8 –bit timer/counters
 Six interrupt sources
 Programmable serial channel
 Low power idle power-down modes

AT89C51 is 8-bit micro controller, which has 4 KB on chip flash memory, which is
just sufficient for our application. The on-chip Flash ROM allows the program memory to be
reprogrammed in system or by conventional non-volatile memory Programmer. Moreover
ATMEL is the leader in flash technology in today’s market place and hence using AT 89C51
is the optimal solution.
AT89C51 MICROCONTROLLER ARCHITECTURE

The 89C51 architecture consists of these specific features:

 Eight –bit CPU with registers A (the accumulator) and B

 Sixteen-bit program counter (PC) and data pointer (DPTR)
 Eight- bit stack pointer (PSW)
 Eight-bit stack pointer (Sp)
 Internal ROM or EPROM (8751) of 0(8031) to 4K (89C51)
 Internal RAM of 128 bytes:
 Thirty –two input/output pins arranged as four 8-bit ports:p0-p3
 Two 16-bit timer/counters: T0 and T1
 Full duplex serial data receiver/transmitter: SBUF
 Control registers: TCON, TMOD, SCON, PCON, IP, and IE
 Two external and three internal interrupts sources.
 Oscillator and clock circuits.

Fig 3: Functional block diagram of micro controller

Types of memory:

The 89C51 have three general types of memory. They are on-chip memory, external Code
memory and external Ram. On-Chip memory refers to physically existing memory on the micro
controller itself. External code memory is the code memory that resides off chip. This is often in the
form of an external EPROM. External RAM is the Ram that resides off chip. This often is in the form
of standard static RAM or flash RAM.

a) Code memory
Code memory is the memory that holds the actual 89C51 programs that is to be run. This
memory is limited to 64K. Code memory may be found on-chip or off-chip. It is possible to have 4K of
code memory on-chip and 60K off chip memory simultaneously. If only off-chip memory is available
then there can be 64K of off chip ROM. This is controlled by pin provided as EA.

b) Internal RAM
The 89C51 have a bank of 128 of internal RAM. The internal RAM is found on-chip. So it is
the fastest Ram available. And also it is most flexible in terms of reading and writing. Internal Ram is
volatile, so when 89C51 is reset, this memory is cleared. 128 bytes of internal memory are
subdivided. The first 32 bytes are divided into 4 register banks. Each bank contains 8 registers.
Internal RAM also contains 128 bits, which are addressed from 20h to 2Fh. These bits are bit
addressed i.e. each individual bit of a byte can be addressed by the user. They are numbered 00h to
7Fh. The user may make use of these variables with commands such as SETB and CLR.

Flash memory is a nonvolatile memory using NOR technology, which allows the user to
electrically program and erase information. Flash memory is used in digital cellular phones, digital
cameras, LAN switches, PC Cards for notebook computers, digital set-up boxes, embedded
controllers, and other devices.
 Fig 5: - Pin diagram of AT89C51

Pin Description:

VCC: Supply voltage.

GND: Ground.

Port 0:

Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can
sink eight TTL inputs. When 1sare written to port 0 pins, the pins can be used as high
impedance inputs. Port 0 may also be configured to be the multiplexed low order address/data
bus during accesses to external program and data memory. In this mode P0 has internal pull-
ups. Port 0 also receives the code bytes during Flash programming, and outputs the code
bytes during program verification. External pull-ups are required during program verification.
Port 1:

Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output
buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled
high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are
externally being pulled low will source current (IIL) because of the internal pull-ups. Port 1
also receives the low-order address bytes during Flash programming and verification.
Port 2:

Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output
buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled
high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are
externally being pulled low will source current (IIL) because of the internal pull-ups.
Port 3:

Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers can
sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal
pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will
source current (IIL) because of the pull-ups.

Port 3 also serves the functions of various special features of the AT89C51 as listed below:

Tab 6.2.1 Port pins and their alternate functions

RST:

Reset input. A high on this pin for two machine cycles while the oscillator is running resets
the device.

ALE/PROG:

Address Latch Enable output pulse for latching the low byte of the address during
accesses to external memory. This pin is also the program pulse input (PROG) during Flash
programming. In normal operation ALE is emitted at a constant rate of 1/6the oscillator
frequency, and may be used for external timing or clocking purposes. Note, however, that one
ALE pulse is skipped during each access to external Data Memory.
If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is
active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the
ALE-disable bit has no effect if the micro controller is in external execution mode.

PSEN:

Program Store Enable is the read strobe to external program memory. When the
AT89C51 is executing code from external program memory, PSEN is activated twice each
machine cycle, except that two PSEN activations are skipped during each access to external
data memory.
EA/VPP:

External Access Enable. EA must be strapped to GND in order to enable the device to fetch
code from external program memory locations starting at 0000H up to FFFFH.

Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA
should be strapped to VCC for internal program executions. This pin also receives the 12-volt
programming enable voltage (VPP) during Flash programming, for parts that require 12-volt VPP.

XTAL1:

Input to the inverting oscillator amplifier and input to the internal clock operating
circuit.

XTAL2:

Output from the inverting oscillator amplifier.

Oscillator Characteristics:

XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier,
which can be configured for use as an on-chip oscillator, as shown in Figs 6.1 Either a quartz
crystal or ceramic resonator may be used. To drive the device from an external clock source,
XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 6.2. There are no
requirements on the duty cycle of the external clock signal, since the input to the internal
clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage
high and low time specifications must be observed.

Fig 6.1 Oscillator Connections Fig 6.2 External Clock Drive Configuration