Programmable Frequency Sweep and

Output Burst Waveform Generator

Data Sheet AD5930
FEATURES GENERAL DESCRIPTION
Programmable frequency profile The AD59301 is a waveform generator with programmable
No external components necessary frequency sweep and output burst capability. Utilizing
Output frequency up to 25 MHz embedded digital processing that allows enhanced frequency
Burst and listen capability control, the device generates synthesized analog or digital
Preprogrammable frequency profile minimizes number of frequency-stepped waveforms. Because frequency profiles
DSP/µcontroller writes
are preprogrammed, continuous write cycles are eliminated
Sinusoidal/triangular/square wave outputs
and thereby free up valuable DSP/µcontroller resources.
Automatic or single pin control of frequency stepping Waveforms start from a known phase and are incremented
Waveform starts at known phase phase continuously, which allows phase shifts to be easily
Increments at 0° phase or phase continuously determined. Consuming only 8 mA, the AD5930 provides a
Power-down mode: 20 µA convenient low power solution to waveform generation.
Power supply: 2.3 V to 5.5 V
Automotive temperature range: −40°C to +125°C The AD5930 can be operated in a variety of modes. In
20-lead pb-free TSSOP continuous output mode, the device outputs the required
frequency for a defined length of time and then steps to the
next frequency. The length of time the device outputs a
APPLICATIONS particular frequency is either preprogrammed and the device
Frequency sweeping/radar increments the frequency automatically, or, alternatively, is
Network/impedance measurements incremented externally via the CTRL pin. In burst mode, the
Incremental frequency stimulus device outputs its frequency for a length of time and then
Sensory applications returns to midscale for a further predefined length of time
Proximity and motion before stepping to the next frequency. When the MSBOUT pin
BFSK is enabled, a digital output is generated.
Frequency bursting/pulse trains
(continued on Page 3)

FUNCTIONAL BLOCK DIAGRAM

INTERRUPT STANDBY DVDD CAP/2.5V DGND AGND AVDD

AD5930 REGULATOR
VCC SYNC
MCLK 2.5V BUFFER SYNCOUT
OUTPUT BURST
CONTROLLER
DGND O/P
DATA SYNC
BUFFER MSBOUT
CTRL INCREMENT
CONTROLLER
DATA INCR 24-BIT 10-BIT IOUTB
PIPELINED DAC
FREQUENCY DDS CORE IOUT
CONTROLLER 24
DATA AND CONTROL
ON-BOARD FULL-SCALE COMP
CONTROL REFERENCE CONTROL
SERIAL INTERFACE REGISTER
05333-001

FSYNC SCLK SDATA REF FSADJUST

Figure 1.

1
Protected by US Patent Number 6747583.

Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
No license is granted by implication or otherwise under any patent or patent rights of Analog Tel: 781.329.4700 www.analog.com
Devices.Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 © 2005–2012 Analog Devices, Inc. All rights reserved.
AD5930 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 Powering up the AD5930 .......................................................... 17

Applications ....................................................................................... 1 Programming the AD5930........................................................ 17

General Description ......................................................................... 1 Setting up the Frequency Sweep............................................... 19

Functional Block Diagram .............................................................. 1 Activating and Controlling the Sweep ..................................... 20

Revision History ............................................................................... 2 Outputs from the AD5930 ........................................................ 21

Specifications..................................................................................... 4 Applications..................................................................................... 22

Timing Characteristics..................................................................... 6 Grounding and Layout .............................................................. 22

Absolute Maximum Ratings............................................................ 8 AD5930 to ADSP-21xx Interface ............................................. 22

ESD Caution .................................................................................. 8 AD5930 to 68HC11/68L11 Interface ....................................... 23

Pin Configuration and Function Descriptions ............................. 9 AD5930 to 80C51/80L51 Interface .......................................... 23

Typical Performance Characteristics ........................................... 11 AD5930 to DSP56002 Interface ............................................... 23

Terminology .................................................................................... 15 Evaluation Board ........................................................................ 24

Theory of Operation ...................................................................... 16 Schematic..................................................................................... 25

The Frequency Profile................................................................ 16 Outline Dimensions ....................................................................... 27

Output Modes ............................................................................. 16 Ordering Guide .......................................................................... 27

Serial Interface ............................................................................ 17

REVISION HISTORY
2/12—Rev. 0 to Rev. A
Change to Figure 2 ........................................................................... 5
Changes to Figure 22, Figure 23, Figure 24, Figure 25,
and Figure 26 ................................................................................... 13
Changes to Figure 27, Figure 28, Figure 29, and
Figure 30 .......................................................................................... 25

11/05—Revision 0: Initial Version

Rev. A | Page 2 of 28
Data Sheet AD5930

GENERAL DESCRIPTION
(continued from Page 1)

To program the device, the user enters the start frequency, the sweep again. In addition, a single frequency or burst can be
increment step size, the number of increments to be made, and generated without any sweep.
the time interval that the part outputs each frequency. The The AD5930 is written to via a 3-wire serial interface, which
frequency sweep profile is initiated, started, and executed by operates at clock rates up to 40 MHz. The device operates with
toggling the CTRL pin. a power supply from 2.3 V to 5.5 V. Note that AVDD and DVDD
A number of different sweep profiles are offered. Frequencies can are independent of each other and can be operated from
be stepped in triangular-sweep mode, which continuously sweeps different voltages. The AD5930 also has a standby function,
up and down through the frequency range. Alternatively, in saw- which allows sections of the device that are not being used
sweep mode, the frequency is swept up through the frequency to be powered down.
range, but returns to the initial frequency before executing the The AD5930 is available in a 20-lead pb-free TSSOP package.

Rev. A | Page 3 of 28
AD5930 Data Sheet

SPECIFICATIONS
AVDD = DVDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, TA = TMIN to TMAX, RSET = 6.8 kΩ, RLOAD = 200 Ω for IOUT and IOUTB,
unless otherwise noted.
Table 1.
Y Grade 1
Parameter Min Typ Max Unit Test Conditions/Comments
SIGNAL DAC SPECIFICATIONS
Resolution 10 Bits
Update Rate 50 MSPS
IOUT Full-Scale 2 3 4.0 mA
VOUT Peak-to-Peak 0.56 V
VOUT Offset 45 mV From 0 V to the trough of the waveform
VMIDSCALE 0.325 V Voltage at midscale output
Output Compliance 0.8 V AVDD = 2.3 V, internal reference used 3
DC Accuracy
Integral Nonlinearity (INL) ±1.5 LSB
Differential Nonlinearity (DNL) ±0.75 LSB
DDS SPECIFICATIONS
Dynamic Specifications
Signal-to-Noise Ratio 53 60 dB fMCLK = 50 MHz, fOUT = fMCLK/4096
Total Harmonic Distortion −60 −53 dBc fMCLK = 50 MHz, fOUT = fMCLK/4096
Spurious-Free Dynamic Range
(SFDR)
Wideband (0 to Nyquist) −62 −52 dBc fMCLK = 50 MHz, fOUT = fMCLK/50
Narrowband (±200 kHz) −76 −73 dBc fMCLK = 50 MHz, fOUT = fMCLK/50
Clock Feedthrough −50 dBc Up to 16 MHz out
Wake-Up Time 1.7 ms From standby
OUTPUT BUFFER
VOUT Peak-to-Peak 0 DVDD V Typically, square wave on MSBOUT and SYNCOUT
Output Rise/Fall Time2 12 ns
VOLTAGE REFERENCE
Internal Reference 1.15 1.18 1.26 V
External Reference Range 1.3 V
REFOUT Input Impedance 1 kΩ VIN @ REF pin < Internal VREF
25 kΩ VIN @ REF pin > Internal VREF
Reference TC2 90 ppm/°C
LOGIC INPUTS
Input Current 0.1 ±1 µA
VINH, Input High Voltage 1.7 V DVDD = 2.3 V to 2.7 V
2.0 V DVDD = 2.7 V to 3.6 V
2.8 V DVDD = 4.5 V to 5.5 V
VINL, Input Low Voltage 0.6 V DVDD = 2.3 V to 2.7 V
0.7 V DVDD = 2.7 V to 3.6 V
0.8 V DVDD = 4.5 V to 5.5 V
CIN, Input Capacitance2 3 pF
LOGIC OUTPUTS2
VOH, Output High Voltage DVDD − 0.4 V V ISINK = 1 mA
VOL, Output Low Voltage 0.4 V ISINK = 1 mA
Floating-State O/P Capacitance 5 pF

Rev. A | Page 4 of 28
Data Sheet AD5930
Y Grade 1
Parameter Min Typ Max Unit Test Conditions/Comments
POWER REQUIREMENTS fMCLK = 50 MHz, fOUT = fMCLK/7
AVDD/DVDD 2.3 5.5 V
IAA 3.8 4 mA
IDD 2.4 2.7 mA
IAA + IDD 6.2 6.7 mA
Low Power Sleep Mode Device is reset before putting into standby
20 85 µA All outputs powered down, MCLK = 0 V, serial interface active
140 240 µA All outputs powered down, MCLK active, serial interface active
1
Operating temperature range is as follows: Y Version: −40°C to +125°C; typical specifications are at 25°C.
2
Guaranteed by design.
3
Minimum RSET = 3.9 kΩ.

RSET
100nF 10nF 6.8V

CAP/2.5V REFOUT FSADJUST AVDD

10nF
REGULATOR
ON-BOARD FULL-SCALE COMP
REFERENCE CONTROL

12 SIN IOUT
AD5930 10-BIT
ROM DAC
RLOAD

05333-002
20pF
200Ω

Figure 2. Test Circuit Used to Test the Specifications

Rev. A | Page 5 of 28
AD5930 Data Sheet

TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
See Figure 4 to Figure 7. DVDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, all specifications TMIN to TMAX, unless otherwise noted.
Table 2. 1
Parameter Limit at TMIN, TMAX Unit Conditions/Comments
t1 20 ns min MCLK period
t2 8 ns min MCLK high duration
t3 8 ns min MCLK low duration
t4 25 ns min SCLK period
t5 10 ns min SCLK high time
t6 10 ns min SCLK low time
t7 5 ns min FSYNC to SCLK falling edge setup time
t8 10 ns min FSYNC to SCLK hold time
t9 5 ns min Data setup time
t10 3 ns min Data hold time
t11 2 x t1 ns min Minimum CTRL pulse width
t12 0 ns min CTRL rising edge to MCLK falling edge setup time
t13 10 x t1 ns typ CTRL rising edge to IOUT/IOUTB delay (initial pulse, includes initialization)
8 x t1 ns typ CTRL rising edge to IOUT/IOUTB delay (initial pulse, includes initialization)
t14 2 x t1 ns typ Frequency change to SYNC output, saw sweep, each frequency increment
t15 2 x t1 ns typ Frequency change to SYNC output, saw sweep, end of sweep
t16 2 x t1 ns typ Frequency change to SYNC output, triangle sweep, end of sweep
t17 20 ns max MCLK falling edge after 16th clock edge to MSB out
1
Guaranteed by design, not production tested.

t1
MCLK
05333-003

t2
t3

Figure 3. Master Clock

t5 t4
SCLK
t7 t6 t8
FSYNC

t10
t9
05333-004

SDATA D15 D14 D2 D1 D0 D15 D14

Figure 4. Serial Timing

Rev. A | Page 6 of 28
Data Sheet AD5930
t12
MCLK

CTRL
t11

05333-005
IOUT/IOUTB
t13

Figure 5. CTRL Timing

CTRL

t13
IOUT

SYNC O/P
(Each Frequency
Increment) t14

05333-006
SYNC O/P
(End of Sweep) t15

Figure 6. CTRL Timing, Saw-Sweep Mode

CTRL

t13
IOUT

SYNC O/P
(Each Frequency
Increment) t14
05333-007

SYNC O/P
(End of Sweep) t16

Figure 7. CTRL Timing, Triangular-Sweep Mode

Rev. A | Page 7 of 28
AD5930 Data Sheet

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings
Table 3. may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
Parameter Rating
other conditions above those indicated in the operational
AVDD to AGND −0.3 V to +6.0 V
section of this specification is not implied. Exposure to absolute
DVDD to DGND −0.3 V to +6.0 V
maximum rating conditions for extended periods may affect
AGND to DGND −0.3 V to +0.3 V
device reliability.
CAP/2.5V to DGND −0.3 V to 2.75 V
Digital I/O Voltage to DGND −0.3 V to DVDD + 0.3 V
Analog I/O Voltage to AGND −0.3 V to AVDD + 0.3 V
Operating Temperature Range
Automotive (Y Version) −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature +150°C
TSSOP Package (4-Layer Board)
θJA Thermal Impedance 112°C/W
θJC Thermal Impedance 27.6°C/W
Reflow Soldering (Pb-Free) 300°C
Peak Temperature 260(+0/−5)°C
Time at Peak Temperature 10 sec to 40 sec

ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. A | Page 8 of 28
Data Sheet AD5930

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

FSADJUST 1 20 IOUTB
REF 2 19 IOUT
COMP 3 18 AGND
AD5930
AVDD 4 TOP VIEW 17 STANDBY
(Not to Scale)
DVDD 5 16 FSYNC
CAP/2.5V 6 15 SCLK
DGND 7 14 SDATA
MCLK 8 13 CTRL
SYNCOUT 9 12 INTERRUPT

05333-008
MSBOUT 10 11 DGND O/P

Figure 8. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description
1 FSADJUST Full-Scale Adjust Control. A resistor (RSET) must be connected externally between this pin and AGND.
This determines the magnitude of the full-scale DAC current. The relationship between RSET and the
full-scale current is:
IOUTFULL-SCALE = 18 × VREFOUT/RSET
where VREFOUT = 1.20 V nominal and RSET = 6.8 kΩ typical.
2 REF Voltage Reference. This pin can be an input or an output. The AD5930 has an internal 1.18 V reference, which
is made available at this pin. Alternatively, this reference can be overdriven by an external reference, with a
voltage range as given in the Specifications section. A 10 nF decoupling capacitor should be connected
between REF and AGND.
3 COMP DAC Bias Pin. This pin is used for decoupling the DAC bias voltage to AVDD.
4 AVDD Positive Power Supply for the Analog Section. AVDD can have a value from +2.3 V to +5.5 V. A 0.1 µF decoupling
capacitor should be connected between AVDD and AGND.
5 DVDD Positive Power Supply for the Digital Section. DVDD can have a value from +2.3 V to +5.5 V. A 0.1 µF decoupling
capacitor should be connected between DVDD and DGND.
6 CAP/2.5V Digital Circuitry. Operates from a 2.5 V power supply. This 2.5 V is generated from DVDD using an on-board
regulator. The regulator requires a decoupling capacitor of typically 100 nF, which is connected from CAP/2.5V
to DGND. If DVDD is equal to or less than 2.7 V, CAP/2.5V can be shorted to DVDD.
7 DGND Ground for all Digital Circuitry. This excludes digital output buffers.
8 MCLK Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK.
The output frequency accuracy and phase noise are determined by this clock.
9 SYNCOUT Digital Output for Sweep Status Information. User selectable for end of sweep (EOS) or frequency increments
through the control register (SYNCOP bit). This pin must be enabled by setting Control Register Bit SYNCOPEN to 1.
10 MSBOUT Digital Output. The inverted MSB of the DAC data is available at this pin. This output pin must be enabled by
setting bit MSBOUTEN in the control register to 1.
11 DGND O/P Separate DGND Connection for Digital Output Buffers. Connect to DGND.
12 INTERRUPT Digital Input. This pins acts as an interrupt during a frequency sweep. A low to high transition is sampled by the
internal MCLK, which resets internal state machines. This results in the DAC output going to midscale.
13 CTRL Digital Input. Triple function pin for initialization, start, and external frequency increments. A low-to-high transition,
sampled by the internal MCLK, is used to initialize and start internal state machines, which then execute the pre-
programmed frequency sweep sequence. When in auto-increment mode, a single pulse executes the entire sweep
sequence. When in external increment mode, each frequency increment is triggered by low-to-high transitions.
14 SDATA Serial Data Input. The 16-bit serial data-word is applied to this input with the register address first followed by the
MSB to LSB of the data.
15 SCLK Serial Clock Input. Data is clocked into the AD5930 on each falling SCLK edge.
16 FSYNC Active Low Control Input. This is the frame synchronization signal for the serial data. When FSYNC is taken low,
the internal logic is informed that a new word is being loaded into the device.
17 STANDBY Active High Digital Input. When this pin is high, the internal MCLK is disabled, and the reference DAC and regulator
are powered down. For optimum power saving, it is recommended to reset the AD5930 before putting it into
standby, as this results in a shutdown current of typically 20 µA.

Rev. A | Page 9 of 28
AD5930 Data Sheet
Pin No. Mnemonic Description
18 AGND Ground for all Analog Circuitry.
19 IOUT Current Output. This is a high impedance current source output. A load resistor of nominally 200 Ω should be
connected between IOUT and AGND. A 20 pF capacitor to AGND is also recommended to act as a low-pass filter
and to reduce clock feedthrough. In conjunction with IOUTB, a differential signal is available.
20 IOUTB Current Output. IOUTB is the compliment of IOUT. This pin should preferably be tied through an external load
resistor of 200 Ω to AGND, but can be tied directly to AGND. A 20 pF capacitor to AGND is also recommended as a
low-pass filter to reduce clock feedthrough. In conjunction with IOUT, a differential signal is available.

Rev. A | Page 10 of 28
Data Sheet AD5930

TYPICAL PERFORMANCE CHARACTERISTICS

9 –40
TA = 25°C AVDD = DVDD = 3V/5V
8 AVDD = 5V –45 MCLK = 50MHz
MSBOUT, SYNCOUT ENABLED CREG = 0111 1111 1111
DVDD = 5V –50 TA = 25°C
7 FOUT = MCLK/7
–55
6

SFDR (dBc)
–60 FOUT = MCLK/50
IDD (mA)

5 DVDD = 3V
–65
4
–70
3 DVDD = 5V, FOUT = MCLK/7
–75 FOUT = MCLK/3
2
–80
DVDD = 3V, FOUT = MCLK/7

05333-027

05333-030
1 –85

0 –90
0 5 10 15 20 25 30 35 40 45 50 0 5 10 15 20 25 30 35 40 45 50
MCLK FREQUENCY (MHz) MCLK FREQUENCY (MHz)

Figure 9. Current Consumption (IDD) vs. MCLK Frequency Figure 12. Wideband SFDR vs. MCLK Frequency

7 –60
TA = 25°C AVDD = DVDD = 3V/5V
MCLK = 50MHz MSBOUT ON,
SYNCOUT ON MCLK = 50MHz
6 CREG = 0111 1111 1111
–65
TA = 25°C
5
MSBOUT OFF, FOUT = MCLK/50
MSBOUT ON, –70
SYNCOUT ON
SFDR (dBc)

SYNCOUT OFF
IDD (mA)

4
–75 FOUT = MCLK/3
3
MSBOUT OFF,
–80
2 SYNCOUT OFF

1 –85 FOUT = MCLK/7

05333-028

05333-031
0 –90
1kHz 100kHz 1MHz 5MHz 15MHz 25MHz 0 5 10 15 20 25 30 35 40 45 50
500kHz 10kHz 500kHz 2MHz 10MHz 20MHz
MCLK FREQUENCY (MHz)
FOUT (Hz)

Figure 10. IDD vs. FOUT for Various Digital Output Conditions Figure 13. Narrowband SFDR vs. MCLK Frequency

3.5 –30
AVDD = DVDD = 3V/5V
AIDD CREG = 0111 1111 1111
3.0 –40 TA = 25°C MCLK = 50MHz

2.5
–50
DIDD
SFDR (dBc)

2.0
IDD (mA)

–60
1.5
MCLK = 10MHz
–70
1.0
LEGEND MCLK = 1MHz
MCLK = 30MHz
1. SINEWAVE OUTPUT, INTERNALLY CONTROLLED SWEEP –80
0.5 2. TRIANGULAR OUTPUT, INTERNALLY CONTROLLED SWEEP
05333-032
05333-029

3. SINEWAVE OUTPUT, EXTERNALLY CONTROLLED SWEEP

4. TRIANGULAR OUTPUT, EXTERNALLY CONTROLLED SWEEP
0 –90
1 2 3 4 0.001 0.01 0.1 1 10 100
CONTROL OPTION (See Legend) FOUT (MHz)

Figure 11. IDD vs. Output Waveform Type and Control Figure 14. Wideband SFDR vs. FOUT for Various MCLK Frequencies

Rev. A | Page 11 of 28
AD5930 Data Sheet
70 12
TA = 25°C
AVDD = DVDD = 5V
65 fOUT = FMCLK/4096 10

NUMBER OF DEVICES
60 8
SNR (dB)

55 6

50 4

45 2

05333-034

05333-025
40 0
0 10M 20M 30M 40M 50M 552 554 556 558 560 562 564 566 568 570 572
MCLK FREQUENCY (MHz) VOUT PEAK-TO-PEAK (mV)

Figure 15. SNR vs. MCLK Frequency Figure 18. Histogram of VOUT Peak-to-Peak

12
1.25
AVDD = DVDD = 5V
10

1.23

NUMBER OF DEVICES
8

1.21
VREF (V)

1.19 4

2
1.17

05333-026
05333-035

0
1.15 44.4 44.6 44.8 45.0 45.2 45.4 45.6 45.8 46.0 46.2
–40 –20 0 20 40 60 80 100 120 VOUT OFFSET (mV)
TEMPERATURE (°C)

Figure 16. VREF vs. Temperature Figure 19. Histogram of VOUT Offset
0
2.0 TA = 25°C
–10 100mV p-p RIPPLE
NO DECOUPLING ON SUPPLIES
1.9 AVDD = DVDD = 2.3V
AVDD = DVDD = 5V
–20
1.8
ATTENUATION (dB)
WAKE-UP TIME (ms)

–30
1.7 AVDD = DVDD = 5V DVDD (on CAP/2.5V)
–40
1.6
–50
1.5
–60
1.4
–70 AVDD (on IOUT)
05333-033

1.3
05333-036

–80
1.2 10 100 1k 10k 100k 1M
–40 –20 0 20 40 60 80 100 120 MODULATING FREQUENCY (Hz)
TEMPERATURE (°C)

Figure 17. Wake-up Time vs. Temperature Figure 20. PSSR

Rev. A | Page 12 of 28
Data Sheet AD5930
0 0
–10
–20 –10
–30
–20
–40
–50 –30
–60
PHASE NOISE

–70 –40
–80

(dB)
–50
–90
–100 –60
–110
–120 –70
–130
–80
–140

05333-037

05333-016
–150 –90
–160
–170 –100
100 1k 10k 100k 0 5M
f (Hz) RWB 1K VWB 300 ST 50 SEC
FREQUENCY (Hz)

Figure 21. Output Phase Noise Figure 24. fMCLK = 10 MHz; fOUT = 3.33 MHz = fMCLK/3,
Frequency Word = 555555

0 0

–10 –10

–20 –20

–30 –30

–40 (dB) –40

(dB)

–50 –50

–60 –60

–70 –70

–80 –80

05333-017
05333-014

–90 –90

–100 –100
0 100k 0 160k
RWB 100 VWB 30 ST 100 SEC RWB 100 VWB 30 ST 200 SEC
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 22. fMCLK = 10 MHz; Figure 25. fMCLK = 50 MHz;

fOUT = 2.4 kHz, Frequency Word = 000FBA fOUT = 12 kHz, Frequency Word = 000FBA

0 0

–10 –10

–20 –20

–30 –30

–40 –40
(dB)
(dB)

–50 –50

–60 –60

–70 –70

–80 –80
05333-018
05333-015

–90 –90

–100 –100
0 5M 0 1.6M
RWB 1K VWB 300 ST 50 SEC RWB 100 VWB 300 ST 200 SEC
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 23. fMCLK = 10 MHz; Figure 26. fMCLK = 50 MHz;

fOUT = 1.43 MHz = fMCLK/7, Frequency Word = 249249 fOUT = 120 kHz, Frequency Word = 009D49

Rev. A | Page 13 of 28
AD5930 Data Sheet
0 0

–10 –10

–20 –20

–30 –30

–40 –40
(dB)

(dB)
–50 –50

–60 –60

–70 –70

–80 –80

05333-019

05333-021
–90 –90

–100 –100
0 25M 0 25M
RWB 1K VWB 300 ST 200 SEC RWB 1K VWB 300 ST 200 SEC
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 27. fMCLK = 50 MHz; Figure 29. fMCLK = 50 MHz; fOUT = 7.143 MHz = fMCLK/7,
fOUT = 1.2 MHz, Frequency Word = 0624DD Frequency Word = 2492492

0 0

–10 –10

–20 –20

–30 –30

–40 –40
(dB)
(dB)

–50 –50

–60 –60

–70 –70

–80 –80

05333-022
05333-020

–90 –90

–100 –100
0 25M 0 25M
RWB 1K VWB 300 ST 200 SEC RWB 1K VWB 300 ST 200 SEC
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 28. fMCLK = 50 MHz; Figure 30. fMCLK = 50 MHz; fOUT = 16.667 MHz = fMCLK/3,
fOUT = 4.8 MHz, Frequency Word = 189374 Frequency Word = 5555555

Rev. A | Page 14 of 28
Data Sheet AD5930

TERMINOLOGY
Integral Nonlinearity (INL) Total Harmonic Distortion (THD)
This is the maximum deviation of any code from a straight line THD is the ratio of the rms sum of harmonics to the rms value
passing through the endpoints of the transfer function. The of the fundamental. For the AD5930, THD is defined as
endpoints of the transfer function are zero scale and full scale.
The error is expressed in LSBs. V 2 2 + V 3 2 + V 4 2 + V 5 2 + V6 2
THD(dB) = 20 log
V1
Differential Nonlinearity (DNL)
This is the difference between the measured and ideal 1 LSB where:
change between two adjacent codes in the DAC. A specified V1 is the rms amplitude of the fundamental.
differential nonlinearity of ±1 LSB maximum ensures V2, V3, V4, V5, and V6 are the rms amplitudes of the second
monotonicity. through the sixth harmonic.

Output Compliance Signal-to-Noise Ratio (SNR)

The output compliance refers to the maximum voltage that can SNR is the ratio of the rms value of the measured output signal
be generated at the output of the DAC to meet the specifica- to the rms sum of all other spectral components below the
tions. When voltages greater than that specified for the output Nyquist frequency. The value for SNR is expressed in decibels.
compliance are generated, the AD5930 may not meet the
specifications listed in the data sheet. Clock Feedthrough
There is feedthrough from the MCLK input to the analog
Spurious-Free Dynamic Range (SFDR) output. Clock feedthrough refers to the magnitude of the
Along with the frequency of interest, harmonics of the MCLK signal relative to the fundamental frequency in the
fundamental frequency and images of these frequencies are AD5930’s output spectrum.
present at the output of a DDS device. The SFDR refers to the
largest spur or harmonic that is present in the band of interest.
The wide band SFDR gives the magnitude of the largest
harmonic or spur relative to the magnitude of the fundamental
frequency in the 0 to Nyquist bandwidth. The narrow band
SFDR gives the attenuation of the largest spur or harmonic in a
bandwidth of ±200 kHz about the fundamental frequency.

Rev. A | Page 15 of 28
AD5930 Data Sheet

THEORY OF OPERATION
The AD5930 is a general-purpose synthesized waveform Triangular-Sweep Mode
generator capable of providing digitally programmable In the case of a triangular sweep, the AD5930 repeatedly
waveform sequences in both the frequency and time domain. sweeps between sweep start to sweep end, that is, from FSTART
The device contains embedded digital processing to provide a incrementally to
repetitive sweep of a user programmable frequency profile
FSTART + NINCR × Δf
allowing enhanced frequency control. Because the device is pre-
programmable, it eliminates continuous write cycles from a and then returns to FSTART in a decremented manner (see Figure 32).
DSP/μcontroller in generating a particular waveform. The triangular-sweep cycle time is given by
THE FREQUENCY PROFILE (1 + (2 × NINCR)) × tINT
The frequency profile is defined by the start frequency (FSTART),
the frequency increment (Δf) and the number of increments
per sweep (NINCR). The increment interval between frequency
increments, tINT, is either user programmable with the interval FSTART

automatically determined by the device (auto-increment mode), MIDSCALE

05333-010
or externally controlled via a hardware pin (external increment FSTART FSTART + NINCR × ∆F FSTART
FSTART + ∆F FSTART + ∆F
mode). For automatic update, the interval profile can either be
for a fixed number of clock periods or for a fixed number of Figure 32. Triangular-Sweep Profile
output waveform cycles.
OUTPUT MODES
In the auto-increment mode, a single pulse at the CTRL pin starts The AD5930 offers two possible output modes: continuous
and executes the frequency sweep. In the external increment output mode and burst output mode. Both of these modes are
mode, the CTRL pin also starts the sweep, but the frequency illustrated in Figure 33.
increment interval is determined by the time interval between
sequential 0/1 transitions on the CTRL pin. Furthermore, the tINT

CTRL pin can be used to directly control the burst profile, where CONTINUOUS
during the input high time, the output waveform is present, and MODE

during the input low time, the output is reset to midscale.

TBURST

The frequency profile can be swept in two different modes: saw BURST
sweep or triangular (up/down) sweep. MODE

Saw-Sweep Mode

05333-011
1 2
In the case of a saw sweep, the AD5930 repeatedly NUMBER STEP CHANGES

sweeps between sweep start to sweep end, that is, from Figure 33. Continuous Mode and Burst Mode of the AD5930
FSTART incrementally to
Continuous Output Mode
FSTART + NINCR × Δf
In this mode, each frequency of the sweep is available for the
and then returns directly to FSTART to begin again (see Figure 31). length of time programmed into the time interval (tINT) register.
This gives a saw-sweep cycle time of This means the frequency swept output signal is continuously
(NINCR + 1) × tINT available, and is therefore phase continuous at all frequency
increments.

To set up the AD5930 in continuous mode, the CW/BURST bit

(D7) in the control register must be set to 0. See the Activating
and Controlling the Sweep section for more details.

Burst Output Mode

In this mode, the AD5930 provides a programmable burst
FSTART
of the waveform output for a fixed length of time (TBURST)
MIDSCALE
within the programmed increment interval (tINT). Then for
05333-009

the remainder of the tINT interval, the output is reset to mid-

FSTART FSTART + ∆F FSTART + NINCR × ∆F
scale and remains there until the next frequency increment.
Figure 31. Saw-Sweep Profile

Rev. A | Page 16 of 28
Data Sheet AD5930
This is beneficial for applications where the user needs to burst PROGRAMMING THE AD5930
a frequency for a set period, and then “listen” for a response The AD5930 is designed to provide automatic frequency sweeps
before increasing to the next frequency. Note also that the when the CTRL pin is triggered. The automatic sweep is
beginning of each frequency increment is at midscale (Phase 0 controlled by a set of registers, the addresses of which are given
Rad). Therefore, the phase of the signal is always known. in Table 5. The function of each register is described in more
To set up the AD5930 in burst mode, the CW/BURST bit (D7) detail in the following section.
in the control register must be set to 1. See the Activating and Table 5. Register Addresses
Controlling the Sweep section for more details about the burst Register Address
output mode. D15 D14 D13 D12 Mnemonic Name
0 0 0 0 CREG Control bits
SERIAL INTERFACE
0 0 0 1 NINCR Number of
The AD5930 has a standard 3-wire serial interface, which is increments
compatible with SPI®, QSPI™, MICROWIRE™, and DSP 0 0 1 0 ∆f Lower 12 bits of delta
interface standards. frequency
0 0 1 1 ∆f Higher 12 bits of
Data is loaded into the device as a 16-bit word under the delta frequency
control of a serial clock input, SCLK. The timing diagram for 0 1 tINT Increment interval
this operation is given in Figure 4. 1 0 TBURST Burst interval
1 1 0 0 FSTART Lower 12 bits of start
The FSYNC input is a level-triggered input that acts as a frame frequency
synchronization and chip enable. Data can only be transferred 1 1 0 1 FSTART Higher 12 bits of start
into the device when FSYNC is low. To start the serial data frequency
transfer, FSYNC should be taken low, observing the minimum 1 1 1 0 Reserved
FSYNC to SCLK falling edge setup time, t7. After FSYNC goes 1 1 1 1 Reserved
low, serial data is shifted into the device's input shift register on
the falling edges of SCLK for 16 clock pulses. FSYNC can be
The Control Register
taken high after the 16th falling edge of SCLK, observing the
minimum SCLK falling edge to FSYNC rising edge time, t8. The AD5930 contains a 12-bit control register (see Table 6) that
Alternatively, FSYNC can be kept low for a multiple of 16 SCLK sets up the operating modes of the AD5930. The different
pulses, and then brought high at the end of the data transfer. In functions and the various output options from the AD5930 are
this way, a continuous stream of 16-bit words can be loaded while controlled by this register.
FSYNC is held low. FSYNC should only go high after the 16th Table 7 describes the individual bits of the control register.
SCLK falling edge of the last word is loaded.
To address the control register, D15 to D12 of the 16-bit serial
The SCLK can be continuous, or, alternatively, the SCLK can word must be set to 0.
idle high or low between write operations.
Table 6. Control Register
POWERING UP THE AD5930 D15 D14 D13 D12 D11 to D0
When the AD5930 is powered up, the part is in an undefined 0 0 0 0 Control Bits
state, and therefore, must be reset before use. The eight registers
(control and frequency) contain invalid data and need to be set
to a known value by the user. The control register should be the
first register to be programmed, as this sets up the part. Note
that a write to the control register automatically resets the
internal state machines and provides an analog output of
midscale as it provides the same function as the INTERRUPT
pin. Typically, this is followed by a serial loading of all the
required sweep parameters. The DAC output remains at
midscale until a sweep is started using the CTRL pin.

Rev. A | Page 17 of 28
AD5930 Data Sheet
Table 7. Description of Bits in the Control Register
Bit Name Function
D15 ADDR Register address bits.
to
D12
D11 B24 Two write operations are required to load a complete word into the FSTART register and the Δf register.
When B24 = 1, a complete word is loaded into a frequency register in two consecutive writes. The first write
contains the 12 LSBs of the frequency word and the next write contains the 12 MSBs. Refer to Table 5 for the
appropriate addresses. The write to the destination register occurs after both words have been loaded, so the
register never holds an intermediate value.
When B24 = 0, the 24-bit FSTART /Δf register operates as two 12-bit registers, one containing the 12 MSBs and the
other containing the 12 LSBs. This means that the 12 MSBs of the frequency word can be altered independent of
the 12 LSBs and vice versa. This is useful if the complete 24-bit update is not required. To alter the 12 MSBs or the
12 LSBs, a single write is made to the appropriate register address. Refer to Table 5 for the appropriate addresses.
D10 DAC ENABLE When DAC ENABLE = 1, the DAC is enabled.
When DAC ENABLE = 0, the DAC is powered down. This saves power and is beneficial when only using the MSB of
the DAC input data (available at the MSBOUT pin).
D9 SINE/TRI The function of this bit is to control what is available at the IOUT/IOUTB pins.
When SINE/TRI = 1, the SIN ROM is used to convert the phase information into amplitude information resulting in a
sinusoidal signal at the output.
When SINE/TRI = 0, the SIN ROM is bypassed, resulting in a triangular (up-down) output from the DAC.
D8 MSBOUTEN When MSBOUTEN = 1, the MSBOUT pin is enabled.
When MSBOUTEN = 0, the MSBOUT is disabled (tri-state).
D7 CW/BURST When CW/BURST = 1, the AD5930 outputs each frequency continuously for the length of time or number of output
waveform cycles specified in the appropriate register, TBURST.
When CW/BURST = 0, the AD5930 bursts each frequency for the length of time/number of cycles specified in the
burst register, TBURST. For the remainder of the time within each increment window (TBURST − tINT), the AD5930
outputs a DC value of midscale. In external increment mode, it is defined by the pulse widths on the CTRL pin.
D6 INT/EXT This bit is active when D7 = 0 and is also used in conjunction with D5. When the user is incrementing the frequency
BURST externally (D5 = 1), D6 dictates whether the user is controlling the burst internally or externally.
When INT/EXT BURST = 1, the output burst is controlled externally through the CTRL pin. This is useful if the user is
using an external source to both trigger the frequency increments and determine the burst interval.
When INT/EXT BURST = 0, the output burst is controlled internally. The burst is pre-programmed by the user into
the TBURST register (the burst interval can either be clock-based or for a specified number of output cycles).
When D5 = 0, this bit is ignored.
D5 INT/EXT When INT/EXT INCR = 1, the frequency increments are triggered externally through the CTRL pin.
INCR When INT/EXT INCR = 0, the frequency increments are triggered automatically.
D4 MODE The function of this bit is to control what type of frequency sweep is carried out.
When MODE = 1, the frequency profile is a saw sweep.
When MODE = 0, the frequency profile is a triangular (up-down) sweep.
D3 SYNCSEL This bit is active when D2 = 1. It is user-selectable to pulse at the end of sweep (EOS) or at each frequency
increment.
When SYNCSEL = 1, the SYNCOP pin outputs a high level at the end of the sweep and returns to zero at the start of
the subsequent sweep.
When SYNCSEL= 0, the SYNCOP outputs a pulse of 4 × TCLOCK only at each frequency increment.
D2 SYNCOUTEN When SYNCOUTEN= 1, the SYNC output is available at the SYNCOP pin.
When SYNCOUTEN= 0, the SYNCOP pin is disabled (tri-state).
D1 Reserved This bit must always be set to 1.
D0 Reserved This bit must always be set to 1.

Rev. A | Page 18 of 28
Data Sheet AD5930
SETTING UP THE FREQUENCY SWEEP Number of Increments (NINCR)
As stated previously in The Frequency Profile section, the An end frequency, or a maximum/minimum frequency before
AD5930 requires certain registers to be programmed to enable a the sweep changes direction is not required on the AD5930.
frequency sweep. The following sections discuss these registers Instead, this end frequency is calculated by multiplying the
in more detail. frequency increment value (Δf) by the number of frequency
steps (NINCR), and adding it to/subtracting it from the start
Start Frequency (FSTART) frequency (FSTART), that is, FSTART + NINCR × Δ f. The NINCR register
To start a frequency sweep, the user needs to tell the AD5930 is a 12-bit register, with the address shown in Table 10.
what frequency to start sweeping from. This frequency is stored Table 10. NINCR Register Bits
in a 24-bit register called FSTART. If the user wishes to alter the
D15 D14 D13 D12 D11 to D0
entire contents of the FSTART register, two consecutive writes
0 0 0 1 12 bits of NINCR <11…0>
must be performed, one to the LSBs and the other to the MSBs.
Note that for an entire write to this register, the Control Bit B24 The number of increments is programmed in binary fashion,
(D11) should be set to 1 with the LSBs programmed first. with 000000000010 representing the minimum number of
frequency increments (2 increments), and 111111111111
In some applications, the user does not need to alter all 24 bits representing the maximum number of increments (4095).
of the FSTART register. By setting the Control Bit B24 (D11) to 0,
Table 11. NINCR Data Bits
the 24-bit register operates as two 12-bit registers, one
D11 D0 Number of Increments
containing the 12 MSBs and the other containing the 12 LSBs.
This means that the 12 MSBs of the FSTART word can be altered 0000 0000 0010 2 frequency increments. This is the
minimum number of frequency
independently of the 12 LSBs, and vice versa. The addresses of increments.
both the LSBs and the MSBs of this register is given in Table 8. 0000 0000 0011 3 frequency increments.
Table 8. FSTART Register Bits 0000 0000 0100 4 frequency increments.
D15 D14 D13 D12 D11 to D0 … … … …
1 1 0 0 12 LSBs of FSTART <11…0> 1111 1111 1110 4094 frequency increments.
1 1 0 1 12 MSBs of FSTART <23…12> 1111 1111 1111 4095 frequency increments.
Frequency Increments (Δf) Increment Interval (tINT)
The value in the Δf register sets the increment frequency for the The increment interval dictates the duration of the DAC output
sweep and is added incrementally to the current output frequency. signal for each individual frequency of the frequency sweep.
Note that the increment frequency can be positive or negative, The AD5930 offers the user two choices:
thereby giving an increasing or decreasing frequency sweep.
 The duration is a multiple of cycles of the output frequency.
At the start of a sweep, the frequency contained in the FSTART
 The duration is a multiple of MCLK periods.
register is output. Next, the frequency (FSTART + Δf ) is output.
This is followed by (FSTART + Δf + Δf) and so on. Multiplying the This is selected by Bit D13 in the tINT register as shown in Table 12.
Δf value by the number of increments (NINCR), and adding it to
Table 12. tINT Register Bits
the start frequency (FSTART), gives the final frequency in the
sweep. Mathematically this final frequency/stop frequency is D15 D14 D13 D12 D11 D10 to D0
represented by 0 1 0 x x 11 bits <10…0>
Fixed number of output
FSTART + (NINCR × Δf). waveform cycles.
0 1 1 x x 11 bits <10…0>
The Δf register is a 23-bit register, and requires two 16-bit Fixed number of clock
writes to be programmed. Table 9 gives the addresses associated periods.
with both the MSB and LSB registers of the Δf word.
Programming of this register is in binary form with the
Table 9. Δf Register Bits minimum number being decimal 2. Note in Table 12 that 11
Sweep bits, Bit D10 to Bit D0, of the register are available to program
D15 D14 D13 D12 D11 D10 to D0 Direction the time interval. As an example, if MCLK = 50 MHz, then each
0 0 1 0 12 LSBs of Δf N/A clock period/base interval is (1/50 MHz) = 20 ns. If each
<11…0> frequency needs to be output for 100 ns, then <00000000101>
0 0 1 1 0 11 MSBs of Positive Δf or decimal 5 needs to be programmed to this register. Note that
Δf <22…12> (FSTART + Δf ) the AD5930 can output each frequency for a maximum
0 0 1 1 1 11 MSBs of Negative f duration of 211 −1 (or 2047) times the increment interval.
Δf <22…12> (FSTART − Δf )

Rev. A | Page 19 of 28
AD5930 Data Sheet
Therefore, in this example, a time interval of 20 ns × 2047 = 40 μs Table 14. TBURST Register Bits
is the maximum, with the minimum being 40 ns. For some D15 D14 D13 D12 D11 D10 to D0
applications, this maximum time of 40 μs may be insufficient. 1 0 0 x x 11 bits of <0…10>
Therefore, to cater for sweeps that need a longer increment Fixed number of output
interval, time-base multipliers are provided. Bit D12 and Bit D11 waveform cycles.
are dedicated to the time-base multipliers (see Table 12). A more 1 0 1 x x 11 bits of <0…10>
detailed table of the multiplier options is given in Table 13. Fixed number of clock
periods.
Table 13. Time-Base Multiplier Values
However, note that when using both the increment interval
D12 D11 Multiplier Value
(tINT) and burst time register (TBURST), the settings for Bit D13
0 0 Multiply (1/MCLK) by 1
should be the same. In instances where they differ, the AD5930
0 1 Multiply (1/MCLK) by 5
defaults to the value programmed into the tINT register.
1 0 Multiply (1/MCLK) by 100
Similarly, Bit 12 and Bit 11, the time-base multiplier bits, always
1 1 Multiply (1/MCLK) by 500
default to the value programmed into the tINT register.
If MCLK is 50 MHz and a multiplier of 500 is used, then the
base interval (TBASE) is now (1/(50 MHz) x 500)) = 10 μs. Using ACTIVATING AND CONTROLLING THE SWEEP
a multiplier of 500, the maximum increment interval is 10 μs × After the registers have been programmed, a 0 ≥ 1 transition on
211 − 1 = 20.5 ms. Therefore, the option of time-base multipliers the CTRL pin starts the sweep. The sweep always starts from
gives the user enhanced flexibility when programming the the frequency programmed into the FSTART register. It changes by
length of the frequency window, because any frequency can be the value in the F register and increases by the number of
output for a minimum of 40 ns up to a maximum of 20.5 ms. steps in the NINCR register. However, both the time interval and
burst duration of each frequency can be internally controlled
Length of Sweep Time
using the tINT and TBURST registers, or externally using the CTRL
The length of time to complete a user-programmed frequency pin. The options available are:
sweep is given by the following equation:
1. auto-increment, auto-burst control
TSWEEP = (1 + NINCR) × TBASE
2. external increment, auto-burst control
Burst Time Resister (TBURST)
As previously described in the Burst Output Mode section, the 3. external increment, external burst control
AD5930 offers the user the ability to output each frequency in
1. Auto-Increment, Auto-Burst Control
the sweep for a length of time within the increment interval
(tINT), and then return to midscale for the remainder of the time The values in the tINT and TBURST registers are used to control the
(tINT – TBURST) before stepping to the next frequency. The burst sweep. The AD5930 bursts each frequency for the length of
option must be enabled. This is done by setting Bit D7 in the time programmed in the TBURST register, and outputs midscale
control register to 0. for the remainder of the interval time (tINT – TBURST).

Similar to the time interval register, the burst register can have To set up the AD5930 to this mode, CW/BURST (Bit D7) in the
its duration as: control register must be set to 0, INT/EXT BURST (Bit D6)
must be set to 0, and INT/EXT INCR (Bit D5) must be set to 0.
 A multiple of cycles of the output frequency Note that if the part is only operating in continuous mode, then
(Bit D7) in the control register should be set to 1.
 A multiple of MCLK periods
2. External Increment, Auto-Burst Control
The address for this register is given in Table 14.
The time interval, tINT, is set by the pulse rate on the CTRL pin.
The first 0 ≥1 transition on the pin starts the sweep. Each
subsequent 0 ≥1 transition on the CTRL pin increments the
output frequency by the value programmed into the F register.
For each increment interval, the AD5930 outputs each
frequency for the length of time programmed into the TBURST
register, and outputs midscale until the CTRL pin is pulsed
again. Note that for this mode, the values programmed into Bit
D13, Bit D12, and bit D11 of the TBURST register are used.

Rev. A | Page 20 of 28
Data Sheet AD5930
To setup the AD5930 to this mode, CW/BURST (Bit D7) in the OUTPUTS FROM THE AD5930
control register must be set to 0, INT/EXT BURST (Bit D6) The AD5930 offers a variety of outputs from the chip. The analog
must be set to 0, and INT/EXT INCR (Bit D5) must be set to 1. outputs are available from the IOUT/IOUTB pins, and include a
Note that if the part is only operating in continuous mode, then sine wave and a triangle output. The digital outputs are available
Bit D7 in the control register should be set to 1. from the MSBOUT pin and the SYNCOUT pin.
3. External Increment, External Burst Control: Analog Outputs
Both the increment interval (tINT) and the burst interval (TBURST) Sinusoidal Output
are controlled by the CTRL pin. A 0 ≥ 1 transition on the CTRL
pin starts the sweep. The duration of CTRL high then dictates The SIN ROM is used to convert the phase information from
the length of time the AD5930 bursts that frequency. The low the frequency register into amplitude information, which results
time of CTRL is the “listen” time, that is, how long the part in a sinusoidal signal at the output. To have a sinusoidal output
remains at midscale. Bringing the CTRL pin high again initiates a from the IOUT/IOUTB pins, set Bit SINE/TRI (Bit D9) to 1.
frequency increment, and the pattern continues. For this mode, Triangle Output
the settings for Bit D13, Bit D12, and Bit D11 are ignored.
The SIN ROM can be bypassed so that the truncated digital
To setup the AD5930 to this mode, CW/BURST (Bit D7) in the output from the NCO is sent to the DAC. In this case, the
control register must be set to 0, INT/EXT BURST (Bit D6) output is no longer sinusoidal. The DAC produces a 10-bit
must be set to 1, and INT/EXT INCR (Bit D5) must be set to 1. linear triangular function. To have a triangle output from the
Note that if the part is only operating in continuous mode, then IOUT/IOUTB pins, set Bit SINE/TRI (D9) to 0. Note that the
Bit D7 in the control register should be set to 1. DAC ENABLE bit (D10) must be 1 (that is, the DAC is enabled)
when using these pins.
Interrupt Pin
p/2 5p/2 9p/2
This function is used as an interrupt during a frequency sweep. VOUT MAX

A low-to-high transition on this pin is sampled by the internal

05333-012
VOUT MIN
MCLK, thereby resetting internal state machines, which results 3p/2 7p/2 11p/2
in the output going to midscale. Figure 34. Triangle Output

Standby Pin Digital Outputs

Sections of the AD5930 that are not in use can be powered Square Wave Output from MSBOUT
down to minimize power consumption. This is done by using
The inverse of the MSB from the NCO can be output from the
the STANDBY pin. For the optimum power savings, it is
AD5930. By setting the MSBOUTEN (D8) control bit to 1, the
recommended to reset the AD5930 before entering standby,
inverted MSB of the DAC data is available at the MSBOUT pin.
because doing so reduces the power-down current to 20 µA.
This is useful as a digital clock source.
When this pin is high, the internal MCLK is disabled, and the DVDD
reference, DAC, and regulator are powered down. When in this

05333-013
state, the DAC output of the AD5930 remains at its present DGND
value as the NCO is no longer accumulating. When the device Figure 35. MSB Output
is taken back out of standby mode, the MCLK is re-activated
and the sweep continues. To ensure correct operation for new SYNCOUT Pin
data, it is recommended that the device be internally reset using The SYNCOUT pin can be used to give the status of the sweep.
a control register write or using the INTERRUPT pin, and then It is user selectable for the end of the sweep, or to output a 4 ×
restarted. TCLOCK pulse at frequency increments. The timing information
for both of these modes is shown in Figure 6 and Figure 7.

The SYNCOUT pin must be enabled before use. This is done

using Bit D2 in the control register. The output available from
this pin is then controlled by Bit D3 in the control register. See
Table 5 for more information.

Rev. A | Page 21 of 28
AD5930 Data Sheet

APPLICATIONS
GROUNDING AND LAYOUT Proper operation of the comparator requires good layout
The printed circuit board that houses the AD5930 should be strategy. The strategy must minimize the parasitic capacitance
designed so that the analog and digital sections are separated between VIN and the SIGN BIT OUT pin by adding isolation
and confined to certain areas of the board. This facilitates the using a ground plane. For example, in a multilayered board, the
use of ground planes that can be easily separated. A minimum VIN signal could be connected to the top layer and the SIGN
etch technique is generally best for ground planes because it BIT OUT connected to the bottom layer, so that isolation is
gives the best shielding. Digital and analog ground planes provided between the power and ground planes.
should only be joined in one place. If the AD5930 is the only Interfacing to Microprocessors
device requiring an AGND to DGND connection, then the
The AD5930 has a standard serial interface that allows the part
ground planes should be connected at the AGND and DGND
to interface directly with several microprocessors. The device
pins of the AD5930. If the AD5930 is in a system where
uses an external serial clock to write the data/control
multiple devices require AGND to DGND connections, the
information into the device. The serial clock can have a
connection should be made at one point only, a star ground
frequency of 40 MHz maximum. The serial clock can be
point that should be established as close as possible to the
continuous, or it can idle high or low between write operations.
AD5930.
When data/control information is being written to the AD5930,
Avoid running digital lines under the device as these couple FSYNC is taken low and is held low while the 16 bits of data are
noise onto the die. The analog ground plane should be allowed being written into the AD5930. The FSYNC signal frames the
to run under the AD5930 to avoid noise coupling. The power 16 bits of information being loaded into the AD5930.
supply lines to the AD5930 should use as large a track as
possible to provide low impedance paths and reduce the effects
AD5930 TO ADSP-21xx INTERFACE
of glitches on the power supply line. Fast switching signals, such Figure 36 shows the serial interface between the AD5930 and
as clocks, should be shielded with digital ground to avoid the ADSP-21xx. The ADSP-21xx should be set up to operate in
radiating noise to other sections of the board. Avoid crossover the SPORT transmit alternate framing mode (TFSW = 1). The
of digital and analog signals. Traces on opposite sides of the ADSP-21xx are programmed through the SPORT control
board should run at right angles to each other. This reduces the register and should be configured as follows:
effects of feedthrough through the board. A microstrip
1. Internal clock operation (ISCLK = 1)
technique is by far the best, but is not always possible with a
double-sided board. In this technique, the component side of 2. Active low framing (INVTFS = 1)
the board is dedicated to ground planes, while signals are placed
on the other side. 3. 16-bit word length (SLEN = 15)

Good decoupling is important. The analog and digital supplies 4. Internal frame sync signal (ITFS = 1)
to the AD5930 are independent and separately pinned out to
5. Generate a frame sync for each write (TFSR = 1)
minimize coupling between analog and digital sections of the
device. All analog and digital supplies should be decoupled to Transmission is initiated by writing a word to the Tx register
AGND and DGND, respectively, with 0.1 µF ceramic capacitors after the SPORT has been enabled. The data is clocked out on
in parallel with 10 µF tantalum capacitors. To achieve the best each rising edge of the serial clock and clocked into the AD5930
from the decoupling capacitors, they should be placed as close on the SCLK falling edge.
as possible to the device, ideally right up against the device. In
systems where a common supply is used to drive both the ADSP-2101/ AD59301
ADSP-21031
AVDD and DVDD of the AD5930, it is recommended that the
system’s AVDD supply be used. This supply should have the TFS FSYNC
recommended analog supply decoupling between the AVDD DT SDATA
pins of the AD5930 and AGND, and the recommended digital SCLK SCLK
supply decoupling capacitors between the DVDD pins and
05333-038

DGND.
1ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 36. ADSP-2101/ADSP-2103 to AD5930 Interface

Rev. A | Page 22 of 28
Data Sheet AD5930
AD5930 TO 68HC11/68L11 INTERFACE a second write operation is initiated to transmit the second byte
Figure 37 shows the serial interface between the AD5930 and of data. P3.3 is taken high following the completion of the
the 68HC11/68L11 µcontroller. The µcontroller is configured as second write operation. SCLK should idle high between the two
the master by setting bit MSTR in the SPCR to 1, which write operations. The 80C51/80L51 outputs the serial data in an
provides a serial clock on SCK while the MOSI output drives LSB first format. The AD5930 accepts the MSB first (the 4
the serial data line SDATA. Since the µcontroller does not have MSBs being the control information, the next 4 bits being the
a dedicated frame sync pin, the FSYNC signal is derived from a address while the 8 LSBs contain the data when writing to a
port line (PC7). The setup conditions for correct operation of destination register). Therefore, the transmit routine of the
the interface are as follows: 80C51/80L51 must take this into account and rearrange the bits
so that the MSB is output first.
1. SCK idles high between write operations (CPOL = 0)
80C51/80L511 AD59301
2. Data is valid on the SCK falling edge (CPHA = 1)

When data is being transmitted to the AD5930, the FSYNC line P3.3 FSYNC

is taken low (PC7). Serial data from the 68HC11/68L11 is RXD SDATA

transmitted in 8-bit bytes with only eight falling clock edges TXD SCLK

05333-040
occurring in the transmit cycle. Data is transmitted MSB first.
In order to load data into the AD5930, PC7 is held low after the 1ADDITIONAL PINS OMITTED FOR CLARITY.
first 8 bits are transferred and a second serial write operation is
Figure 38. 80C51/80L51 to AD5930 Interface
performed to the AD5930. Only after the second 8 bits have
been transferred should FSYNC be taken high again. AD5930 TO DSP56002 INTERFACE
68HC11/68L111 AD59301 Figure 39 shows the interface between the AD5930 and the
DSP56002. The DSP56002 is configured for normal mode,
asynchronous operation with a gated internal clock (SYN = 0,
PC7 FSYNC
GCK = 1, SCKD = 1). The frame sync pin is generated internally
MOSI SDATA
(SC2 = 1), the transfers are 16 bits wide (WL1 = 1, WL0 = 0), and
SCK SCLK
the frame sync signal frames the 16 bits (FSL = 0). The frame
05333-039

sync signal is available on Pin SC2, but needs to be inverted

1ADDITIONAL PINS OMITTED FOR CLARITY.
before being applied to the AD5930. The interface to the
Figure 37. 68HC11/68L11 to AD5930 Interface
DSP56000/DSP56001 is similar to that of the DSP56002.

AD5930 TO 80C51/80L51 INTERFACE DSP560021 AD59301

Figure 38 shows the serial interface between the AD5930 and
the 80C51/80L51 µcontroller. The µcontroller is operated in SC2 FSYNC
mode 0 so that TXD of the 80C51/80L51 drives SCLK of the STD SDATA
AD5930, while RXD drives the serial data line SDATA. The SCK SCLK
FSYNC signal is again derived from a bit programmable pin on 05333-041

the port (P3.3 being used in the diagram). When data is to be

transmitted to the AD5930, P3.3 is taken low. The 80C51/80L51 1ADDITIONAL PINS OMITTED FOR CLARITY.
transmits data in 8-bit bytes, thus, only eight falling SCLK edges
occur in each cycle. To load the remaining 8 bits to the AD5930, Figure 39. DSP56002 to AD5930 Interface
P3.3 is held low after the first 8 bits have been transmitted, and

Rev. A | Page 23 of 28
AD5930 Data Sheet
EVALUATION BOARD Using the AD5930 Evaluation Board
The AD5930 evaluation board allows designers to evaluate the high The AD5930 evaluation kit is a test system designed to simplify
performance AD5930 DDS modulator with minimum effort. the evaluation of the AD5930. An application note is also
available with the evaluation board and gives full information
The evaluation board interfaces to the USB port of a PC. It is on operating the evaluation board.
possible to power the entire board off the USB port. All that is
needed to complete the evaluation of the chip is either a Prototyping Area
spectrum analyzer or a scope. An area is available on the evaluation board for the user to add
additional circuits to the evaluation test set. Users may want to
The DDS evaluation kit includes a populated and tested
build custom analog filters for the output or add buffers and
AD5930 printed circuit board. The EVAL-AD5930EB kit is
operational amplifiers to be used in the final application.
shipped with a CD-ROM that includes self-installing software.
The PC is connected to the evaluation board using the supplied XO vs. External Clock
cable. The software is compatible with Microsoft® Windows® The AD5930 can operate with master clocks up to 50 MHz. A
2000 and Windows XP. 50 MHz oscillator is included on the evaluation board.
A schematic of the evaluation board is shown in Figure 40 and However, this oscillator can be removed and, if required, an
Figure 41. external CMOS clock can be connected to the part.

Rev. A | Page 24 of 28
 SCHEMATIC
Data Sheet

02
A K
1 GL2 2 R3 LED
1kΩ 3.3V C12
GROUND LINK R0603 0.1µF
C0603 3.3V
R17
ADP3303-3.3 C10 0Ω
2.2µF R0603
8 1 RTAJ_A
IN1 VCC 3.3V 3.3V
+ C9 C8 7 2
10µF 0.1µF IN2 WP +
5 6
RTAJ_A C0603 SD SCL R4 R17
3 100kΩ 100kΩ 3.3V
NR
GND R0603 R0603
C5 C7
4 U3 0.1µF 0.1µF
C0603 C0603
C3 C4

3
7
11
17
27
32
43
55
0.1µF 0.1µF
C0603 C0603
18

VCC
VCC
VCC
VCC
VCC
VCC
VCC
PB0/FD0

AVCC
19
PB1/FD1 3.3V
20
PB2/FD2
42 RESET 21
PB3/FD3
44 22 C11
*WAKEUP PB4/FD4 10µF
23
PB5/FD5 RTAJ_A
24
J1 PB6/FD6
54 25
CLKOUT PB7/FD7 +
USB-MINI-B 45
1
PD0/FD8
VBUS 46
U4 PD1/FD9
2 9 47 3.3V
SHIELD D– D– CY7C68013-CS P PD2/FD10
3 8 48 C6
D+ D+ PD3/FD11 22pF
4 49 3.3V
IO PD4/FD12 C0603
5 50
GND 33 PD5/FD13 24LC01 R2 R1
PA0/INT0 51
PD6/FD14 2.2kΩ 2.2kΩ
34 52

Rev. A | Page 25 of 28
PA1/INT1 PD7/FD15 1 8
35 A0 VCC R0603 R0603
STANDBY PA2/*SLOE 2 7
36 A1 WP
INTERRUPT PA3/*WU2 3 6
37 29 A2 SCL
CTRL PA4/FIFOADR0 CTL0/*FLAGA 4 5
38 30 VSS SDA
SDATA PA5/FIFOADR1 CTL1/*FLAGB
39 31
SCLK PA6/*PKTEND CTL2/*FLAGC
FSYNC 40 SDA SCL

Figure 40. Page 1 of EVAL-AD5930EB Schematic

PA7/*FLD/SLCS
3.3V
16
SDA
1 15
RDY0/*SLRD SCL
2
C28 C30 C32 C33 C34 C35 C36 RDY1/*SLWR
0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 13 4
IFCLK XTALOUT
14
RSVD
5
XTALIN
Y1
AGND
GND
GND
GND
GND
GND
GND
GND

3.3V
6

24MHz
10
12
26
28
41
53
56

T3 T4 T5
C1 C2
22pF 22pF
T6 T7 C0603 C0603

05333-023
AD5930
 AD5930

T21 T22
R16
DVDD LK1 3.3V L1 1.5kΩ LK8 AVDD
T23 T24
A B BEAD 1 2 B A
J2–1 J14–1
FSYNC SCLK SDATA DVDD AVDD
DGND AGND
C14 C13 C29 C31
J3 J4 J5 0.1µF 10µF 10µF 0.1µF
J2–2 J14–2
C0603 RTAJ_A RTAJ_A C0603

3
6
10
13
C16
10µF

S1B
S2B
S3B
S4B
16
RTAJ_A REF
DVDD DVDD VDD DVDD REF
2 4 +
C37 FSYNC S1A D1
5 7 C15 C22
0.1µF SCLK S2A D2 AVDD J15
11 9 0.1µF 0.1µF
C0603 SDATA S3A D3 C19 C0603
14 12 C0603
S4A D4 10µF
IN EN GND RTAJ_A IOUT
IOUT

1
8
ADG774

15
LK2 T26 +
FS_A C24 R7
DVDD C17 LK7 C20 200Ω J11
A B C0603
0.1µF 0.1µF R0603
C0603 C0603
C21 R6
6.8kΩ IOUTB
C0603 IOUTB

6
5
4
R0603
CTRL LK4 CTRL FSYNC
CAP/2.5V DVDD AVDD C25 R8
CTRL SCLK 200Ω J12
R10 A B 16 1 C0603
J6 10kΩ SDATA FSYNC FSADJUST C23 R0603
R0603 15 2 0.01µF

Rev. A | Page 26 of 28
SCLK REF C0603
14 3 MSBOUT
SDATA COMP AVDD MSBOUT
INTERRUPT LK5 INT U1
13 AD5930 19 C26
INTERRUPT CTRL IOUT J10
R11 A B 12 20 C0603
J7 10kΩ INTERRUPT IOUTB
17

Figure 41. Page 2 of EVAL-AD5930EB Schematic

R0603 STANDBY
10 SYNCOUT
MSBOUT SYNCOUT
8 9
STANDBY LK6 STANDBY MCLK SYNCOUT
C18 J9
STANDBY DGND O/P DGND AGND C0603
R12 A B
J8
7

10kΩ
11
18

R0603
SURFACE MOUNT AREA
T25 THROUGH HOLE AREA
MCLK GL1
MCLK LK6
8 14 GROUND LINK
O/P VDD DVDD
R9 A B R15 U7 C17
J13 49.9kΩ R0603 50MHZ_XTAL 0.1µF
R0603 7 C0603
GND

05333-024
Data Sheet
Data Sheet AD5930

OUTLINE DIMENSIONS
6.60
6.50
6.40

20 11

4.50
4.40
4.30
6.40 BSC
1 10

PIN 1
0.65
BSC
0.15 1.20 MAX 0.20
0.05 0.09 0.75
8° 0.60
0.30
0° 0.45
COPLANARITY 0.19 SEATING
0.10 PLANE

COMPLIANT TO JEDEC STANDARDS MO-153-AC

Figure 42. 20-Lead Thin Shrink Small Outline Package (TSSOP)

(RU-20)
Dimensions shown in millimeters

ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD5930YRUZ −40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20
AD5930YRUZ-REEL7 −40°C to +105°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20
EVAL-AD5930EBZ Evaluation Board
1
Z = RoHS Compliant Part.

Rev. A | Page 27 of 28
AD5930 Data Sheet

NOTES

© 2005–2012 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D05333-0-2/12(A)

Rev. A | Page 28 of 28