BULETINUL INSTITUTULUI POLITEHNIC DIN IAŞI

Publicat de
Universitatea Tehnică „Gheorghe Asachi” din Iaşi
Tomul LXI (LXV), Fasc. 2, 2015
Secţia
ELECTROTEHNICĂ. ENERGETICĂ. ELECTRONICĂ

CMOS SCHMITT TRIGGER WITH

CURRENT-CONTROLLED HYSTERESIS
BY

DAMIAN IMBREA*

Technical University “Gheorghe Asachi” of Iaşi,

Department of Electronics,Telecommunications and Information Technology

Received: June10, 2015

Accepted for publication: June 30, 2015

Abstract. A new topology of Schmitt trigger circuit is proposed; the

hysteresis can be adjusted by means of a bias current. The circuit is designed in
65 nm CMOS standard process and operates at 1 V (± 10%) supply voltage in
the temperature range [–40, +125] °C. It can be used in both digital and analog
applications up to 5 GHz input frequency. The silicon area occupied by the
circuit is less than 21 µm2.
Key words: hysteresis; Schmitt trigger; threshold control; process corners.

1. Introduction
Several configurations of Schmitt trigger circuits have been proposed.
Some of them are shown in Fig. 1; all these schematics include enhancement-
mode transistors only. The threshold voltages VtL and VtH specific to a Schmitt
trigger, also called Low and High switching thresholds, are dependent on the
process variations, supply voltage and temperature. The frequency of the input
signal Vin also affects VtL and VtH due to the intrinsic parasitic capacitors (not
represented in Fig. 1).
Explanations and switching threshold calculations relating to the
circuits in Fig. 1 a, b, c can be found in (Dokic, 2012). It can be seen that the
*
Corresponding author: e-mail: dimbrea@etti.tuiasi.ro
62 Damian Imbrea

schematic in Fig. 1 c is derived from the one in Fig. 1 a by removing two

PMOS transistors; a similar way to get another trigger circuit, starting from that
in Fig. 1 a, is to remove two NMOS transistors.

Fig. 1 – Configurations of CMOS Schmitt trigger circuits.

The circuits depicted in Fig. 1 d, e, f) are taken, in this order, from

(Madhuri et al., 2012; Arith et al., 2013; Saxena et al., 2014). The last two
schematics may also be regarded as derived from that in Fig. 1 a, the circuit
which is known as “conventional” Schmitt trigger.
The trigger described in (Singhanath et al., 2011) is based on dynamic
body biasing technique and consists of three stage CMOS inverters. The
switching thresholds can be independently adjusted by controlling the body
potential.
 Bul. Inst. Polit. Iaşi, t. LXI (LXV), f. 2, 2015 63

A differential Schmitt trigger with tunable hysteresis is presented in

(Yuan, 2010). The core of this circuit is a cross-coupled inverter pair. The
hysteresis (i.e., the difference VtH – VtL) can be adjusted by varying the current
through symmetrical loads.
The trigger described below has one input and one output, as those in
Fig. 1. An external bias current is used to control the hysteresis. To some extent,
the bias current is a means to compensate for process variations, supply voltage
and temperature.

2. Circuit Description
The schematic of the proposed Schmitt trigger, shown in Fig. 2, contains
the inverters N1–P1, N2–P2 and the current sources P5 and P3. The second
inverter N2–P2 is supplied directly from VDD while the first inverter N1–P1 is
supplied from the current sources P5 and P3. Except for P4 and P5 which have
long channels, all other transistors have short channels (i.e., minimum or close
to the minimum length, specific to core devices), in order to achieve an
operating speed as high as possible. The intrinsic capacitors C1, C2 do influence
the switching thresholds at high frequencies; C1 and C2 are mainly gate
capacitors and can be approximated by the relations
C1  C gN2  C gP2 ,C2  C gP3  C Inv (1)

where: CInv is the input capacitance of the inverter named Inv.

Fig. 2 – Schematic of the proposed Schmitt trigger.

The functional description and calculation of the circuit switching

thresholds VtL and VtH will be done by means of the time diagrams illustrated in
64 Damian Imbrea

Fig. 3; these waveforms are taken from a low-frequency transient simulation.

Fig. 3 – Waveforms specific to the proposed Schmitt trigger.

At low values (close to VSS) of the input voltage Vin the transistor N1 is
off (I1 = 0); all this time the transistors P1, P3, P5 are working in the triode region
at zero drain current and the voltages V1, V3 are close to VDD. Increasing Vin will
determine N1 to enter the active (or saturation) region, while P1, P3 and P5
 Bul. Inst. Polit. Iaşi, t. LXI (LXV), f. 2, 2015 65

remain in the triode region. When Vin reaches the high threshold VtH, the
transistors P1, P3 and P5 enter the active region. At this moment the current
through P5 is equal to Ib, V1 falls approximately to 0.5 V and N1 is still active;
also, V2 reaches about 0.15 V and V3 drops to about 0.8 V.
From Fig. 2 (at low frequencies) it follows that
I1  I b  I 3 . (2)
For both transistors N1 and P3, working in strong inversion, we can
evaluate the drain currents by using the square law
1 W
I D   Cox (| VGS |  | Vth 0 |) 2 (1   | VDS |) , (3)
2 L
where µ, Cox, W/L, Vth0 and λ are, respectively, the mobility of charge carriers,
the gate-oxide capacitor per unit area, the channel width/length ratio, the
threshold voltage with VBS = 0 V (body-source voltage) and the channel-length
modulation coefficient.
By combining (2) and (3) we get successively
1 W
n Coxn 1 (VtH  Vthn0 ) 2 (1  1 0.5VDD ) 
2 L1
, (4)
1 W
 I b   p Coxp 3 (0.85VDD  Vthp0 ) 2 (1  3 0.2VDD ),
2 L3

1 W
I b   p Coxp 3 (0.85VDD  Vthp0 ) 2 (1  3 0.2VDD )
2 L3
VtH  Vthn0  . (5)
1 W
 n Coxn 1 (1  1 0.5VDD )
2 L1

After Vin exceeds the threshold VtH, the following will happen: P 3 turns
off, N1 enters the triode region and P 5 remains active (I1 = Ib). Further, while Vin
increases to VDD, P5 enters the triode region and then it turns off.
Decreasing Vin from VDD to VSS will determine V3 to decrease almost
linearly, P5 to go successively in the triode and then in the active regions, and
N1 to enter the triode region; until Vin reaches the low threshold VtL, P3 remains
off. When Vin equals VtL, the transistor N1 becomes active (V1 ≈ 0.4 V) and the
voltage V2 falls down to VSS; this would result in a large current through P3 and
therefore, N1 is forced to return quickly back to the triode region. After Vin falls
below the threshold VtL, P3 enters the triode region.
The relation I1 = Ib underlies the low threshold calculation. This time N 1
may operate in the moderate inversion or subthreshold region, depending on the
value of Ib, so the EKV model (Enz et al., 1995) should be used instead of (3).
For NMOS transistors with VBS = 0 V and VDS > 4VT, the model takes the form
66 Damian Imbrea

W 2 2 V  Vthn0 Cdep
I D  2n n Coxn VT ln (1  exp GS ),n  1  , (6)
L 2nVT Coxn
where n, Cdep and VT are, respectively, the slope factor, the surface depletion
capacitance and the thermal voltage. The slope factor n is technology-
dependent, taking values in the range [1.1, 1.8], and it decreases slightly with
increasing the difference VGS – Vthn0 (also called pinch-off voltage).
The low threshold is given by
 I b L1 
VtL  Vthn0  2nVT ln  exp  1 . (7)
 VT 2n n CoxnW1 
 
By taking the difference between (5) and (7) we obtain the hysteresis
value:

W3
2 I b   p Coxp (0.85VDD  Vthp0 )2 (1  3 0.2VDD )
L3
VtH  VtL  
W
n Coxn 1 (1  1 0.5VDD ) (8)
L1
 I b L1 
 2nVT ln  exp  1 .
 VT 2n n CoxnW1 
 
The bias current Ib has a greater influence on the low threshold; the high
threshold changes very little. Both switching thresholds and the hysteresis
depend on the process variations, supply voltage and temperature.
At high frequencies the following equation should be used instead of (2)
I1  I b  I 3  I C1 , (9)
where IC1 is the discharge current of capacitor C1; the high threshold VtH will
increase. The low threshold VtL should be calculated by using the relation
I1  I b  I C1 . (10)
This time the capacitor C1 has to be charged by a current derived from
the bias current Ib and thus, VtL will decrease.
The capacitor C2 determines a slight increase of VtH through the current
I3.

3. Simulation Results

Transient responses of the circuit to triangular rail-to-rail input voltages

of 50 MHz and 1 GHz are illustrated in Figs. 4 and 5, respectively. The high
 Bul. Inst. Polit. Iaşi, t. LXI (LXV), f. 2, 2015 67

threshold is almost insensitive to the bias current and increases with frequency.
The low threshold is sensitive to both bias current and frequency; in accordance
with (7), its dependence on current is not linear. The range of the bias current Ib
must be chosen depending on the input frequency.

Fig. 4 – Transient responses to 50 MHz input signal.

Fig. 5 – Transient responses to 1 GHz input signal.

The influences of the process variations, supply voltage and temperature

(PVT) on the two switching thresholds are shown in Figs. 6,…,8; the
simulations are performed at 1 GHz input frequency and 2 µA bias current.
68 Damian Imbrea

The low threshold VtL is more sensitive to the process variations than
the high threshold VtH. From ff corner to sf corner, VtL varies (approximately)
between 150 mV and 400 mV; VtH varies between 700 mV and 600 mV.
The changes in supply voltage (±100 mV) have a slightly higher
influence on the high threshold (about ±50 mV).
Both switching thresholds are weakly dependent on temperature; VtL is
slightly more sensitive and it decreases by less than 50 mV with increasing
temperature from –40 ºC to 125 ºC.

Fig. 6 – Switching thresholds versus process corners.

Fig. 7 – Switching thresholds versus supply voltage.

 Bul. Inst. Polit. Iaşi, t. LXI (LXV), f. 2, 2015 69

Fig. 8 – Switching thresholds versus temperature.

Fig. 9 shows the rise and fall times of the voltage V2, at 1 GHz input
frequency.

Fig. 9 – Rise and fall times corresponding to voltage V2.

The current consumption of the circuit at 1 GHz input frequency, in the

worst case conditions and 5 µA bias current is depicted in Fig. 10. The root
mean square of the supply current is about 50 µA.
70 Damian Imbrea

Fig. 10 – Supply current consumption.

The silicon area of the Schmitt trigger in Fig. 2, which includes the load
inverter Inv, is less than 21 µm2; the layout is illustrated in Fig. 11. The mirror
P4-P5 (situated in the upper part) occupies about half of the total area.

Fig. 11 – Layout view of the proposed Schmitt trigger.

For low-frequency applications the transistors can be sized differently.

The channel-length modulation effect can be eliminated by increasing the
transistor lengths.
 Bul. Inst. Polit. Iaşi, t. LXI (LXV), f. 2, 2015 71

4. Comparisons with Similar Works

The topology of the circuit proposed in this paper is a new one.

Comparisons between this work and the ones referenced in this paper are rather
difficult to do, because they provide too little information. However, some
comparisons with (Yuan 2010) can be done, even if the circuit described there
has a differential structure. The comparisons are listed in the Table 1.

Table 1
Comparisons
This work Yuan 2010
Process 65 nm CMOS std. 0.18 µm CMOS std.
Supply voltage [0.9, 1.1] V
1.8 V nominal
1 V nominal
Supply current 50 µA (rms)@1GHz
2.61 mA
consumption 200 µA (peak)@1GHz
PVT simulations shown not shown
Temperature range [-40, +125] ºC not shown
Max. input frequency 5 GHz not shown
Controlled thresholds low threshold both thresholds
(at low frequency) 0 < VtL < 0.54 V 0.95 V < VtL, VtH < 1.35 V
Max. hysteresis
0.54 V 0.23 V
(at low frequency)
Rise time 35 ps@1GHz
not shown
Fall time 61 ps@1GHz
Silicon area < 21 µm2 not shown

5. Conclusions

The new Schmitt trigger described in this work contains only 7 MOS
transistors of type 1.0V standard-Vt. The circuit is designed in 65 nm CMOS
standard process but can be implemented in any other technology. The silicon
area is about 21 µm2; also, the power consumption is quite small.
The circuit schematic consists of two inverters and two current sources;
one of the current sources is controlled by an external bias current that serves to
adjust the low switching threshold and also the hysteresis.
Simulations show that both switching thresholds are weakly dependent
on temperature. The process variations and supply voltage have greater
influences; their compensation up to a certain degree can be made through the
external bias current.
The circuit can be used in digital and analog applications up to 5 GHz
frequency.
72 Damian Imbrea

REFERENCES

Arith F.B., Mamun Md., Bhuiyan M.A.S., Bakar A.A.A., Low Voltage Schmitt Trigger
in 0.18 µm CMOS Technology. Advances in Natural and Applied Sciences, 7,
1, 33-38 (2013).
Dokic B. L., Cutting Edge Research in New Technologies. InTech, 2012.
Enz C.C., Krummenacher F., Vittoz E.A., An Analytical MOS Transistor Model Valid
in all Regions of Operation and Dedicated to Low-Voltage And Low-Current
Applications. J. Analog Integr. Circ. Sig. Process., 8, 1, 83-114 (1995).
Madhuri K., Srinivasulu A., Shaker C., Priyadarsini I., Two New CMOS Schmitt Trigger
Circuits Based on Current Sink and Pseudo Logic Structures. iC3S, 3, 18-21
(2012).
Saxena A., Shrivastava A., Akashe S., Estimation of High Performance in Schmitt
Triggers with Stacking Power-Gating Techniques in 45 nm CMOS Technology.
Internat. J. Commun. Syst., 27, 4369-4383 (2014).
Singhanath P., Suadet A., Kanjanop A., Thongleam T., Kuankid S., Kasemsuwan V.,
Low Voltage Adjustable CMOS Schmitt Trigger. ICMSAO, 1-4 (2011).
Yuan F., Differential CMOS Schmitt Trigger with Tunable Hysteresis. J. Analog Integr.
Circ. Sig. Process., 62, 245-248 (2010).

TRIGGER SCHMITT CMOS CU HISTEREZIS CONTROLAT ÎN CURENT

(Rezumat)

Se prezintă o nouă topologie de trigger Schmitt. Circuitul este proiectat într-o

tehnologie CMOS standard de 65 nm şi conţine 7 tranzistoare MOS cu tensiuni de prag
standard. Tensiunea de alimentare nominală este 1 V, cu toleranţa ±10%. Trigger-ul
funcţionează în gama de temperatură [–40, +125] ºC.
Schema circuitului conţine două inversoare; unul este alimentat direct de la
sursa de tensiune de 1 V iar celălalt este alimentat prin două surse de current, conectate
în paralel. O sursă de current este controlată din exteriorul circuitului cu un current de
polarizare de ordinul µA; prin intermediul acestuia se reglează pragul de comutare
inferior şi implicit histerezisul.
Pragurile de comutare sunt puţin dependente de temperatură; influenţe mai
mari asupra lor au variaţiile procesului tehnologic şi ale tensiunii de alimentare.
Circuitul ocupă o arie de siliciu de aproximativ 21 µm2, are un consum de
current relativ mic şi poate fi utilizat în diverse aplicaţii (analogice şi digitale).
Tensiunea de intrare a circuitului poate să aibă frecvenţe până la 5 GHz.