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Control

The document describes the instruction set architecture of a RISC-V processor. It lists 38 instructions organized by type (R, I, S, B, U, J) and shows their opcode, function, and control signal settings. The instructions include arithmetic, logical, load/store, branch, upper immediate, and jump operations. Control signals determine the execution unit, operands, and whether to write registers or memory.

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13 views10 pages

Control

The document describes the instruction set architecture of a RISC-V processor. It lists 38 instructions organized by type (R, I, S, B, U, J) and shows their opcode, function, and control signal settings. The instructions include arithmetic, logical, load/store, branch, upper immediate, and jump operations. Control signals determine the execution unit, operands, and whether to write registers or memory.

Uploaded by

NguyênNguyên
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as XLSX, PDF, TXT or read online on Scribd
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No Type Inst[30] Inst[14:12] Inst[6:2] BrEq BrLT PCSel

1R ADD 0 000 01100 x x 0


2R SUB 1 000 01100 x x 0
3R SLL 0 001 01100 x x 0
4R SLT 0 010 01100 x x 0
5R SLTU 0 011 01100 x x 0
6R XOR 0 100 01100 x x 0
7R SRL 0 101 01100 x x 0
8R SRA 1 101 01100 x x 0
9R OR 0 110 01100 x x 0
10 R AND 0 111 01100 x x 0

11 I ADDI x 000 00100 x x 0


12 I SLTI x 010 00100 x x 0
13 I SLTIU x 011 00100 x x 0
14 I XORI x 100 00100 x x 0
15 I ORI x 110 00100 x x 0
16 I ANDI x 111 00100 x x 0
17 I SLLI 0 001 00100 x x 0
18 I SRLI 0 101 00100 x x 0
19 I SRAI 1 101 00100 x x 0

20 I LB x 000 00000 x x 0
21 I LH x 001 00000 x x 0
22 I LW x 010 00000 x x 0
23 I LBU x 100 00000 x x 0
24 I LHU x 101 00000 x x 0

25 S SB x 000 01000 x x 0
26 S SH x 001 01000 x x 0
27 S SW x 010 01000 x x 0

0 0
28 B BEQ x 000 11000 x
1 1
0 1
29 B BNE x 001 11000 x
1 0
0 0
30 B BLT x 100 11000 x
1 1
0 1
31 B BGE x 101 11000 x
1 0
0 0
32 B BLTU x 110 11000 x
1 1
0 1
33 B BGEU x 111 11000 x
1 0
34 U LUI x x 01101 x x 0
35 U AUIPC x x 00101 x x 0

36 J JAL x x 11011 x x 1
37 J JALR x 000 11001 x x 1
ImmSel RegWEn BrUn Bsel Asel ALUSel MemRW WBSel
x 1x 0 0 0000 0 01
x 1x 0 0 0001 0 01
x 1x 0 0 0010 0 01
x 1x 0 0 0011 0 01
x 1x 0 0 0100 0 01
x 1x 0 0 0101 0 01
x 1x 0 0 0110 0 01
x 1x 0 0 0111 0 01
x 1x 0 0 1000 0 01
x 1x 0 0 1001 0 01

I 1x 1 0 0000 0 01
I 1x 1 0 0011 0 01
I 1x 1 0 0100 0 01
I 1x 1 0 0101 0 01
I 1x 1 0 1000 0 01
I 1x 1 0 1001 0 01
I 1x 1 0 0010 0 01
I 1x 1 0 0110 0 01
I 1x 1 0 0111 0 01

I 1x 1 0 0000 0 00
I 1x 1 0 0000 0 00
I 1x 1 0 0000 0 00
I 1x 1 0 0000 0 00
I 1x 1 0 0000 0 00

S 0x 1 0 0000 1x
S 0x 1 0 0000 1x
S 0x 1 0 0000 1x

B 0x 1 1 0000 0x

B 0x 1 1 0000 0x

B 0 0 1 1 0000 0x

B 0 0 1 1 0000 0x

B 0 1 1 1 0000 0x

B 0 1 1 1 0000 0x
U 1x 1x 1010 0 01
U 1x 1 1 0000 0 01

J 1x 1 1 0000 0 10
I 1x 1 0 0000 0 10
ALUSel Imm_Sel
0000 ADD I 000
0001 SUB S 001
0010 SLL B 010
0011 SLT U 011
0100 SLTU J 100
0101 XOR
0110 SRL
0111 SRA
1000 OR
1001 AND
1010 BUFFER

PCSel
0 PC+4
1 ALU

BrEq
0 unbranch
1 branch

BrLT
0 greater
1 less

BrUn
0 signed
1 unsigned

Asel
0 Reg
1 PC

Bsel
0 Reg
1 Imm[31:0]

RegWEn MemRW

0 0

1 Write to reg 1 Write to mem


WBSel
00 mem
01 ALU
10 PC+4

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