Applying the New CMOS MICRO-DACs

National Semiconductor
Applying the New CMOS Application Note 271
MICRO-DAC TM Tim Regan
September 1981

Most microprocessor based systems designers will find that In the application circuits that follow, the connections for the
the new CMOS MICRO-DAC are among the most interest- control pins for the actual digital interface are omitted for
ing and versatile devices they will include in their system. simplicity. Several methods of configuring the DAC to ac-
The availability of these devices opens a vast new area of cept its inputs from a processor exist and are described on
applications where the microprocessor can provide an intel- the data sheets. The actual method used depends on the
ligent controlling function in the analog world. Traditional overall system provisions and requirements. The digital in-
analog control devices, primarily potentiometers and put code is referred to as D and represents the decimal
switches which require a time-consuming and often errone- equivalent of the binary input. For example, D would range
ous human interface, can often be replaced by a processor from 0 to 4095 in steps of 1 to describe the full range of
and DACs to perform precise and automatic controls. A little digital inputs for a 12-bit MICRO-DAC. Any of the MICRO-
creative thinking can easily generate several functions that DAC can be used in any of the circuits shown, depending on
could be better performed automatically. The purpose of accuracy and/or resolution requirements.
this note is to stimulate this thought and to illustrate the
THE DIGITAL POTENTIOMETER
versatility of CMOS DACs to achieve results.
The most common and basic application of a DAC is gener-
The use of CMOS processing in the fabrication of the MI-
ating discrete voltage output levels within a given span, and
CRO-DAC offers several important features. The primary
serving in essence as an attenuator (Figure 2 ). The applied
advantage is that the current switching R-2R ladder net-
digital input word multiplies the applied reference voltage,
work, used for the actual D to A conversion, can conduct
and the output voltage is this product normalized to the
current in both directions (sourcing or sinking current at its
DAC’s resolution. The op amp shown is used to convert the
analog output) to control either a positive or negative fixed
output current from the DAC to a voltage via a feedback
voltage reference or an AC signal. In addition, all of the
resistor included in the DAC (RfB). This output current
necessary digital input conditioning circuitry to permit a di-
ranges from a near zero output leakage (on the order of 10
rect microprocessor interface with no additional logic devic-
nA) for an applied code of all zeros (D e 0), to a full-scale
es needed is included with minimal device power require-
value (D e 2nb1, where n is the DAC’s bits of resolution) of
ments. All of the MICRO-DAC can be controlled from an 8-
VREF divided by the R value of the internal R-2R ladder
bit data bus regardless of the number of digital inputs for a
network (nominally 15 kX). The current at IOUT 2 is equal to
particular device. The operation of the R-2R ladder and the
that caused by the one’s complement of the applied digital
digital interface signal requirements are explained in detail
input, so while IOUT 1 is at full-scale, IOUT 2 will be zero.
on the actual device data sheets.
Note that the output voltage is the opposite polarity of the
Resolution and linearity are the most important characteris- applied reference voltage, but since CMOS DACs can ac-
tics of the analog output of any D to A. Linearity is important cept bipolar reference voltages, if a positive output is need-
to insure that each and every analog output quantity is pre- ed, a negative reference can be applied. To preserve the
dictable within a given tolerance (specified as a percent of linearity of the output, the two current output pins of the
the full-scale range) for any applied digital word. Resolution DAC must be as close to 0V as possible, which requires the
defines the number of possible analog output quantities input offset voltage of the op amp to be nulled. The amount
available within a given range. Higher resolution in a DAC of linearity error degradation is approximately VOS d VREF.
serves to minimize the gaps in the analog output inherent in For AC signal attenuation, in audio applications for example,
digitally-based controls. The new line of MICRO-DAC offers the DAC’s linearity over the full range of the applied refer-
a wide variety of converters to fit the accuracy and resolu- ence voltage, even as it passes through zero, is sufficiently
tion requirements of a great number of applications. The good enough to distort a 10V peak sine wave by only
device part numbers are summarized in Figure 1 . 0.004%.
Resolution
Linearity Error
8 Bits 10 Bits 12 Bits
(% of Full-Scale) 256 Output 1024 Output 4096 Output
Steps Steps Steps
g 0.012% DAC1208,
DAC1230
g 0.024% DAC1209,
DAC1231
g 0.05% DAC0830 DAC1000, DAC1210,
DAC1006 DAC1232
g 0.1% DAC0831 DAC1001,
AN-271

DAC1007
g 0.2% DAC0832 DAC1002,
DAC1008
MICRO-DACTM and BI-FETTM are trade-
marks of National Semiconductor Corp. FIGURE 1. The MICRO-DAC Family
C1995 National Semiconductor Corporation TL/H/5629 RRD-B30M115/Printed in U. S. A.
The feedback capacitor shown in Figure 2 is added to im- The low cost, high resolution, and stability with time and
prove the settling time of the output as the input code is temperature of the MICRO-DAC allow precise output levels
changed. With no compensation, a fair amount of overshoot that rival the capability of the best multiple turn potentiome-
and ringing appears at the output due to a feedback pole ters, and can automatically be adjusted, as required, by a
formed by the feedback resistor, and the output capaci- controlling microprocessor.
tance of the DAC, which appears from the (b) input of the
LEVEL SHIFTING THE OUTPUT RANGE
op amp ground.
As shown in Figure 4 , the zero code output of the DAC can
It is most desirable to select an op amp for use with the
be shifted, if desired, to any level by summing a fixed cur-
MICRO-DAC which combines good DC characteristics, pri-
rent to the DAC’s current output terminal, offsetting the out-
marily low VOS and low VOS drift, with fast AC characteris-
put voltage of the op amp. The applied reference voltage
tics such as slew rate, settling time and bandwidth. Such a
now serves as the output span controller and is fractionally
combination is difficult to find in a single op amp for use with
added to the output as a function of the applied code.
the higher accuracy 12-bit DACs. Figure 3 shows an op amp
configuration which combines the excellent DC input char-
acteristics of the LM11 with the fast response of an LF351
BI-FETTM op amp.

b VREFD
VOUT e
256
for 0 s D s 255

FIGURE 2. The Digital Pot

Settling time & 8mS

for a zero to full-
scale transition

FIGURE 3. Composite Amplifier for Good DC Characteristics and Fast Output Response

TL/H/5629 – 1

Ð (
RfB D
VOUT e b VREF a
FIGURE 4. Level Shifted Output R1 256

2
SINGLE SUPPLY OPERATION linearity can be obtained in this circuit with the 8 and 10-bit
The R-2R ladder can be operated as a voltage switching MICRO-DAC, but is difficult because of the very low value
network to circumvent the output voltage inversion inherent reference required with the 12-bit parts. The resistance to
in the current switching mode. This allows single supply op- ground of the VREF terminal is nominally 15 kX, indepen-
eration. In Figure 5 , the reference voltage is applied to the dent of the digital input code.
IOUT 1 terminal, and is attenuated by the R-2R ladder in BIPOLAR OUTPUT FROM A FIXED REFERENCE
proportion to the applied code, and output to the VREF ter- VOLTAGE
minal with no phase inversion. To insure linear operation in
The use of a second op amp in the analog output circuitry
this mode, the applied reference voltage must be kept less
can provide a bipolar output swing from a fixed reference
than 3V for the 10-bit DACs or less than 5V for the 8-bit
voltage. This, in effect, gives sign significance to the MSB of
DACs. The applied supply voltage to the DAC must be at
the digital input word to allow 2-quadrant multiplication of
least 10V more positive than the reference voltage to insure
the reference voltage. The polarity of the reference can still
that the CMOS ladder switches have enough voltage over-
be reversed or be an AC signal to realize full 4-quadrant
drive to fully turn on. An external op amp can be added to
multiplication. This circuit is shown in Figure 6 .
provide gain to the DAC output voltage for a wide overall
output span. Only the input offset voltage of amplifier OA 1 needs to be
nulled to preserve the linearity of the DAC. The offset of OA
The zero code output voltage is limited by the low level
2 will affect only absolute accuracy of the output voltage.
output saturation voltage of the op amp. The 2 kX load
resistor helps to minimize this voltage. Specified DAC

Ð 1024 (
4D
VOUT e a VREF

FIGURE 5. Single Supply Operation

TL/H/5629 – 2

(D b 128)
VOUT e VREF
128

*These resistors are available from Input Code Ideal VOUT

Beckman Instruments, Inc. as their
part no. 694-3-R10K-Q MSB . . . LSB a VREF b VREF

1 LSB e
lVREFl 1 1 1 1 1 1 1
VREF b 1 LSB 1 b l VREF l a 1 LSB
128
1 1 0 0 0 0 0
VREF/2 0 b l VREF l /2
1 0 0 0 0 0 00 0 0
0 1 1 1 1 1 1
b 1 LSB 1 a 1 LSB

0 0 1 1 1 1 1 1 b
lVREFl b 1 LSB lVREFl a 1 LSB
2 2
0 0 0 0 0 0 0 0 b l VREF l a l VREF l

FIGURE 6. Bipolar Output from a Fixed Reference Voltage

3
DAC CONTROLLED AMPLIFIER CAPACITANCE MULTIPLIER
In the circuit of Figure 7 , the DAC is used as the feedback The DAC controlled amplifier can be used in a capacitance
element for an inverting amplifier configuration. The R–2R multiplier circuit to give a processor control of a system’s
ladder digitally adjusts the amount of output signal fed back time or frequency domain response. The circuit in Figure 8
to the amplifier’summing junction. The feedback resistance uses the DAC to adjust the gain of a stage with a fixed
can be thought of as varying from j 15 kX to % as the capacitive feedback, creating a Miller equivalent input ca-
input code changes from full-scale to zero. The internal RfB pacitance of the fixed capacitance times 1 a the amplifier’s
is used as the amplifier’s input resistor. It is important to gain. The voltage across the equivalent input capacitance to
note that when the input code is all zeros the feedback loop ground is limited to the maximum output voltage of op amp
is opened and the op amp output will saturate. A1, divided by 1 a 2n/D, where n is the DAC’s bits of
resolution.

b VIN(1024)
VOUT e
D

FIGURE 7. DAC Controlled Amplifer

TL/H/5629 – 3

# J
256
CEQUIV e C1 1a
D

FIGURE 8. Capacitance Multiplier

4
HIGH VOLTAGE OUTPUT The output current of these circuits is limited to that of the
Many DAC applications involve the generation of high volt- LM143, typically 20 mA. If higher voltage and/or higher out-
age levels to be used for deflection plate driving, high volt- put current is needed, a discrete power stage can be used,
age motor speed, or position control. All of the MICRO-DAC as shown in Figure 10 .
can control as much as g 25V applied to the reference ter- To insure accuracy with these high voltage circuits, concern
minal, but guaranteed performance is specified at no more for the power dissipation and temperature coefficients of
than g 10V. Since the output amplifier serves as a current- the resistors used to increase the output voltage is neces-
to-voltage converter, increasing the effective feedback re- sary. The T-network configuration shown in Figure 10 reduc-
sistance directly increases the amplifier’s output voltage for es the dependence of the output voltage to temperature
a given DAC output current. Use of a high voltage op amp, changes by reducing the significance of the tracking require-
the LM143 with 80V supply capability for example, can ac- ments of the external resistors to the internal RfB resistor.
commodate this increased gain and allow the use of refer- Using two resistors with similar temperature coefficients for
ence voltage within the DAC’s specified limits. Figure 9 illus- R1 and R2, and making their ratio dominant in setting the
trates how higher voltage outputs can be obtained for both overall gain provide the most stable results.
unipolar and bipolar requirements.
a) Unipolar Output

b VRD
VOUT e (RfB a R1)
1024
0 s VOUT s 50V

b) Bipolar Output

(D b 512) 3 VR
VOUT e
512

FIGURE 9. Unipolar and Bipolar Voltage Boosting

Ð1 (
b VREFD R2 R2
VOUT e a a
4096 RfB R1
TL/H/5629 – 4
FIGURE 10. High Voltage Power DAC

5
HIGH CURRENT CONTROLLER The entire circuit ‘‘floats’’ by operating at whatever ground
The MICRO-DAC can also be used to linearly control cur- reference potential is required by the total loop resistance
rent flow useful in applications such as automatic test sys- and loop current. To insure proper operation, the voltage
tems, stepper-motor torque compensation, and heater con- differential between the input and output terminals must be
trols. Figure 11 illustrates the use of a DAC1230 controlling kept in the range of 16V to 55V, and the digital inputs to the
a 0A to 1A current sink. The largest source of nonlinearity in DAC must be electrically isolated from the ground potential
this circuit is the stability of the current sensing resistance of the controlling processor. This isolation can best be
with changes in its power dissipation. To minimize this ef- achieved with opto-isolators switching the digital inputs to
fect, the sensing resistance should be kept as low as possi- the ground potential of the DAC for a logic low level.
ble. To maintain the output current range, the reference In a non-microprocessor based system where the loop con-
voltage to the DAC must be reduced. The flexible reference trolling information comes from thumbwheel switches, the
requirements of the MICRO-DAC permit the application of a digital input data for the DAC can be derived from BCD to
lower reference with no degradation in linearity. A triple Dar- binary CMOS logic circuitry, which is ground referenced to
lington is used to minimize the base current term flowing the ground potential of the DAC. The total supply current
through the sense resistor, but not into the collector termi- requirements of all circuits used must, of course, be less
nal. than 4 mA, and the value of R1 could be adjusted accord-
ingly.
4 ma to 20 mA CURRENT LOOP CONTROLLER
The standard 4 mA b20 mA industrial process current loop TARE COMPENSATION/AUTO-ZEROING
controller is an application where automatic, microproces- Probably the most popular application of D to A converters
sor directed operation is often required, and is a natural is in auto-zeroing or auto-referencing. In these systems the
application for D to A converters. The low power require- DAC is called upon to hold an output voltage used to offset
ments of the CMOS MICRO-DAC allow the design of a con- the analog input range of an A to D converter. This is done
troller that is powered directly from the loop it is controlling. to reserve the full input range of the A to D for analog volt-
Figure 12 illustrates a 2-terminal floating 4 mA to 20 mA ages starting from reference potential to a full-scale value
controller. relative to that reference voltage. A common example of
In this circuit, the output transistor will conduct whatever this is Tare Compensation in a weighing system where the
current is necessary to keep the voltage across R3 equal to weight of the scale platform, and possibly a container, is
the voltage across R2. This voltage, and therefore the total subtracted automatically from the total weight being mea-
loop current, is directly proportional to the output current sured. This, in effect, expands the range of weight that
from the DAC. the net resistance of R1 is used to set the could be measured by preventing a premature full-scale
zero code loop current to 4 mA, and R2 is adjusted to pro- reading, and allows an automatic indication of the actual
vide the 16 mA output span with a full-scale DAC code. unknown quantity.

1A (D)
IO e
4096

TL/H/5629 – 5
FIGURE 11. High Current Controller

6
Figure 13 illustrates this basic technique. In this system the A/D’s input, to zero. The DAC’s output is held constant so
DAC would initially be given a zero code and the system’s that any subsequent A/D conversions will yield a value rela-
input would be set to some reference quantity. A conversion tive in magnitude to the initial reference quantity. To insure
of this input would be performed, then the corresponding that the output code from the A to D generates the proper
code would be applied to the DAC. The output of the DAC DAC output voltage, the two devices should be driven from
will be equal to and of the opposite polarity as the input the same reference voltage.
voltage to force the amplifier’s output, and therefore the

Ð R1 ( Ð1 (
1 D R2
IOUT e VREF a a
256 RfB R3
FIGURE 12. Two-Terminal 4 mAb20 mA Current Loop Controller

TL/H/5629 – 6
FIGURE 13. Basic Tare Compensation

7
For differential input signals, an instrumentation amplifier is completed, the voltage at the reference pin of the instru-
such as the LM363 can be used. The output reference pin mentation amplifier will be equal to and of the opposite po-
of this amplifier can be driven directly by the DAC’s output larity of the amplifier’s offset voltage, multiplied by the gain.
amplifier to offset the A to D input. Details of the A/D’s operation in this mode and an example
Auto-zeroing is the unique case of auto-referencing where of a microprocessor successive approximation routine can
the reference input is the zero or null condition. This tech- be found on the ADC0801 data sheet.
nique essentially shorts out or electrically simulates a bal- D TO A CONVERTER WITH A VERNIER ADJUSTMENT
ance of the system’s input device, and uses a DAC to cor-
In many systems it is required that an analog voltage be
rect for offset errors contributed by the signal conditioning
generated as a controlling function by a processor, when
amplification stage. Since amplifier errors are generally
only an approximate value is known, with the exact value
much lower in magnitude than the signal after being ampli-
dependent on feedback from the controlled device. In this
fied, and can be of either polarity when applied to the A/D, a
case, the processor could output an 8-bit ‘‘coarse’’ word to
bipolar output configuration utilizing a CMOS DAC (Figure 6 )
the 8 MSBs of a 12-bit DAC. Then the 4 LSBs could be
driven from a reduced reference voltage can null the offset
incremented or decremented by an up/down counter to
errors to within microvolts of zero. This is illustrated in Fig-
serve as a 16 LSB dither or vernier, which would stop when
ure 14 for an LM363 differential amplification stage.
external sensing circuitry detected the actual desired value.
The auto-zeroing routine performed by the processor is es- The DAC1208 can be used in just such a system, as shown
sentially a successive approximation routine which utilizes in Figure 15 . The digital input circuitry of this device
the A/D converter as a high resolution comparator, a fea-
ture unique to the ADC0801 A/D shown. When the routine

SW2 and SW4 closed for auto-zeroing

SW1 and SW3 closed for signal measurement

FIGURE 14. Auto-Zeroing

TL/H/5629 – 7
FIGURE 15. 8-Bit Coarse, 4-Bit Vernier DAC

8
provides all 12 input lines with separate registers for the 8 Linearity of the output frequency versus the applied digital
MSBs and the 4 LSBs. The register for the 4 LSBs can be input code is as good as the DAC up to 30 kHz, where the
configured to flow through so that the output will always propagation delay through the LM319 comparator starts
reflect the state of the counter’s output. adding non-linearity.
DAC CONTROLLED FUNCTION GENERATOR Integrating capacitor, C1, is selected for the maximum out-
put frequency which occurs with a full-scale input code
CMOS DACs find wide use in the synthesis of periodic
when the DAC provides its maximum output current. A prob-
waveforms from digital information primarily for their preci-
lem in selecting this capacitor is that the R value of the
sion and flexibility in controlling magnitude and timing pa-
internal R-2R ladder can vary over the range of 10 kX to 20
rameters. If the signal generated is used as an excitation for
kX. This can be accommodated by adjusting the amount of
a system, the data is readily available for a processor to
positive feedback around the comparator to provide the de-
know precisely where the input is to enable it to interpret the
sired maximum frequency for a given capacitor. This adjust-
output response of the system. Typically, the data required
ment also alters the amplitude of the triangle wave, but this
to generate the amplitude information resides in the system
can be attenuated or amplified as required to achieve any
ROM and the frequency is controlled by the rate at which
desired amplitude.
the DAC is updated. Some of the more typical waveforms
include sin, square, sawtooth ramps or staircases, and trian- The sine wave output is derived from the triangle wave by
gles. virtue of the non-linear conduction characteristics of the
transistors used in the shaper circuit. The wave-shape ad-
Figure 16 shows the implementation of a MICRO-DAC pro-
justment is used to obtain minimum distortion of the sine
viding frequency control of a sine, square and triangle func-
wave output and should be adjusted after the triangle wave
tion generator. The DAC is used as a digitally programmable
output is established.
input resistor for an integrator. The bipolar nature of the
reference input is important to the generation of a symmetri- The square wave output is a 50% duty cycle, symmetrical
cal triangle wave and a symmetrically clamped square g 7V signal. Since only (/2 of the LM319 dual comparator is
wave. This allows the integrating capacitor to be ground used, the other side can be used to provide TTL or CMOS
referenced with equal charging and discharging currents. logic compatible output if needed.

# C1 controls maximum frequency

# k 0.5% sine wave THD over range
# Range 30 kHz maximum
# LinearityÐDAC limit
D
# fe
4096 (4/3 RfB C)

TL/H/5629 – 8
FIGURE 16. DAC Controlled Function Generator

9
For DAC controlled amplitude versatility, the basic unipolar 2. Low power consumption CMOS circuitry (20 mW typ).
configuration (Figure 2 ) can be used at any or all of the 3. Direct microprocessor interface with the necessary con-
outputs. trolling logic designed in. All parts are 8-bit bus compati-
LOGARITHMIC AMPLIFIER WITH A PROGRAMMABLE ble.
SCALE FACTOR 4. TTL compatible digital input thresholds independent of
Sensors that operate over a wide dynamic range, such as the DAC’s VCC supply.
photomultiplier tubes, often require signal compression via 5. Linearity is guaranteed over temperature following a sim-
logarithmic amplifiers. Figure 17 shows a logging amplifier ple zero and full-scale adjustment procedure.
with a digitally programmable output scale factor from 10 6. The current outputs, IOUT 1 and IOUT 2, want to be at
mV/decade to 10V/decade over an input voltage range of ground potential.
100 mV to 10V, or an input current range of 10 nA to 1 mA.
7. IOUT 1 should always be used in conjunction with the in-
The DAC1006 is used as the scaling element to attenuate
ternally provided feedback resistor, as this resistor
or amplify the logarithmic output.
matches and tracks with temperature the resistors used
SUMMARY in the R-2R ladder network.
The circuits described in this note illustrate only a very small 8. The internal R value can vary over a 10 kX to 20 kX
percentage of possible MICRO-DAC applications. The key range.
points to remember when considering the use of one of 9. The 12-bit MICRO-DAC are not recommended for use in
these devices are summarized below. the voltage switching mode.
1. The reference voltage can be a bipolar AC or DC signal
within the range of 25V with specified linearity guaranteed
at g 10V and g 1V.

TL/H/5629 – 9
*Tel Labs Q81 ( a 0.3%/§ C)
**Adjust for 10V/dec output sensitivity
at full-scale input code

10D VIN
VOUT e log
1024 VREF

FIGURE 17. Logarithmic Amplifier with Digitally Programmable Scale Factor

10
11
Applying the New CMOS MICRO-DACs

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with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
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AN-271

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